1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/lm32_dcache.v Sun Apr 04 20:40:03 2010 +0100 1.3 @@ -0,0 +1,533 @@ 1.4 +// ============================================================================= 1.5 +// COPYRIGHT NOTICE 1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 +// ALL RIGHTS RESERVED 1.8 +// This confidential and proprietary software may be used only as authorised by 1.9 +// a licensing agreement from Lattice Semiconductor Corporation. 1.10 +// The entire notice above must be reproduced on all authorized copies and 1.11 +// copies may only be made to the extent permitted by a licensing agreement from 1.12 +// Lattice Semiconductor Corporation. 1.13 +// 1.14 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.15 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.16 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.17 +// U.S.A email: techsupport@latticesemi.com 1.18 +// =============================================================================/ 1.19 +// FILE DETAILS 1.20 +// Project : LatticeMico32 1.21 +// File : lm32_dcache.v 1.22 +// Title : Data cache 1.23 +// Dependencies : lm32_include.v 1.24 +// Version : 6.1.17 1.25 +// : Initial Release 1.26 +// Version : 7.0SP2, 3.0 1.27 +// : No Change 1.28 +// Version : 3.1 1.29 +// : Support for user-selected resource usage when implementing 1.30 +// : cache memory. Additional parameters must be defined when 1.31 +// : invoking lm32_ram.v 1.32 +// ============================================================================= 1.33 + 1.34 +`include "lm32_include.v" 1.35 + 1.36 +`ifdef CFG_DCACHE_ENABLED 1.37 + 1.38 +`define LM32_DC_ADDR_OFFSET_RNG addr_offset_msb:addr_offset_lsb 1.39 +`define LM32_DC_ADDR_SET_RNG addr_set_msb:addr_set_lsb 1.40 +`define LM32_DC_ADDR_TAG_RNG addr_tag_msb:addr_tag_lsb 1.41 +`define LM32_DC_ADDR_IDX_RNG addr_set_msb:addr_offset_lsb 1.42 + 1.43 +`define LM32_DC_TMEM_ADDR_WIDTH addr_set_width 1.44 +`define LM32_DC_TMEM_ADDR_RNG (`LM32_DC_TMEM_ADDR_WIDTH-1):0 1.45 +`define LM32_DC_DMEM_ADDR_WIDTH (addr_offset_width+addr_set_width) 1.46 +`define LM32_DC_DMEM_ADDR_RNG (`LM32_DC_DMEM_ADDR_WIDTH-1):0 1.47 + 1.48 +`define LM32_DC_TAGS_WIDTH (addr_tag_width+1) 1.49 +`define LM32_DC_TAGS_RNG (`LM32_DC_TAGS_WIDTH-1):0 1.50 +`define LM32_DC_TAGS_TAG_RNG (`LM32_DC_TAGS_WIDTH-1):1 1.51 +`define LM32_DC_TAGS_VALID_RNG 0 1.52 + 1.53 +`define LM32_DC_STATE_RNG 2:0 1.54 +`define LM32_DC_STATE_FLUSH 3'b001 1.55 +`define LM32_DC_STATE_CHECK 3'b010 1.56 +`define LM32_DC_STATE_REFILL 3'b100 1.57 + 1.58 +///////////////////////////////////////////////////// 1.59 +// Module interface 1.60 +///////////////////////////////////////////////////// 1.61 + 1.62 +module lm32_dcache ( 1.63 + // ----- Inputs ----- 1.64 + clk_i, 1.65 + rst_i, 1.66 + stall_a, 1.67 + stall_x, 1.68 + stall_m, 1.69 + address_x, 1.70 + address_m, 1.71 + load_q_m, 1.72 + store_q_m, 1.73 + store_data, 1.74 + store_byte_select, 1.75 + refill_ready, 1.76 + refill_data, 1.77 + dflush, 1.78 + // ----- Outputs ----- 1.79 + stall_request, 1.80 + restart_request, 1.81 + refill_request, 1.82 + refill_address, 1.83 + refilling, 1.84 + load_data 1.85 + ); 1.86 + 1.87 +///////////////////////////////////////////////////// 1.88 +// Parameters 1.89 +///////////////////////////////////////////////////// 1.90 + 1.91 +parameter associativity = 1; // Associativity of the cache (Number of ways) 1.92 +parameter sets = 512; // Number of sets 1.93 +parameter bytes_per_line = 16; // Number of bytes per cache line 1.94 +parameter base_address = 0; // Base address of cachable memory 1.95 +parameter limit = 0; // Limit (highest address) of cachable memory 1.96 + 1.97 +localparam addr_offset_width = clogb2(bytes_per_line)-1-2; 1.98 +localparam addr_set_width = clogb2(sets)-1; 1.99 +localparam addr_offset_lsb = 2; 1.100 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1); 1.101 +localparam addr_set_lsb = (addr_offset_msb+1); 1.102 +localparam addr_set_msb = (addr_set_lsb+addr_set_width-1); 1.103 +localparam addr_tag_lsb = (addr_set_msb+1); 1.104 +localparam addr_tag_msb = clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1; 1.105 +localparam addr_tag_width = (addr_tag_msb-addr_tag_lsb+1); 1.106 + 1.107 +///////////////////////////////////////////////////// 1.108 +// Inputs 1.109 +///////////////////////////////////////////////////// 1.110 + 1.111 +input clk_i; // Clock 1.112 +input rst_i; // Reset 1.113 + 1.114 +input stall_a; // Stall A stage 1.115 +input stall_x; // Stall X stage 1.116 +input stall_m; // Stall M stage 1.117 + 1.118 +input [`LM32_WORD_RNG] address_x; // X stage load/store address 1.119 +input [`LM32_WORD_RNG] address_m; // M stage load/store address 1.120 +input load_q_m; // Load instruction in M stage 1.121 +input store_q_m; // Store instruction in M stage 1.122 +input [`LM32_WORD_RNG] store_data; // Data to store 1.123 +input [`LM32_BYTE_SELECT_RNG] store_byte_select; // Which bytes in store data should be modified 1.124 + 1.125 +input refill_ready; // Indicates next word of refill data is ready 1.126 +input [`LM32_WORD_RNG] refill_data; // Refill data 1.127 + 1.128 +input dflush; // Indicates cache should be flushed 1.129 + 1.130 +///////////////////////////////////////////////////// 1.131 +// Outputs 1.132 +///////////////////////////////////////////////////// 1.133 + 1.134 +output stall_request; // Request pipeline be stalled because cache is busy 1.135 +wire stall_request; 1.136 +output restart_request; // Request to restart instruction that caused the cache miss 1.137 +reg restart_request; 1.138 +output refill_request; // Request a refill 1.139 +reg refill_request; 1.140 +output [`LM32_WORD_RNG] refill_address; // Address to refill from 1.141 +reg [`LM32_WORD_RNG] refill_address; 1.142 +output refilling; // Indicates if the cache is currently refilling 1.143 +reg refilling; 1.144 +output [`LM32_WORD_RNG] load_data; // Data read from cache 1.145 +wire [`LM32_WORD_RNG] load_data; 1.146 + 1.147 +///////////////////////////////////////////////////// 1.148 +// Internal nets and registers 1.149 +///////////////////////////////////////////////////// 1.150 + 1.151 +wire read_port_enable; // Cache memory read port clock enable 1.152 +wire write_port_enable; // Cache memory write port clock enable 1.153 +wire [0:associativity-1] way_tmem_we; // Tag memory write enable 1.154 +wire [0:associativity-1] way_dmem_we; // Data memory write enable 1.155 +wire [`LM32_WORD_RNG] way_data[0:associativity-1]; // Data read from data memory 1.156 +wire [`LM32_DC_TAGS_TAG_RNG] way_tag[0:associativity-1];// Tag read from tag memory 1.157 +wire [0:associativity-1] way_valid; // Indicates which ways are valid 1.158 +wire [0:associativity-1] way_match; // Indicates which ways matched 1.159 +wire miss; // Indicates no ways matched 1.160 + 1.161 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_read_address; // Tag memory read address 1.162 +wire [`LM32_DC_TMEM_ADDR_RNG] tmem_write_address; // Tag memory write address 1.163 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_read_address; // Data memory read address 1.164 +wire [`LM32_DC_DMEM_ADDR_RNG] dmem_write_address; // Data memory write address 1.165 +wire [`LM32_DC_TAGS_RNG] tmem_write_data; // Tag memory write data 1.166 +reg [`LM32_WORD_RNG] dmem_write_data; // Data memory write data 1.167 + 1.168 +reg [`LM32_DC_STATE_RNG] state; // Current state of FSM 1.169 +wire flushing; // Indicates if cache is currently flushing 1.170 +wire check; // Indicates if cache is currently checking for hits/misses 1.171 +wire refill; // Indicates if cache is currently refilling 1.172 + 1.173 +wire valid_store; // Indicates if there is a valid store instruction 1.174 +reg [associativity-1:0] refill_way_select; // Which way should be refilled 1.175 +reg [`LM32_DC_ADDR_OFFSET_RNG] refill_offset; // Which word in cache line should be refilled 1.176 +wire last_refill; // Indicates when on last cycle of cache refill 1.177 +reg [`LM32_DC_TMEM_ADDR_RNG] flush_set; // Which set is currently being flushed 1.178 + 1.179 +genvar i, j; 1.180 + 1.181 +///////////////////////////////////////////////////// 1.182 +// Functions 1.183 +///////////////////////////////////////////////////// 1.184 + 1.185 +`include "lm32_functions.v" 1.186 + 1.187 +///////////////////////////////////////////////////// 1.188 +// Instantiations 1.189 +///////////////////////////////////////////////////// 1.190 + 1.191 + generate 1.192 + for (i = 0; i < associativity; i = i + 1) 1.193 + begin : memories 1.194 + // Way data 1.195 + if (`LM32_DC_DMEM_ADDR_WIDTH < 11) 1.196 + begin : data_memories 1.197 + lm32_ram 1.198 + #( 1.199 + // ----- Parameters ------- 1.200 + .data_width (32), 1.201 + .address_width (`LM32_DC_DMEM_ADDR_WIDTH), 1.202 +`ifdef CFG_DCACHE_DAT_USE_DP_TRUE 1.203 + .RAM_IMPLEMENTATION ("EBR"), 1.204 + .RAM_TYPE ("RAM_DP_TRUE") 1.205 +`else 1.206 + `ifdef CFG_DCACHE_DAT_USE_SLICE 1.207 + .RAM_IMPLEMENTATION ("SLICE") 1.208 + `else 1.209 + .RAM_IMPLEMENTATION ("AUTO") 1.210 + `endif 1.211 +`endif 1.212 + ) way_0_data_ram 1.213 + ( 1.214 + // ----- Inputs ------- 1.215 + .read_clk (clk_i), 1.216 + .write_clk (clk_i), 1.217 + .reset (rst_i), 1.218 + .read_address (dmem_read_address), 1.219 + .enable_read (read_port_enable), 1.220 + .write_address (dmem_write_address), 1.221 + .enable_write (write_port_enable), 1.222 + .write_enable (way_dmem_we[i]), 1.223 + .write_data (dmem_write_data), 1.224 + // ----- Outputs ------- 1.225 + .read_data (way_data[i]) 1.226 + ); 1.227 + end 1.228 + else 1.229 + begin 1.230 + for (j = 0; j < 4; j = j + 1) 1.231 + begin : byte_memories 1.232 + lm32_ram 1.233 + #( 1.234 + // ----- Parameters ------- 1.235 + .data_width (8), 1.236 + .address_width (`LM32_DC_DMEM_ADDR_WIDTH), 1.237 +`ifdef CFG_DCACHE_DAT_USE_DP_TRUE 1.238 + .RAM_IMPLEMENTATION ("EBR"), 1.239 + .RAM_TYPE ("RAM_DP_TRUE") 1.240 +`else 1.241 + `ifdef CFG_DCACHE_DAT_USE_SLICE 1.242 + .RAM_IMPLEMENTATION ("SLICE") 1.243 + `else 1.244 + .RAM_IMPLEMENTATION ("AUTO") 1.245 + `endif 1.246 +`endif 1.247 + ) way_0_data_ram 1.248 + ( 1.249 + // ----- Inputs ------- 1.250 + .read_clk (clk_i), 1.251 + .write_clk (clk_i), 1.252 + .reset (rst_i), 1.253 + .read_address (dmem_read_address), 1.254 + .enable_read (read_port_enable), 1.255 + .write_address (dmem_write_address), 1.256 + .enable_write (write_port_enable), 1.257 + .write_enable (way_dmem_we[i] & (store_byte_select[j] | refill)), 1.258 + .write_data (dmem_write_data[(j+1)*8-1:j*8]), 1.259 + // ----- Outputs ------- 1.260 + .read_data (way_data[i][(j+1)*8-1:j*8]) 1.261 + ); 1.262 + end 1.263 + end 1.264 + 1.265 + // Way tags 1.266 + lm32_ram 1.267 + #( 1.268 + // ----- Parameters ------- 1.269 + .data_width (`LM32_DC_TAGS_WIDTH), 1.270 + .address_width (`LM32_DC_TMEM_ADDR_WIDTH), 1.271 +`ifdef CFG_DCACHE_DAT_USE_DP_TRUE 1.272 + .RAM_IMPLEMENTATION ("EBR"), 1.273 + .RAM_TYPE ("RAM_DP_TRUE") 1.274 +`else 1.275 + `ifdef CFG_DCACHE_DAT_USE_SLICE 1.276 + .RAM_IMPLEMENTATION ("SLICE") 1.277 + `else 1.278 + .RAM_IMPLEMENTATION ("AUTO") 1.279 + `endif 1.280 +`endif 1.281 + ) way_0_tag_ram 1.282 + ( 1.283 + // ----- Inputs ------- 1.284 + .read_clk (clk_i), 1.285 + .write_clk (clk_i), 1.286 + .reset (rst_i), 1.287 + .read_address (tmem_read_address), 1.288 + .enable_read (read_port_enable), 1.289 + .write_address (tmem_write_address), 1.290 + .enable_write (`TRUE), 1.291 + .write_enable (way_tmem_we[i]), 1.292 + .write_data (tmem_write_data), 1.293 + // ----- Outputs ------- 1.294 + .read_data ({way_tag[i], way_valid[i]}) 1.295 + ); 1.296 + end 1.297 + 1.298 + endgenerate 1.299 + 1.300 +///////////////////////////////////////////////////// 1.301 +// Combinational logic 1.302 +///////////////////////////////////////////////////// 1.303 + 1.304 +// Compute which ways in the cache match the address being read 1.305 +generate 1.306 + for (i = 0; i < associativity; i = i + 1) 1.307 + begin : match 1.308 +assign way_match[i] = ({way_tag[i], way_valid[i]} == {address_m[`LM32_DC_ADDR_TAG_RNG], `TRUE}); 1.309 + end 1.310 +endgenerate 1.311 + 1.312 +// Select data from way that matched the address being read 1.313 +generate 1.314 + if (associativity == 1) 1.315 + begin : data_1 1.316 +assign load_data = way_data[0]; 1.317 + end 1.318 + else if (associativity == 2) 1.319 + begin : data_2 1.320 +assign load_data = way_match[0] ? way_data[0] : way_data[1]; 1.321 + end 1.322 +endgenerate 1.323 + 1.324 +generate 1.325 + if (`LM32_DC_DMEM_ADDR_WIDTH < 11) 1.326 + begin 1.327 +// Select data to write to data memories 1.328 +always @(*) 1.329 +begin 1.330 + if (refill == `TRUE) 1.331 + dmem_write_data = refill_data; 1.332 + else 1.333 + begin 1.334 + dmem_write_data[`LM32_BYTE_0_RNG] = store_byte_select[0] ? store_data[`LM32_BYTE_0_RNG] : load_data[`LM32_BYTE_0_RNG]; 1.335 + dmem_write_data[`LM32_BYTE_1_RNG] = store_byte_select[1] ? store_data[`LM32_BYTE_1_RNG] : load_data[`LM32_BYTE_1_RNG]; 1.336 + dmem_write_data[`LM32_BYTE_2_RNG] = store_byte_select[2] ? store_data[`LM32_BYTE_2_RNG] : load_data[`LM32_BYTE_2_RNG]; 1.337 + dmem_write_data[`LM32_BYTE_3_RNG] = store_byte_select[3] ? store_data[`LM32_BYTE_3_RNG] : load_data[`LM32_BYTE_3_RNG]; 1.338 + end 1.339 +end 1.340 + end 1.341 + else 1.342 + begin 1.343 +// Select data to write to data memories - FIXME: Should use different write ports on dual port RAMs, but they don't work 1.344 +always @(*) 1.345 +begin 1.346 + if (refill == `TRUE) 1.347 + dmem_write_data = refill_data; 1.348 + else 1.349 + dmem_write_data = store_data; 1.350 +end 1.351 + end 1.352 +endgenerate 1.353 + 1.354 +// Compute address to use to index into the data memories 1.355 +generate 1.356 + if (bytes_per_line > 4) 1.357 +assign dmem_write_address = (refill == `TRUE) 1.358 + ? {refill_address[`LM32_DC_ADDR_SET_RNG], refill_offset} 1.359 + : address_m[`LM32_DC_ADDR_IDX_RNG]; 1.360 + else 1.361 +assign dmem_write_address = (refill == `TRUE) 1.362 + ? refill_address[`LM32_DC_ADDR_SET_RNG] 1.363 + : address_m[`LM32_DC_ADDR_IDX_RNG]; 1.364 +endgenerate 1.365 +assign dmem_read_address = address_x[`LM32_DC_ADDR_IDX_RNG]; 1.366 +// Compute address to use to index into the tag memories 1.367 +assign tmem_write_address = (flushing == `TRUE) 1.368 + ? flush_set 1.369 + : refill_address[`LM32_DC_ADDR_SET_RNG]; 1.370 +assign tmem_read_address = address_x[`LM32_DC_ADDR_SET_RNG]; 1.371 + 1.372 +// Compute signal to indicate when we are on the last refill accesses 1.373 +generate 1.374 + if (bytes_per_line > 4) 1.375 +assign last_refill = refill_offset == {addr_offset_width{1'b1}}; 1.376 + else 1.377 +assign last_refill = `TRUE; 1.378 +endgenerate 1.379 + 1.380 +// Compute data and tag memory access enable 1.381 +assign read_port_enable = (stall_x == `FALSE); 1.382 +assign write_port_enable = (refill_ready == `TRUE) || !stall_m; 1.383 + 1.384 +// Determine when we have a valid store 1.385 +assign valid_store = (store_q_m == `TRUE) && (check == `TRUE); 1.386 + 1.387 +// Compute data and tag memory write enables 1.388 +generate 1.389 + if (associativity == 1) 1.390 + begin : we_1 1.391 +assign way_dmem_we[0] = (refill_ready == `TRUE) || ((valid_store == `TRUE) && (way_match[0] == `TRUE)); 1.392 +assign way_tmem_we[0] = (refill_ready == `TRUE) || (flushing == `TRUE); 1.393 + end 1.394 + else 1.395 + begin : we_2 1.396 +assign way_dmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || ((valid_store == `TRUE) && (way_match[0] == `TRUE)); 1.397 +assign way_dmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || ((valid_store == `TRUE) && (way_match[1] == `TRUE)); 1.398 +assign way_tmem_we[0] = ((refill_ready == `TRUE) && (refill_way_select[0] == `TRUE)) || (flushing == `TRUE); 1.399 +assign way_tmem_we[1] = ((refill_ready == `TRUE) && (refill_way_select[1] == `TRUE)) || (flushing == `TRUE); 1.400 + end 1.401 +endgenerate 1.402 + 1.403 +// On the last refill cycle set the valid bit, for all other writes it should be cleared 1.404 +assign tmem_write_data[`LM32_DC_TAGS_VALID_RNG] = ((last_refill == `TRUE) || (valid_store == `TRUE)) && (flushing == `FALSE); 1.405 +assign tmem_write_data[`LM32_DC_TAGS_TAG_RNG] = refill_address[`LM32_DC_ADDR_TAG_RNG]; 1.406 + 1.407 +// Signals that indicate which state we are in 1.408 +assign flushing = state[0]; 1.409 +assign check = state[1]; 1.410 +assign refill = state[2]; 1.411 + 1.412 +assign miss = (~(|way_match)) && (load_q_m == `TRUE) && (stall_m == `FALSE); 1.413 +assign stall_request = (check == `FALSE); 1.414 + 1.415 +///////////////////////////////////////////////////// 1.416 +// Sequential logic 1.417 +///////////////////////////////////////////////////// 1.418 + 1.419 +// Record way selected for replacement on a cache miss 1.420 +generate 1.421 + if (associativity >= 2) 1.422 + begin : way_select 1.423 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.424 +begin 1.425 + if (rst_i == `TRUE) 1.426 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 1.427 + else 1.428 + begin 1.429 + if (refill_request == `TRUE) 1.430 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 1.431 + end 1.432 +end 1.433 + end 1.434 +endgenerate 1.435 + 1.436 +// Record whether we are currently refilling 1.437 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.438 +begin 1.439 + if (rst_i == `TRUE) 1.440 + refilling <= `FALSE; 1.441 + else 1.442 + refilling <= refill; 1.443 +end 1.444 + 1.445 +// Instruction cache control FSM 1.446 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.447 +begin 1.448 + if (rst_i == `TRUE) 1.449 + begin 1.450 + state <= `LM32_DC_STATE_FLUSH; 1.451 + flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 1.452 + refill_request <= `FALSE; 1.453 + refill_address <= {`LM32_WORD_WIDTH{1'bx}}; 1.454 + restart_request <= `FALSE; 1.455 + end 1.456 + else 1.457 + begin 1.458 + case (state) 1.459 + 1.460 + // Flush the cache 1.461 + `LM32_DC_STATE_FLUSH: 1.462 + begin 1.463 + if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}}) 1.464 + state <= `LM32_DC_STATE_CHECK; 1.465 + flush_set <= flush_set - 1'b1; 1.466 + end 1.467 + 1.468 + // Check for cache misses 1.469 + `LM32_DC_STATE_CHECK: 1.470 + begin 1.471 + if (stall_a == `FALSE) 1.472 + restart_request <= `FALSE; 1.473 + if (miss == `TRUE) 1.474 + begin 1.475 + refill_request <= `TRUE; 1.476 + refill_address <= address_m; 1.477 + state <= `LM32_DC_STATE_REFILL; 1.478 + end 1.479 + else if (dflush == `TRUE) 1.480 + state <= `LM32_DC_STATE_FLUSH; 1.481 + end 1.482 + 1.483 + // Refill a cache line 1.484 + `LM32_DC_STATE_REFILL: 1.485 + begin 1.486 + refill_request <= `FALSE; 1.487 + if (refill_ready == `TRUE) 1.488 + begin 1.489 + if (last_refill == `TRUE) 1.490 + begin 1.491 + restart_request <= `TRUE; 1.492 + state <= `LM32_DC_STATE_CHECK; 1.493 + end 1.494 + end 1.495 + end 1.496 + 1.497 + endcase 1.498 + end 1.499 +end 1.500 + 1.501 +generate 1.502 + if (bytes_per_line > 4) 1.503 + begin 1.504 +// Refill offset 1.505 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.506 +begin 1.507 + if (rst_i == `TRUE) 1.508 + refill_offset <= {addr_offset_width{1'b0}}; 1.509 + else 1.510 + begin 1.511 + case (state) 1.512 + 1.513 + // Check for cache misses 1.514 + `LM32_DC_STATE_CHECK: 1.515 + begin 1.516 + if (miss == `TRUE) 1.517 + refill_offset <= {addr_offset_width{1'b0}}; 1.518 + end 1.519 + 1.520 + // Refill a cache line 1.521 + `LM32_DC_STATE_REFILL: 1.522 + begin 1.523 + if (refill_ready == `TRUE) 1.524 + refill_offset <= refill_offset + 1'b1; 1.525 + end 1.526 + 1.527 + endcase 1.528 + end 1.529 +end 1.530 + end 1.531 +endgenerate 1.532 + 1.533 +endmodule 1.534 + 1.535 +`endif 1.536 +