lm32_decoder.v

changeset 0
cd0b58aa6f83
child 26
73de224304c1
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/lm32_decoder.v	Sun Apr 04 20:40:03 2010 +0100
     1.3 @@ -0,0 +1,583 @@
     1.4 +// =============================================================================
     1.5 +//                           COPYRIGHT NOTICE
     1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 +// ALL RIGHTS RESERVED
     1.8 +// This confidential and proprietary software may be used only as authorised by
     1.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 +// The entire notice above must be reproduced on all authorized copies and
    1.11 +// copies may only be made to the extent permitted by a licensing agreement from
    1.12 +// Lattice Semiconductor Corporation.
    1.13 +//
    1.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.17 +// U.S.A                                   email: techsupport@latticesemi.com
    1.18 +// =============================================================================/
    1.19 +//                         FILE DETAILS
    1.20 +// Project          : LatticeMico32
    1.21 +// File             : lm32_decoder.v
    1.22 +// Title            : Instruction decoder
    1.23 +// Dependencies     : lm32_include.v
    1.24 +// Version          : 6.1.17
    1.25 +//                  : Initial Release
    1.26 +// Version          : 7.0SP2, 3.0
    1.27 +//                  : No Change
    1.28 +// Version          : 3.1
    1.29 +//                  : Support for static branch prediction. Information about
    1.30 +//                  : branch type is generated and passed on to the predictor.
    1.31 +// Version          : 3.2
    1.32 +//                  : No change
    1.33 +// Version          : 3.3
    1.34 +//                  : Renamed port names that conflict with keywords reserved
    1.35 +//                  : in System-Verilog.
    1.36 +// =============================================================================
    1.37 +
    1.38 +`include "lm32_include.v"
    1.39 +
    1.40 +// Index of opcode field in an instruction
    1.41 +`define LM32_OPCODE_RNG         31:26
    1.42 +`define LM32_OP_RNG             30:26
    1.43 +
    1.44 +// Opcodes - Some are only listed as 5 bits as their MSB is a don't care
    1.45 +`define LM32_OPCODE_ADD         5'b01101
    1.46 +`define LM32_OPCODE_AND         5'b01000
    1.47 +`define LM32_OPCODE_ANDHI       6'b011000
    1.48 +`define LM32_OPCODE_B           6'b110000
    1.49 +`define LM32_OPCODE_BI          6'b111000
    1.50 +`define LM32_OPCODE_BE          6'b010001
    1.51 +`define LM32_OPCODE_BG          6'b010010
    1.52 +`define LM32_OPCODE_BGE         6'b010011
    1.53 +`define LM32_OPCODE_BGEU        6'b010100
    1.54 +`define LM32_OPCODE_BGU         6'b010101
    1.55 +`define LM32_OPCODE_BNE         6'b010111
    1.56 +`define LM32_OPCODE_CALL        6'b110110
    1.57 +`define LM32_OPCODE_CALLI       6'b111110
    1.58 +`define LM32_OPCODE_CMPE        5'b11001
    1.59 +`define LM32_OPCODE_CMPG        5'b11010
    1.60 +`define LM32_OPCODE_CMPGE       5'b11011
    1.61 +`define LM32_OPCODE_CMPGEU      5'b11100
    1.62 +`define LM32_OPCODE_CMPGU       5'b11101
    1.63 +`define LM32_OPCODE_CMPNE       5'b11111
    1.64 +`define LM32_OPCODE_DIVU        6'b100011
    1.65 +`define LM32_OPCODE_LB          6'b000100
    1.66 +`define LM32_OPCODE_LBU         6'b010000
    1.67 +`define LM32_OPCODE_LH          6'b000111
    1.68 +`define LM32_OPCODE_LHU         6'b001011
    1.69 +`define LM32_OPCODE_LW          6'b001010
    1.70 +`define LM32_OPCODE_MODU        6'b110001
    1.71 +`define LM32_OPCODE_MUL         5'b00010
    1.72 +`define LM32_OPCODE_NOR         5'b00001
    1.73 +`define LM32_OPCODE_OR          5'b01110
    1.74 +`define LM32_OPCODE_ORHI        6'b011110
    1.75 +`define LM32_OPCODE_RAISE       6'b101011
    1.76 +`define LM32_OPCODE_RCSR        6'b100100
    1.77 +`define LM32_OPCODE_SB          6'b001100
    1.78 +`define LM32_OPCODE_SEXTB       6'b101100
    1.79 +`define LM32_OPCODE_SEXTH       6'b110111
    1.80 +`define LM32_OPCODE_SH          6'b000011
    1.81 +`define LM32_OPCODE_SL          5'b01111
    1.82 +`define LM32_OPCODE_SR          5'b00101
    1.83 +`define LM32_OPCODE_SRU         5'b00000
    1.84 +`define LM32_OPCODE_SUB         6'b110010
    1.85 +`define LM32_OPCODE_SW          6'b010110
    1.86 +`define LM32_OPCODE_USER        6'b110011
    1.87 +`define LM32_OPCODE_WCSR        6'b110100
    1.88 +`define LM32_OPCODE_XNOR        5'b01001
    1.89 +`define LM32_OPCODE_XOR         5'b00110
    1.90 +
    1.91 +/////////////////////////////////////////////////////
    1.92 +// Module interface
    1.93 +/////////////////////////////////////////////////////
    1.94 +
    1.95 +module lm32_decoder (
    1.96 +    // ----- Inputs -------
    1.97 +    instruction,
    1.98 +    // ----- Outputs -------
    1.99 +    d_result_sel_0,
   1.100 +    d_result_sel_1,        
   1.101 +    x_result_sel_csr,
   1.102 +`ifdef LM32_MC_ARITHMETIC_ENABLED
   1.103 +    x_result_sel_mc_arith,
   1.104 +`endif    
   1.105 +`ifdef LM32_NO_BARREL_SHIFT    
   1.106 +    x_result_sel_shift,
   1.107 +`endif
   1.108 +`ifdef CFG_SIGN_EXTEND_ENABLED
   1.109 +    x_result_sel_sext,
   1.110 +`endif    
   1.111 +    x_result_sel_logic,
   1.112 +`ifdef CFG_USER_ENABLED
   1.113 +    x_result_sel_user,
   1.114 +`endif
   1.115 +    x_result_sel_add,
   1.116 +    m_result_sel_compare,
   1.117 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.118 +    m_result_sel_shift,  
   1.119 +`endif    
   1.120 +    w_result_sel_load,
   1.121 +`ifdef CFG_PL_MULTIPLY_ENABLED
   1.122 +    w_result_sel_mul,
   1.123 +`endif
   1.124 +    x_bypass_enable,
   1.125 +    m_bypass_enable,
   1.126 +    read_enable_0,
   1.127 +    read_idx_0,
   1.128 +    read_enable_1,
   1.129 +    read_idx_1,
   1.130 +    write_enable,
   1.131 +    write_idx,
   1.132 +    immediate,
   1.133 +    branch_offset,
   1.134 +    load,
   1.135 +    store,
   1.136 +    size,
   1.137 +    sign_extend,
   1.138 +    adder_op,
   1.139 +    logic_op,
   1.140 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.141 +    direction,
   1.142 +`endif
   1.143 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   1.144 +    shift_left,
   1.145 +    shift_right,
   1.146 +`endif
   1.147 +`ifdef CFG_MC_MULTIPLY_ENABLED
   1.148 +    multiply,
   1.149 +`endif
   1.150 +`ifdef CFG_MC_DIVIDE_ENABLED
   1.151 +    divide,
   1.152 +    modulus,
   1.153 +`endif
   1.154 +    branch,
   1.155 +    branch_reg,
   1.156 +    condition,
   1.157 +    bi_conditional,
   1.158 +    bi_unconditional,
   1.159 +`ifdef CFG_DEBUG_ENABLED
   1.160 +    break_opcode,
   1.161 +`endif
   1.162 +    scall,
   1.163 +    eret,
   1.164 +`ifdef CFG_DEBUG_ENABLED
   1.165 +    bret,
   1.166 +`endif
   1.167 +`ifdef CFG_USER_ENABLED
   1.168 +    user_opcode,
   1.169 +`endif
   1.170 +    csr_write_enable
   1.171 +    );
   1.172 +
   1.173 +/////////////////////////////////////////////////////
   1.174 +// Inputs
   1.175 +/////////////////////////////////////////////////////
   1.176 +
   1.177 +input [`LM32_INSTRUCTION_RNG] instruction;       // Instruction to decode
   1.178 +
   1.179 +/////////////////////////////////////////////////////
   1.180 +// Outputs
   1.181 +/////////////////////////////////////////////////////
   1.182 +
   1.183 +output [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
   1.184 +reg    [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0;
   1.185 +output [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
   1.186 +reg    [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1;
   1.187 +output x_result_sel_csr;
   1.188 +reg    x_result_sel_csr;
   1.189 +`ifdef LM32_MC_ARITHMETIC_ENABLED
   1.190 +output x_result_sel_mc_arith;
   1.191 +reg    x_result_sel_mc_arith;
   1.192 +`endif
   1.193 +`ifdef LM32_NO_BARREL_SHIFT    
   1.194 +output x_result_sel_shift;
   1.195 +reg    x_result_sel_shift;
   1.196 +`endif
   1.197 +`ifdef CFG_SIGN_EXTEND_ENABLED
   1.198 +output x_result_sel_sext;
   1.199 +reg    x_result_sel_sext;
   1.200 +`endif
   1.201 +output x_result_sel_logic;
   1.202 +reg    x_result_sel_logic;
   1.203 +`ifdef CFG_USER_ENABLED
   1.204 +output x_result_sel_user;
   1.205 +reg    x_result_sel_user;
   1.206 +`endif
   1.207 +output x_result_sel_add;
   1.208 +reg    x_result_sel_add;
   1.209 +output m_result_sel_compare;
   1.210 +reg    m_result_sel_compare;
   1.211 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.212 +output m_result_sel_shift;
   1.213 +reg    m_result_sel_shift;
   1.214 +`endif
   1.215 +output w_result_sel_load;
   1.216 +reg    w_result_sel_load;
   1.217 +`ifdef CFG_PL_MULTIPLY_ENABLED
   1.218 +output w_result_sel_mul;
   1.219 +reg    w_result_sel_mul;
   1.220 +`endif
   1.221 +output x_bypass_enable;
   1.222 +wire   x_bypass_enable;
   1.223 +output m_bypass_enable;
   1.224 +wire   m_bypass_enable;
   1.225 +output read_enable_0;
   1.226 +wire   read_enable_0;
   1.227 +output [`LM32_REG_IDX_RNG] read_idx_0;
   1.228 +wire   [`LM32_REG_IDX_RNG] read_idx_0;
   1.229 +output read_enable_1;
   1.230 +wire   read_enable_1;
   1.231 +output [`LM32_REG_IDX_RNG] read_idx_1;
   1.232 +wire   [`LM32_REG_IDX_RNG] read_idx_1;
   1.233 +output write_enable;
   1.234 +wire   write_enable;
   1.235 +output [`LM32_REG_IDX_RNG] write_idx;
   1.236 +wire   [`LM32_REG_IDX_RNG] write_idx;
   1.237 +output [`LM32_WORD_RNG] immediate;
   1.238 +wire   [`LM32_WORD_RNG] immediate;
   1.239 +output [`LM32_PC_RNG] branch_offset;
   1.240 +wire   [`LM32_PC_RNG] branch_offset;
   1.241 +output load;
   1.242 +wire   load;
   1.243 +output store;
   1.244 +wire   store;
   1.245 +output [`LM32_SIZE_RNG] size;
   1.246 +wire   [`LM32_SIZE_RNG] size;
   1.247 +output sign_extend;
   1.248 +wire   sign_extend;
   1.249 +output adder_op;
   1.250 +wire   adder_op;
   1.251 +output [`LM32_LOGIC_OP_RNG] logic_op;
   1.252 +wire   [`LM32_LOGIC_OP_RNG] logic_op;
   1.253 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.254 +output direction;
   1.255 +wire   direction;
   1.256 +`endif
   1.257 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   1.258 +output shift_left;
   1.259 +wire   shift_left;
   1.260 +output shift_right;
   1.261 +wire   shift_right;
   1.262 +`endif
   1.263 +`ifdef CFG_MC_MULTIPLY_ENABLED
   1.264 +output multiply;
   1.265 +wire   multiply;
   1.266 +`endif
   1.267 +`ifdef CFG_MC_DIVIDE_ENABLED
   1.268 +output divide;
   1.269 +wire   divide;
   1.270 +output modulus;
   1.271 +wire   modulus;
   1.272 +`endif
   1.273 +output branch;
   1.274 +wire   branch;
   1.275 +output branch_reg;
   1.276 +wire   branch_reg;
   1.277 +output [`LM32_CONDITION_RNG] condition;
   1.278 +wire   [`LM32_CONDITION_RNG] condition;
   1.279 +output bi_conditional;
   1.280 +wire bi_conditional;
   1.281 +output bi_unconditional;
   1.282 +wire bi_unconditional;
   1.283 +`ifdef CFG_DEBUG_ENABLED
   1.284 +output break_opcode;
   1.285 +wire   break_opcode;
   1.286 +`endif
   1.287 +output scall;
   1.288 +wire   scall;
   1.289 +output eret;
   1.290 +wire   eret;
   1.291 +`ifdef CFG_DEBUG_ENABLED
   1.292 +output bret;
   1.293 +wire   bret;
   1.294 +`endif
   1.295 +`ifdef CFG_USER_ENABLED
   1.296 +output [`LM32_USER_OPCODE_RNG] user_opcode;
   1.297 +wire   [`LM32_USER_OPCODE_RNG] user_opcode;
   1.298 +`endif
   1.299 +output csr_write_enable;
   1.300 +wire   csr_write_enable;
   1.301 +
   1.302 +/////////////////////////////////////////////////////
   1.303 +// Internal nets and registers 
   1.304 +/////////////////////////////////////////////////////
   1.305 +
   1.306 +wire [`LM32_WORD_RNG] extended_immediate;       // Zero or sign extended immediate
   1.307 +wire [`LM32_WORD_RNG] high_immediate;           // Immediate as high 16 bits
   1.308 +wire [`LM32_WORD_RNG] call_immediate;           // Call immediate
   1.309 +wire [`LM32_WORD_RNG] branch_immediate;         // Conditional branch immediate
   1.310 +wire sign_extend_immediate;                     // Whether the immediate should be sign extended (`TRUE) or zero extended (`FALSE)
   1.311 +wire select_high_immediate;                     // Whether to select the high immediate  
   1.312 +wire select_call_immediate;                     // Whether to select the call immediate 
   1.313 +
   1.314 +/////////////////////////////////////////////////////
   1.315 +// Functions
   1.316 +/////////////////////////////////////////////////////
   1.317 +
   1.318 +`include "lm32_functions.v"
   1.319 +
   1.320 +/////////////////////////////////////////////////////
   1.321 +// Combinational logic
   1.322 +/////////////////////////////////////////////////////
   1.323 +
   1.324 +// Determine opcode
   1.325 +assign op_add    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_ADD;
   1.326 +assign op_and    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_AND;
   1.327 +assign op_andhi  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ANDHI;
   1.328 +assign op_b      = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_B;
   1.329 +assign op_bi     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BI;
   1.330 +assign op_be     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BE;
   1.331 +assign op_bg     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BG;
   1.332 +assign op_bge    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGE;
   1.333 +assign op_bgeu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGEU;
   1.334 +assign op_bgu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BGU;
   1.335 +assign op_bne    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_BNE;
   1.336 +assign op_call   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALL;
   1.337 +assign op_calli  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_CALLI;
   1.338 +assign op_cmpe   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPE;
   1.339 +assign op_cmpg   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPG;
   1.340 +assign op_cmpge  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGE;
   1.341 +assign op_cmpgeu = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGEU;
   1.342 +assign op_cmpgu  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPGU;
   1.343 +assign op_cmpne  = instruction[`LM32_OP_RNG] == `LM32_OPCODE_CMPNE;
   1.344 +`ifdef CFG_MC_DIVIDE_ENABLED
   1.345 +assign op_divu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_DIVU;
   1.346 +`endif
   1.347 +assign op_lb     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LB;
   1.348 +assign op_lbu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LBU;
   1.349 +assign op_lh     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LH;
   1.350 +assign op_lhu    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LHU;
   1.351 +assign op_lw     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_LW;
   1.352 +`ifdef CFG_MC_DIVIDE_ENABLED
   1.353 +assign op_modu   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_MODU;
   1.354 +`endif
   1.355 +`ifdef LM32_MULTIPLY_ENABLED
   1.356 +assign op_mul    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_MUL;
   1.357 +`endif
   1.358 +assign op_nor    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_NOR;
   1.359 +assign op_or     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_OR;
   1.360 +assign op_orhi   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_ORHI;
   1.361 +assign op_raise  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RAISE;
   1.362 +assign op_rcsr   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_RCSR;
   1.363 +assign op_sb     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SB;
   1.364 +`ifdef CFG_SIGN_EXTEND_ENABLED
   1.365 +assign op_sextb  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTB;
   1.366 +assign op_sexth  = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SEXTH;
   1.367 +`endif
   1.368 +assign op_sh     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SH;
   1.369 +`ifdef LM32_BARREL_SHIFT_ENABLED
   1.370 +assign op_sl     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SL;      
   1.371 +`endif
   1.372 +assign op_sr     = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SR;
   1.373 +assign op_sru    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_SRU;
   1.374 +assign op_sub    = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SUB;
   1.375 +assign op_sw     = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_SW;
   1.376 +assign op_user   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_USER;
   1.377 +assign op_wcsr   = instruction[`LM32_OPCODE_RNG] == `LM32_OPCODE_WCSR;
   1.378 +assign op_xnor   = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XNOR;
   1.379 +assign op_xor    = instruction[`LM32_OP_RNG] == `LM32_OPCODE_XOR;
   1.380 +
   1.381 +// Group opcodes by function
   1.382 +assign arith = op_add | op_sub;
   1.383 +assign logical = op_and | op_andhi | op_nor | op_or | op_orhi | op_xor | op_xnor;
   1.384 +assign cmp = op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne;
   1.385 +assign bi_conditional = op_be | op_bg | op_bge | op_bgeu  | op_bgu | op_bne;
   1.386 +assign bi_unconditional = op_bi;
   1.387 +assign bra = op_b | bi_unconditional | bi_conditional;
   1.388 +assign call = op_call | op_calli;
   1.389 +`ifdef LM32_BARREL_SHIFT_ENABLED
   1.390 +assign shift = op_sl | op_sr | op_sru;
   1.391 +`endif
   1.392 +`ifdef LM32_NO_BARREL_SHIFT
   1.393 +assign shift = op_sr | op_sru;
   1.394 +`endif
   1.395 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   1.396 +assign shift_left = op_sl;
   1.397 +assign shift_right = op_sr | op_sru;
   1.398 +`endif
   1.399 +`ifdef CFG_SIGN_EXTEND_ENABLED
   1.400 +assign sext = op_sextb | op_sexth;
   1.401 +`endif
   1.402 +`ifdef LM32_MULTIPLY_ENABLED
   1.403 +assign multiply = op_mul;
   1.404 +`endif
   1.405 +`ifdef CFG_MC_DIVIDE_ENABLED
   1.406 +assign divide = op_divu; 
   1.407 +assign modulus = op_modu;
   1.408 +`endif
   1.409 +assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
   1.410 +assign store = op_sb | op_sh | op_sw;
   1.411 +
   1.412 +// Select pipeline multiplexor controls
   1.413 +always @(*)
   1.414 +begin
   1.415 +    // D stage
   1.416 +    if (call) 
   1.417 +        d_result_sel_0 = `LM32_D_RESULT_SEL_0_NEXT_PC;
   1.418 +    else 
   1.419 +        d_result_sel_0 = `LM32_D_RESULT_SEL_0_REG_0;
   1.420 +    if (call) 
   1.421 +        d_result_sel_1 = `LM32_D_RESULT_SEL_1_ZERO;         
   1.422 +    else if ((instruction[31] == 1'b0) && !bra) 
   1.423 +        d_result_sel_1 = `LM32_D_RESULT_SEL_1_IMMEDIATE;
   1.424 +    else
   1.425 +        d_result_sel_1 = `LM32_D_RESULT_SEL_1_REG_1; 
   1.426 +    // X stage
   1.427 +    x_result_sel_csr = `FALSE;
   1.428 +`ifdef LM32_MC_ARITHMETIC_ENABLED
   1.429 +    x_result_sel_mc_arith = `FALSE;
   1.430 +`endif
   1.431 +`ifdef LM32_NO_BARREL_SHIFT
   1.432 +    x_result_sel_shift = `FALSE;
   1.433 +`endif
   1.434 +`ifdef CFG_SIGN_EXTEND_ENABLED
   1.435 +    x_result_sel_sext = `FALSE;
   1.436 +`endif
   1.437 +    x_result_sel_logic = `FALSE;
   1.438 +`ifdef CFG_USER_ENABLED        
   1.439 +    x_result_sel_user = `FALSE;
   1.440 +`endif
   1.441 +    x_result_sel_add = `FALSE;
   1.442 +    if (op_rcsr)
   1.443 +        x_result_sel_csr = `TRUE;
   1.444 +`ifdef LM32_MC_ARITHMETIC_ENABLED    
   1.445 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   1.446 +    else if (shift_left | shift_right) 
   1.447 +        x_result_sel_mc_arith = `TRUE;
   1.448 +`endif
   1.449 +`ifdef CFG_MC_DIVIDE_ENABLED
   1.450 +    else if (divide | modulus)
   1.451 +        x_result_sel_mc_arith = `TRUE;        
   1.452 +`endif
   1.453 +`ifdef CFG_MC_MULTIPLY_ENABLED
   1.454 +    else if (multiply)
   1.455 +        x_result_sel_mc_arith = `TRUE;            
   1.456 +`endif
   1.457 +`endif
   1.458 +`ifdef LM32_NO_BARREL_SHIFT
   1.459 +    else if (shift)
   1.460 +        x_result_sel_shift = `TRUE;        
   1.461 +`endif
   1.462 +`ifdef CFG_SIGN_EXTEND_ENABLED
   1.463 +    else if (sext)
   1.464 +        x_result_sel_sext = `TRUE;
   1.465 +`endif        
   1.466 +    else if (logical) 
   1.467 +        x_result_sel_logic = `TRUE;
   1.468 +`ifdef CFG_USER_ENABLED        
   1.469 +    else if (op_user)
   1.470 +        x_result_sel_user = `TRUE;
   1.471 +`endif
   1.472 +    else 
   1.473 +        x_result_sel_add = `TRUE;        
   1.474 +    
   1.475 +    // M stage
   1.476 +
   1.477 +    m_result_sel_compare = cmp;
   1.478 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.479 +    m_result_sel_shift = shift;
   1.480 +`endif
   1.481 +
   1.482 +    // W stage
   1.483 +    w_result_sel_load = load;
   1.484 +`ifdef CFG_PL_MULTIPLY_ENABLED
   1.485 +    w_result_sel_mul = op_mul; 
   1.486 +`endif
   1.487 +end
   1.488 +
   1.489 +// Set if result is valid at end of X stage
   1.490 +assign x_bypass_enable =  arith 
   1.491 +                        | logical
   1.492 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   1.493 +                        | shift_left
   1.494 +                        | shift_right
   1.495 +`endif                        
   1.496 +`ifdef CFG_MC_MULTIPLY_ENABLED
   1.497 +                        | multiply
   1.498 +`endif
   1.499 +`ifdef CFG_MC_DIVIDE_ENABLED
   1.500 +                        | divide
   1.501 +                        | modulus
   1.502 +`endif
   1.503 +`ifdef LM32_NO_BARREL_SHIFT
   1.504 +                        | shift
   1.505 +`endif                  
   1.506 +`ifdef CFG_SIGN_EXTEND_ENABLED
   1.507 +                        | sext 
   1.508 +`endif                        
   1.509 +`ifdef CFG_USER_ENABLED
   1.510 +                        | op_user
   1.511 +`endif
   1.512 +                        | op_rcsr
   1.513 +                        ;
   1.514 +// Set if result is valid at end of M stage                        
   1.515 +assign m_bypass_enable = x_bypass_enable 
   1.516 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.517 +                        | shift
   1.518 +`endif
   1.519 +                        | cmp
   1.520 +                        ;
   1.521 +// Register file read port 0                        
   1.522 +assign read_enable_0 = ~(op_bi | op_calli);
   1.523 +assign read_idx_0 = instruction[25:21];
   1.524 +// Register file read port 1 
   1.525 +assign read_enable_1 = ~(op_bi | op_calli | load);
   1.526 +assign read_idx_1 = instruction[20:16];
   1.527 +// Register file write port
   1.528 +assign write_enable = ~(bra | op_raise | store | op_wcsr);
   1.529 +assign write_idx = call
   1.530 +                    ? 5'd29
   1.531 +                    : instruction[31] == 1'b0 
   1.532 +                        ? instruction[20:16] 
   1.533 +                        : instruction[15:11];
   1.534 +                        
   1.535 +// Size of load/stores                        
   1.536 +assign size = instruction[27:26];
   1.537 +// Whether to sign or zero extend
   1.538 +assign sign_extend = instruction[28];                      
   1.539 +// Set adder_op to 1 to perform a subtraction
   1.540 +assign adder_op = op_sub | op_cmpe | op_cmpg | op_cmpge | op_cmpgeu | op_cmpgu | op_cmpne | bra;
   1.541 +// Logic operation (and, or, etc)
   1.542 +assign logic_op = instruction[29:26];
   1.543 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.544 +// Shift direction
   1.545 +assign direction = instruction[29];
   1.546 +`endif
   1.547 +// Control flow microcodes
   1.548 +assign branch = bra | call;
   1.549 +assign branch_reg = op_call | op_b;
   1.550 +assign condition = instruction[28:26];      
   1.551 +`ifdef CFG_DEBUG_ENABLED
   1.552 +assign break_opcode = op_raise & ~instruction[2];
   1.553 +`endif
   1.554 +assign scall = op_raise & instruction[2];
   1.555 +assign eret = op_b & (instruction[25:21] == 5'd30);
   1.556 +`ifdef CFG_DEBUG_ENABLED
   1.557 +assign bret = op_b & (instruction[25:21] == 5'd31);
   1.558 +`endif
   1.559 +`ifdef CFG_USER_ENABLED
   1.560 +// Extract user opcode
   1.561 +assign user_opcode = instruction[10:0];
   1.562 +`endif
   1.563 +// CSR read/write
   1.564 +assign csr_write_enable = op_wcsr;
   1.565 +
   1.566 +// Extract immediate from instruction
   1.567 +
   1.568 +assign sign_extend_immediate = ~(op_and | op_cmpgeu | op_cmpgu | op_nor | op_or | op_xnor | op_xor);
   1.569 +assign select_high_immediate = op_andhi | op_orhi;
   1.570 +assign select_call_immediate = instruction[31];
   1.571 +
   1.572 +assign high_immediate = {instruction[15:0], 16'h0000};
   1.573 +assign extended_immediate = {{16{sign_extend_immediate & instruction[15]}}, instruction[15:0]};
   1.574 +assign call_immediate = {{6{instruction[25]}}, instruction[25:0]};
   1.575 +assign branch_immediate = {{16{instruction[15]}}, instruction[15:0]};
   1.576 +
   1.577 +assign immediate = select_high_immediate == `TRUE 
   1.578 +                        ? high_immediate 
   1.579 +                        : extended_immediate;
   1.580 +   
   1.581 +assign branch_offset = select_call_immediate == `TRUE   
   1.582 +                        ? call_immediate
   1.583 +                        : branch_immediate;
   1.584 +    
   1.585 +endmodule 
   1.586 +