lm32_include.v

changeset 0
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child 1
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     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/lm32_include.v	Sun Apr 04 20:40:03 2010 +0100
     1.3 @@ -0,0 +1,329 @@
     1.4 +// =============================================================================
     1.5 +//                           COPYRIGHT NOTICE
     1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 +// ALL RIGHTS RESERVED
     1.8 +// This confidential and proprietary software may be used only as authorised by
     1.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 +// The entire notice above must be reproduced on all authorized copies and
    1.11 +// copies may only be made to the extent permitted by a licensing agreement from
    1.12 +// Lattice Semiconductor Corporation.
    1.13 +//
    1.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.17 +// U.S.A                                   email: techsupport@latticesemi.com
    1.18 +// =============================================================================/
    1.19 +//                         FILE DETAILS
    1.20 +// Project          : LatticeMico32
    1.21 +// File             : lm32_include.v
    1.22 +// Title            : CPU global macros
    1.23 +// Version          : 6.1.17
    1.24 +//                  : Initial Release
    1.25 +// Version          : 7.0SP2, 3.0
    1.26 +//                  : No Change
    1.27 +// Version          : 3.1
    1.28 +//                  : No Change
    1.29 +// Version          : 3.2
    1.30 +//                  : No Change
    1.31 +// Version          : 3.3
    1.32 +//                  : Support for extended configuration register
    1.33 +// =============================================================================
    1.34 +
    1.35 +`ifdef LM32_INCLUDE_V
    1.36 +`else
    1.37 +`define LM32_INCLUDE_V
    1.38 +
    1.39 +// Configuration options
    1.40 +`include "system_conf.v"
    1.41 +
    1.42 +`ifdef TRUE
    1.43 +`else
    1.44 +`define TRUE    1'b1
    1.45 +`define FALSE   1'b0
    1.46 +`define TRUE_N  1'b0
    1.47 +`define FALSE_N 1'b1
    1.48 +`endif
    1.49 +
    1.50 +// Wishbone configuration
    1.51 +`define CFG_IWB_ENABLED
    1.52 +`define CFG_DWB_ENABLED
    1.53 +
    1.54 +// Data-path width
    1.55 +`define LM32_WORD_WIDTH                 32
    1.56 +`define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
    1.57 +`define LM32_SHIFT_WIDTH                5
    1.58 +`define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
    1.59 +`define LM32_BYTE_SELECT_WIDTH          4
    1.60 +`define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
    1.61 +
    1.62 +// Register file size
    1.63 +`define LM32_REGISTERS                  32
    1.64 +`define LM32_REG_IDX_WIDTH              5
    1.65 +`define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
    1.66 +
    1.67 +// Standard register numbers
    1.68 +`define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
    1.69 +`define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
    1.70 +`define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
    1.71 +
    1.72 +// Range of Program Counter. Two LSBs are always 0. 
    1.73 +// `ifdef CFG_ICACHE_ENABLED
    1.74 +// `define LM32_PC_WIDTH                   (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
    1.75 +// `else
    1.76 +// `ifdef CFG_IWB_ENABLED
    1.77 +`define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
    1.78 +// `else
    1.79 +// `define LM32_PC_WIDTH                   `LM32_IROM_ADDRESS_WIDTH
    1.80 +// `endif
    1.81 +// `endif
    1.82 +`define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
    1.83 +
    1.84 +// Range of an instruction
    1.85 +`define LM32_INSTRUCTION_WIDTH          32
    1.86 +`define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
    1.87 +
    1.88 +// Adder operation
    1.89 +`define LM32_ADDER_OP_ADD               1'b0
    1.90 +`define LM32_ADDER_OP_SUBTRACT          1'b1
    1.91 +
    1.92 +// Shift direction
    1.93 +`define LM32_SHIFT_OP_RIGHT             1'b0
    1.94 +`define LM32_SHIFT_OP_LEFT              1'b1
    1.95 +
    1.96 +// Currently always enabled
    1.97 +`define CFG_BUS_ERRORS_ENABLED
    1.98 +
    1.99 +// Derive macro that indicates whether we have single-stepping or not
   1.100 +`ifdef CFG_ROM_DEBUG_ENABLED
   1.101 +`define LM32_SINGLE_STEP_ENABLED
   1.102 +`else
   1.103 +`ifdef CFG_HW_DEBUG_ENABLED
   1.104 +`define LM32_SINGLE_STEP_ENABLED
   1.105 +`endif
   1.106 +`endif
   1.107 +
   1.108 +// Derive macro that indicates whether JTAG interface is required
   1.109 +`ifdef CFG_JTAG_UART_ENABLED
   1.110 +`define LM32_JTAG_ENABLED
   1.111 +`else
   1.112 +`ifdef CFG_DEBUG_ENABLED
   1.113 +`define LM32_JTAG_ENABLED
   1.114 +`else
   1.115 +`endif
   1.116 +`endif
   1.117 +
   1.118 +// Derive macro that indicates whether we have a barrel-shifter or not
   1.119 +`ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.120 +`define LM32_BARREL_SHIFT_ENABLED
   1.121 +`else // CFG_PL_BARREL_SHIFT_ENABLED
   1.122 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   1.123 +`define LM32_BARREL_SHIFT_ENABLED
   1.124 +`else
   1.125 +`define LM32_NO_BARREL_SHIFT
   1.126 +`endif
   1.127 +`endif // CFG_PL_BARREL_SHIFT_ENABLED
   1.128 +
   1.129 +// Derive macro that indicates whether we have a multiplier or not
   1.130 +`ifdef CFG_PL_MULTIPLY_ENABLED
   1.131 +`define LM32_MULTIPLY_ENABLED
   1.132 +`else
   1.133 +`ifdef CFG_MC_MULTIPLY_ENABLED
   1.134 +`define LM32_MULTIPLY_ENABLED
   1.135 +`endif
   1.136 +`endif
   1.137 +
   1.138 +// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
   1.139 +`ifdef CFG_MC_DIVIDE_ENABLED
   1.140 +`define LM32_MC_ARITHMETIC_ENABLED
   1.141 +`endif
   1.142 +`ifdef CFG_MC_MULTIPLY_ENABLED
   1.143 +`define LM32_MC_ARITHMETIC_ENABLED
   1.144 +`endif
   1.145 +`ifdef CFG_MC_BARREL_SHIFT_ENABLED
   1.146 +`define LM32_MC_ARITHMETIC_ENABLED
   1.147 +`endif
   1.148 +
   1.149 +// Derive macro that indicates if we are using an EBR register file
   1.150 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   1.151 +`define LM32_EBR_REGISTER_FILE
   1.152 +`endif
   1.153 +`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
   1.154 +`define LM32_EBR_REGISTER_FILE
   1.155 +`endif
   1.156 +
   1.157 +// Revision number
   1.158 +`define LM32_REVISION                   6'h02
   1.159 +
   1.160 +// Logical operations - Function encoded directly in instruction
   1.161 +`define LM32_LOGIC_OP_RNG               3:0
   1.162 +
   1.163 +// Conditions for conditional branches
   1.164 +`define LM32_CONDITION_WIDTH            3
   1.165 +`define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
   1.166 +`define LM32_CONDITION_E                3'b001
   1.167 +`define LM32_CONDITION_G                3'b010
   1.168 +`define LM32_CONDITION_GE               3'b011
   1.169 +`define LM32_CONDITION_GEU              3'b100
   1.170 +`define LM32_CONDITION_GU               3'b101
   1.171 +`define LM32_CONDITION_NE               3'b111
   1.172 +`define LM32_CONDITION_U1               3'b000
   1.173 +`define LM32_CONDITION_U2               3'b110
   1.174 +
   1.175 +// Size of load or store instruction - Encoding corresponds to opcode
   1.176 +`define LM32_SIZE_WIDTH                 2
   1.177 +`define LM32_SIZE_RNG                   1:0
   1.178 +`define LM32_SIZE_BYTE                  2'b00
   1.179 +`define LM32_SIZE_HWORD                 2'b11
   1.180 +`define LM32_SIZE_WORD                  2'b10
   1.181 +`define LM32_ADDRESS_LSBS_WIDTH         2
   1.182 +
   1.183 +// Width and range of a CSR index
   1.184 +`ifdef CFG_DEBUG_ENABLED
   1.185 +`define LM32_CSR_WIDTH                  5
   1.186 +`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
   1.187 +`else
   1.188 +`ifdef CFG_JTAG_ENABLED
   1.189 +`define LM32_CSR_WIDTH                  4
   1.190 +`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
   1.191 +`else
   1.192 +`define LM32_CSR_WIDTH                  3
   1.193 +`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
   1.194 +`endif
   1.195 +`endif
   1.196 +
   1.197 +// CSR indices
   1.198 +`define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
   1.199 +`define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
   1.200 +`define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
   1.201 +`define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
   1.202 +`define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
   1.203 +`define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
   1.204 +`define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
   1.205 +`define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
   1.206 +`ifdef CFG_DEBUG_ENABLED
   1.207 +`define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
   1.208 +`define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
   1.209 +`endif
   1.210 +`define LM32_CSR_CFG2                   `LM32_CSR_WIDTH'ha
   1.211 +`ifdef CFG_JTAG_ENABLED
   1.212 +`define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
   1.213 +`define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
   1.214 +`endif
   1.215 +`ifdef CFG_DEBUG_ENABLED
   1.216 +`define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
   1.217 +`define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
   1.218 +`define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
   1.219 +`define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
   1.220 +`define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
   1.221 +`define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
   1.222 +`define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
   1.223 +`define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
   1.224 +`endif 
   1.225 +
   1.226 +// Values for WPC CSR
   1.227 +`define LM32_WPC_C_RNG                  1:0
   1.228 +`define LM32_WPC_C_DISABLED             2'b00
   1.229 +`define LM32_WPC_C_READ                 2'b01
   1.230 +`define LM32_WPC_C_WRITE                2'b10
   1.231 +`define LM32_WPC_C_READ_WRITE           2'b11
   1.232 +
   1.233 +// Exception IDs
   1.234 +`define LM32_EID_WIDTH                  3
   1.235 +`define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
   1.236 +`define LM32_EID_RESET                  3'h0
   1.237 +`define LM32_EID_BREAKPOINT             3'd1
   1.238 +`define LM32_EID_INST_BUS_ERROR         3'h2
   1.239 +`define LM32_EID_WATCHPOINT             3'd3
   1.240 +`define LM32_EID_DATA_BUS_ERROR         3'h4
   1.241 +`define LM32_EID_DIVIDE_BY_ZERO         3'h5
   1.242 +`define LM32_EID_INTERRUPT              3'h6
   1.243 +`define LM32_EID_SCALL                  3'h7
   1.244 +
   1.245 +// Pipeline result selection mux controls
   1.246 +
   1.247 +`define LM32_D_RESULT_SEL_0_RNG          0:0
   1.248 +`define LM32_D_RESULT_SEL_0_REG_0        1'b0
   1.249 +`define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
   1.250 +
   1.251 +`define LM32_D_RESULT_SEL_1_RNG          1:0
   1.252 +`define LM32_D_RESULT_SEL_1_ZERO         2'b00
   1.253 +`define LM32_D_RESULT_SEL_1_REG_1        2'b01
   1.254 +`define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
   1.255 +
   1.256 +`define LM32_USER_OPCODE_WIDTH           11
   1.257 +`define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
   1.258 +
   1.259 +// Derive a macro to indicate if either of the caches are implemented
   1.260 +`ifdef CFG_ICACHE_ENABLED
   1.261 +`define LM32_CACHE_ENABLED      
   1.262 +`else
   1.263 +`ifdef CFG_DCACHE_ENABLED
   1.264 +`define LM32_CACHE_ENABLED
   1.265 +`endif
   1.266 +`endif
   1.267 +
   1.268 +/////////////////////////////////////////////////////
   1.269 +// Interrupts
   1.270 +/////////////////////////////////////////////////////
   1.271 +
   1.272 +// Always enable interrupts
   1.273 +`define CFG_INTERRUPTS_ENABLED
   1.274 +
   1.275 +// Currently this is fixed to 32 and should not be changed
   1.276 +`define CFG_INTERRUPTS                  32
   1.277 +`define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
   1.278 +`define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
   1.279 +
   1.280 +/////////////////////////////////////////////////////
   1.281 +// General
   1.282 +/////////////////////////////////////////////////////
   1.283 +
   1.284 +// Sub-word range types
   1.285 +`define LM32_BYTE_WIDTH                 8
   1.286 +`define LM32_BYTE_RNG                   7:0
   1.287 +`define LM32_HWORD_WIDTH                16
   1.288 +`define LM32_HWORD_RNG                  15:0
   1.289 +
   1.290 +// Word sub-byte indicies
   1.291 +`define LM32_BYTE_0_RNG                  7:0
   1.292 +`define LM32_BYTE_1_RNG                  15:8
   1.293 +`define LM32_BYTE_2_RNG                  23:16
   1.294 +`define LM32_BYTE_3_RNG                  31:24
   1.295 +
   1.296 +// Word sub-halfword indices
   1.297 +`define LM32_HWORD_0_RNG                 15:0
   1.298 +`define LM32_HWORD_1_RNG                 31:16
   1.299 +
   1.300 +// Use an asynchronous reset
   1.301 +// To use a synchronous reset, define this macro as nothing
   1.302 +`define CFG_RESET_SENSITIVITY 
   1.303 +
   1.304 +// V.T. Srce
   1.305 +`define SRCE
   1.306 +
   1.307 +// Whether to include context registers for debug exceptions
   1.308 +// in addition to standard exception handling registers
   1.309 +// Bizarre - Removing this increases LUT count!
   1.310 +`define CFG_DEBUG_EXCEPTIONS_ENABLED
   1.311 +
   1.312 +// Wishbone defines 
   1.313 +// Refer to Wishbone System-on-Chip Interconnection Architecture
   1.314 +// These should probably be moved to a Wishbone common file
   1.315 +
   1.316 +// Wishbone cycle types
   1.317 +`define LM32_CTYPE_WIDTH                3
   1.318 +`define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
   1.319 +`define LM32_CTYPE_CLASSIC              3'b000
   1.320 +`define LM32_CTYPE_CONSTANT             3'b001
   1.321 +`define LM32_CTYPE_INCREMENTING         3'b010
   1.322 +`define LM32_CTYPE_END                  3'b111
   1.323 +
   1.324 +// Wishbone burst types
   1.325 +`define LM32_BTYPE_WIDTH                2
   1.326 +`define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
   1.327 +`define LM32_BTYPE_LINEAR               2'b00
   1.328 +`define LM32_BTYPE_4_BEAT               2'b01
   1.329 +`define LM32_BTYPE_8_BEAT               2'b10
   1.330 +`define LM32_BTYPE_16_BEAT              2'b11
   1.331 +
   1.332 +`endif