lm32_instruction_unit.v

changeset 0
cd0b58aa6f83
child 8
07be9df9fee8
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/lm32_instruction_unit.v	Sun Apr 04 20:40:03 2010 +0100
     1.3 @@ -0,0 +1,841 @@
     1.4 +// =============================================================================
     1.5 +//                           COPYRIGHT NOTICE
     1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 +// ALL RIGHTS RESERVED
     1.8 +// This confidential and proprietary software may be used only as authorised by
     1.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 +// The entire notice above must be reproduced on all authorized copies and
    1.11 +// copies may only be made to the extent permitted by a licensing agreement from
    1.12 +// Lattice Semiconductor Corporation.
    1.13 +//
    1.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.17 +// U.S.A                                   email: techsupport@latticesemi.com
    1.18 +// =============================================================================/
    1.19 +//                         FILE DETAILS
    1.20 +// Project      : LatticeMico32
    1.21 +// File         : lm32_instruction_unit.v
    1.22 +// Title        : Instruction unit
    1.23 +// Dependencies : lm32_include.v
    1.24 +// Version      : 6.1.17
    1.25 +//              : Initial Release
    1.26 +// Version      : 7.0SP2, 3.0
    1.27 +//              : No Change
    1.28 +// Version      : 3.1
    1.29 +//              : Support for static branch prediction is added. Fetching of
    1.30 +//              : instructions can also be altered by branches predicted in D
    1.31 +//              : stage of pipeline, and mispredicted branches in the X and M 
    1.32 +//              : stages of the pipeline.
    1.33 +// Version      : 3.2
    1.34 +//              : EBRs use SYNC resets instead of ASYNC resets.
    1.35 +// Version      : 3.3
    1.36 +//              : Support for a non-cacheable Instruction Memory that has a 
    1.37 +//              : single-cycle access latency. This memory can be accessed by
    1.38 +//              : data port of LM32 (so that debugger has access to it).
    1.39 +// Version      : 3.4
    1.40 +//              : No change
    1.41 +// Version      : 3.5
    1.42 +//              : Bug fix: Inline memory is correctly generated if it is not a
    1.43 +//              : power-of-two.
    1.44 +//              : Bug fix: Fixed a bug that caused LM32 (configured without
    1.45 +//              : instruction cache) to lock up in to an infinite loop due to a 
    1.46 +//              : instruction bus error when EBA was set to instruction inline
    1.47 +//              : memory.
    1.48 +// =============================================================================
    1.49 +
    1.50 +`include "lm32_include.v"
    1.51 +
    1.52 +/////////////////////////////////////////////////////
    1.53 +// Module interface
    1.54 +/////////////////////////////////////////////////////
    1.55 +
    1.56 +module lm32_instruction_unit (
    1.57 +    // ----- Inputs -------
    1.58 +    clk_i,
    1.59 +    rst_i,
    1.60 +    // From pipeline
    1.61 +    stall_a,
    1.62 +    stall_f,
    1.63 +    stall_d,
    1.64 +    stall_x,
    1.65 +    stall_m,
    1.66 +    valid_f,
    1.67 +    valid_d,
    1.68 +    kill_f,
    1.69 +    branch_predict_taken_d,
    1.70 +    branch_predict_address_d,
    1.71 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
    1.72 +    branch_taken_x,
    1.73 +    branch_target_x,
    1.74 +`endif
    1.75 +    exception_m,
    1.76 +    branch_taken_m,
    1.77 +    branch_mispredict_taken_m,
    1.78 +    branch_target_m,
    1.79 +`ifdef CFG_ICACHE_ENABLED
    1.80 +    iflush,
    1.81 +`endif
    1.82 +`ifdef CFG_DCACHE_ENABLED
    1.83 +    dcache_restart_request,
    1.84 +    dcache_refill_request,
    1.85 +    dcache_refilling,
    1.86 +`endif        
    1.87 +`ifdef CFG_IROM_ENABLED
    1.88 +    irom_store_data_m,
    1.89 +    irom_address_xm,
    1.90 +    irom_we_xm,
    1.91 +`endif
    1.92 +`ifdef CFG_IWB_ENABLED
    1.93 +    // From Wishbone
    1.94 +    i_dat_i,
    1.95 +    i_ack_i,
    1.96 +    i_err_i,
    1.97 +    i_rty_i,
    1.98 +`endif
    1.99 +`ifdef CFG_HW_DEBUG_ENABLED
   1.100 +    jtag_read_enable,
   1.101 +    jtag_write_enable,
   1.102 +    jtag_write_data,
   1.103 +    jtag_address,
   1.104 +`endif
   1.105 +    // ----- Outputs -------
   1.106 +    // To pipeline
   1.107 +    pc_f,
   1.108 +    pc_d,
   1.109 +    pc_x,
   1.110 +    pc_m,
   1.111 +    pc_w,
   1.112 +`ifdef CFG_ICACHE_ENABLED
   1.113 +    icache_stall_request,
   1.114 +    icache_restart_request,
   1.115 +    icache_refill_request,
   1.116 +    icache_refilling,
   1.117 +`endif
   1.118 +`ifdef CFG_IROM_ENABLED
   1.119 +    irom_data_m,
   1.120 +`endif
   1.121 +`ifdef CFG_IWB_ENABLED
   1.122 +    // To Wishbone
   1.123 +    i_dat_o,
   1.124 +    i_adr_o,
   1.125 +    i_cyc_o,
   1.126 +    i_sel_o,
   1.127 +    i_stb_o,
   1.128 +    i_we_o,
   1.129 +    i_cti_o,
   1.130 +    i_lock_o,
   1.131 +    i_bte_o,
   1.132 +`endif
   1.133 +`ifdef CFG_HW_DEBUG_ENABLED
   1.134 +    jtag_read_data,
   1.135 +    jtag_access_complete,
   1.136 +`endif
   1.137 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.138 +    bus_error_d,
   1.139 +`endif
   1.140 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   1.141 +    instruction_f,
   1.142 +`endif    
   1.143 +    instruction_d
   1.144 +    );
   1.145 +
   1.146 +/////////////////////////////////////////////////////
   1.147 +// Parameters
   1.148 +/////////////////////////////////////////////////////
   1.149 +
   1.150 +parameter associativity = 1;                            // Associativity of the cache (Number of ways)
   1.151 +parameter sets = 512;                                   // Number of sets
   1.152 +parameter bytes_per_line = 16;                          // Number of bytes per cache line
   1.153 +parameter base_address = 0;                             // Base address of cachable memory
   1.154 +parameter limit = 0;                                    // Limit (highest address) of cachable memory
   1.155 +
   1.156 +// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
   1.157 +localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
   1.158 +localparam addr_offset_lsb = 2;
   1.159 +localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
   1.160 +
   1.161 +/////////////////////////////////////////////////////
   1.162 +// Inputs
   1.163 +/////////////////////////////////////////////////////
   1.164 +
   1.165 +input clk_i;                                            // Clock
   1.166 +input rst_i;                                            // Reset
   1.167 +
   1.168 +input stall_a;                                          // Stall A stage instruction
   1.169 +input stall_f;                                          // Stall F stage instruction
   1.170 +input stall_d;                                          // Stall D stage instruction
   1.171 +input stall_x;                                          // Stall X stage instruction
   1.172 +input stall_m;                                          // Stall M stage instruction
   1.173 +input valid_f;                                          // Instruction in F stage is valid
   1.174 +input valid_d;                                          // Instruction in D stage is valid
   1.175 +input kill_f;                                           // Kill instruction in F stage
   1.176 +
   1.177 +input branch_predict_taken_d;                           // Branch is predicted taken in D stage
   1.178 +input [`LM32_PC_RNG] branch_predict_address_d;          // Branch target address
   1.179 +   
   1.180 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   1.181 +input branch_taken_x;                                   // Branch instruction in X stage is taken
   1.182 +input [`LM32_PC_RNG] branch_target_x;                   // Target PC of X stage branch instruction
   1.183 +`endif
   1.184 +input exception_m;
   1.185 +input branch_taken_m;                                   // Branch instruction in M stage is taken
   1.186 +input branch_mispredict_taken_m;                        // Branch instruction in M stage is mispredicted as taken
   1.187 +input [`LM32_PC_RNG] branch_target_m;                   // Target PC of M stage branch instruction
   1.188 +
   1.189 +`ifdef CFG_ICACHE_ENABLED
   1.190 +input iflush;                                           // Flush instruction cache
   1.191 +`endif
   1.192 +`ifdef CFG_DCACHE_ENABLED
   1.193 +input dcache_restart_request;                           // Restart instruction that caused a data cache miss
   1.194 +input dcache_refill_request;                            // Request to refill data cache
   1.195 +input dcache_refilling;
   1.196 +`endif        
   1.197 +
   1.198 +`ifdef CFG_IROM_ENABLED
   1.199 +input [`LM32_WORD_RNG] irom_store_data_m;               // Data from load-store unit
   1.200 +input [`LM32_WORD_RNG] irom_address_xm;                 // Address from load-store unit
   1.201 +input irom_we_xm;                                       // Indicates if memory operation is load or store
   1.202 +`endif
   1.203 +
   1.204 +`ifdef CFG_IWB_ENABLED
   1.205 +input [`LM32_WORD_RNG] i_dat_i;                         // Instruction Wishbone interface read data
   1.206 +input i_ack_i;                                          // Instruction Wishbone interface acknowledgement
   1.207 +input i_err_i;                                          // Instruction Wishbone interface error
   1.208 +input i_rty_i;                                          // Instruction Wishbone interface retry
   1.209 +`endif
   1.210 +
   1.211 +`ifdef CFG_HW_DEBUG_ENABLED
   1.212 +input jtag_read_enable;                                 // JTAG read memory request
   1.213 +input jtag_write_enable;                                // JTAG write memory request
   1.214 +input [`LM32_BYTE_RNG] jtag_write_data;                 // JTAG wrirte data
   1.215 +input [`LM32_WORD_RNG] jtag_address;                    // JTAG read/write address
   1.216 +`endif
   1.217 +
   1.218 +/////////////////////////////////////////////////////
   1.219 +// Outputs
   1.220 +/////////////////////////////////////////////////////
   1.221 +        
   1.222 +output [`LM32_PC_RNG] pc_f;                             // F stage PC
   1.223 +reg    [`LM32_PC_RNG] pc_f;
   1.224 +output [`LM32_PC_RNG] pc_d;                             // D stage PC
   1.225 +reg    [`LM32_PC_RNG] pc_d;
   1.226 +output [`LM32_PC_RNG] pc_x;                             // X stage PC
   1.227 +reg    [`LM32_PC_RNG] pc_x;
   1.228 +output [`LM32_PC_RNG] pc_m;                             // M stage PC
   1.229 +reg    [`LM32_PC_RNG] pc_m;
   1.230 +output [`LM32_PC_RNG] pc_w;                             // W stage PC
   1.231 +reg    [`LM32_PC_RNG] pc_w;
   1.232 +
   1.233 +`ifdef CFG_ICACHE_ENABLED
   1.234 +output icache_stall_request;                            // Instruction cache stall request
   1.235 +wire   icache_stall_request;
   1.236 +output icache_restart_request;                          // Request to restart instruction that cached instruction cache miss
   1.237 +wire   icache_restart_request;
   1.238 +output icache_refill_request;                           // Instruction cache refill request
   1.239 +wire   icache_refill_request;
   1.240 +output icache_refilling;                                // Indicates the icache is refilling
   1.241 +wire   icache_refilling;
   1.242 +`endif
   1.243 +
   1.244 +`ifdef CFG_IROM_ENABLED
   1.245 +output [`LM32_WORD_RNG] irom_data_m;                    // Data to load-store unit on load
   1.246 +wire   [`LM32_WORD_RNG] irom_data_m;                      
   1.247 +`endif   
   1.248 +
   1.249 +`ifdef CFG_IWB_ENABLED
   1.250 +output [`LM32_WORD_RNG] i_dat_o;                        // Instruction Wishbone interface write data
   1.251 +`ifdef CFG_HW_DEBUG_ENABLED
   1.252 +reg    [`LM32_WORD_RNG] i_dat_o;
   1.253 +`else
   1.254 +wire   [`LM32_WORD_RNG] i_dat_o;
   1.255 +`endif
   1.256 +output [`LM32_WORD_RNG] i_adr_o;                        // Instruction Wishbone interface address
   1.257 +reg    [`LM32_WORD_RNG] i_adr_o;
   1.258 +output i_cyc_o;                                         // Instruction Wishbone interface cycle
   1.259 +reg    i_cyc_o; 
   1.260 +output [`LM32_BYTE_SELECT_RNG] i_sel_o;                 // Instruction Wishbone interface byte select
   1.261 +`ifdef CFG_HW_DEBUG_ENABLED
   1.262 +reg    [`LM32_BYTE_SELECT_RNG] i_sel_o;
   1.263 +`else
   1.264 +wire   [`LM32_BYTE_SELECT_RNG] i_sel_o;
   1.265 +`endif
   1.266 +output i_stb_o;                                         // Instruction Wishbone interface strobe
   1.267 +reg    i_stb_o;
   1.268 +output i_we_o;                                          // Instruction Wishbone interface write enable
   1.269 +`ifdef CFG_HW_DEBUG_ENABLED
   1.270 +reg    i_we_o;
   1.271 +`else
   1.272 +wire   i_we_o;
   1.273 +`endif
   1.274 +output [`LM32_CTYPE_RNG] i_cti_o;                       // Instruction Wishbone interface cycle type 
   1.275 +reg    [`LM32_CTYPE_RNG] i_cti_o;
   1.276 +output i_lock_o;                                        // Instruction Wishbone interface lock bus
   1.277 +reg    i_lock_o;
   1.278 +output [`LM32_BTYPE_RNG] i_bte_o;                       // Instruction Wishbone interface burst type 
   1.279 +wire   [`LM32_BTYPE_RNG] i_bte_o;
   1.280 +`endif
   1.281 +
   1.282 +`ifdef CFG_HW_DEBUG_ENABLED
   1.283 +output [`LM32_BYTE_RNG] jtag_read_data;                 // Data read for JTAG interface
   1.284 +reg    [`LM32_BYTE_RNG] jtag_read_data;
   1.285 +output jtag_access_complete;                            // Requested memory access by JTAG interface is complete
   1.286 +wire   jtag_access_complete;
   1.287 +`endif
   1.288 +
   1.289 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.290 +output bus_error_d;                                     // Indicates a bus error occured while fetching the instruction
   1.291 +reg    bus_error_d;
   1.292 +`endif
   1.293 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   1.294 +output [`LM32_INSTRUCTION_RNG] instruction_f;           // F stage instruction (only to have register indices extracted from)
   1.295 +wire   [`LM32_INSTRUCTION_RNG] instruction_f;
   1.296 +`endif
   1.297 +output [`LM32_INSTRUCTION_RNG] instruction_d;           // D stage instruction to be decoded
   1.298 +reg    [`LM32_INSTRUCTION_RNG] instruction_d;
   1.299 +
   1.300 +/////////////////////////////////////////////////////
   1.301 +// Internal nets and registers 
   1.302 +/////////////////////////////////////////////////////
   1.303 +
   1.304 +reg [`LM32_PC_RNG] pc_a;                                // A stage PC
   1.305 +
   1.306 +`ifdef LM32_CACHE_ENABLED
   1.307 +reg [`LM32_PC_RNG] restart_address;                     // Address to restart from after a cache miss  
   1.308 +`endif
   1.309 +
   1.310 +`ifdef CFG_ICACHE_ENABLED
   1.311 +wire icache_read_enable_f;                              // Indicates if instruction cache miss is valid
   1.312 +wire [`LM32_PC_RNG] icache_refill_address;              // Address that caused cache miss
   1.313 +reg icache_refill_ready;                                // Indicates when next word of refill data is ready to be written to cache
   1.314 +reg [`LM32_INSTRUCTION_RNG] icache_refill_data;         // Next word of refill data, fetched from Wishbone
   1.315 +wire [`LM32_INSTRUCTION_RNG] icache_data_f;             // Instruction fetched from instruction cache
   1.316 +wire [`LM32_CTYPE_RNG] first_cycle_type;                // First Wishbone cycle type
   1.317 +wire [`LM32_CTYPE_RNG] next_cycle_type;                 // Next Wishbone cycle type
   1.318 +wire last_word;                                         // Indicates if this is the last word in the cache line
   1.319 +wire [`LM32_PC_RNG] first_address;                      // First cache refill address
   1.320 +`else
   1.321 +`ifdef CFG_IWB_ENABLED
   1.322 +reg [`LM32_INSTRUCTION_RNG] wb_data_f;                  // Instruction fetched from Wishbone
   1.323 +`endif
   1.324 +`endif
   1.325 +`ifdef CFG_IROM_ENABLED
   1.326 +wire irom_select_a;                                     // Indicates if A stage PC maps to a ROM address
   1.327 +reg irom_select_f;                                      // Indicates if F stage PC maps to a ROM address
   1.328 +wire [`LM32_INSTRUCTION_RNG] irom_data_f;               // Instruction fetched from ROM
   1.329 +`endif
   1.330 +`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   1.331 +`else
   1.332 +wire [`LM32_INSTRUCTION_RNG] instruction_f;             // F stage instruction
   1.333 +`endif
   1.334 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.335 +reg bus_error_f;                                        // Indicates if a bus error occured while fetching the instruction in the F stage
   1.336 +`endif
   1.337 +
   1.338 +`ifdef CFG_HW_DEBUG_ENABLED
   1.339 +reg jtag_access;                                        // Indicates if a JTAG WB access is in progress
   1.340 +`endif
   1.341 +
   1.342 +/////////////////////////////////////////////////////
   1.343 +// Functions
   1.344 +/////////////////////////////////////////////////////
   1.345 +
   1.346 +`include "lm32_functions.v"
   1.347 +
   1.348 +/////////////////////////////////////////////////////
   1.349 +// Instantiations
   1.350 +/////////////////////////////////////////////////////
   1.351 +
   1.352 +// Instruction ROM
   1.353 +`ifdef CFG_IROM_ENABLED  
   1.354 +   pmi_ram_dp_true 
   1.355 +     #(
   1.356 +       // ----- Parameters -------
   1.357 +       .pmi_family             (`LATTICE_FAMILY),
   1.358 +	 
   1.359 +       //.pmi_addr_depth_a       (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
   1.360 +       //.pmi_addr_width_a       ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
   1.361 +       //.pmi_data_width_a       (`LM32_WORD_WIDTH),
   1.362 +       //.pmi_addr_depth_b       (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
   1.363 +       //.pmi_addr_width_b       ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
   1.364 +       //.pmi_data_width_b       (`LM32_WORD_WIDTH),
   1.365 +	 
   1.366 +       .pmi_addr_depth_a       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
   1.367 +       .pmi_addr_width_a       (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
   1.368 +       .pmi_data_width_a       (`LM32_WORD_WIDTH),
   1.369 +       .pmi_addr_depth_b       (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
   1.370 +       .pmi_addr_width_b       (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
   1.371 +       .pmi_data_width_b       (`LM32_WORD_WIDTH),
   1.372 +	 
   1.373 +       .pmi_regmode_a          ("noreg"),
   1.374 +       .pmi_regmode_b          ("noreg"),
   1.375 +       .pmi_gsr                ("enable"),
   1.376 +       .pmi_resetmode          ("sync"),
   1.377 +       .pmi_init_file          (`CFG_IROM_INIT_FILE),
   1.378 +       .pmi_init_file_format   (`CFG_IROM_INIT_FILE_FORMAT),
   1.379 +       .module_type            ("pmi_ram_dp_true")
   1.380 +       ) 
   1.381 +       ram (
   1.382 +	    // ----- Inputs -------
   1.383 +	    .ClockA                 (clk_i),
   1.384 +	    .ClockB                 (clk_i),
   1.385 +	    .ResetA                 (rst_i),
   1.386 +	    .ResetB                 (rst_i),
   1.387 +	    .DataInA                ({32{1'b0}}),
   1.388 +	    .DataInB                (irom_store_data_m),
   1.389 +	    .AddressA               (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
   1.390 +	    .AddressB               (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
   1.391 +	    .ClockEnA               (!stall_a),
   1.392 +	    .ClockEnB               (!stall_x || !stall_m),
   1.393 +	    .WrA                    (`FALSE),
   1.394 +	    .WrB                    (irom_we_xm), 
   1.395 +	    // ----- Outputs -------
   1.396 +	    .QA                     (irom_data_f),
   1.397 +	    .QB                     (irom_data_m)
   1.398 +	    );
   1.399 +`endif    
   1.400 + 
   1.401 +`ifdef CFG_ICACHE_ENABLED
   1.402 +// Instruction cache
   1.403 +lm32_icache #(
   1.404 +    .associativity          (associativity),
   1.405 +    .sets                   (sets),
   1.406 +    .bytes_per_line         (bytes_per_line),
   1.407 +    .base_address           (base_address),
   1.408 +    .limit                  (limit)
   1.409 +    ) icache ( 
   1.410 +    // ----- Inputs -----
   1.411 +    .clk_i                  (clk_i),
   1.412 +    .rst_i                  (rst_i),      
   1.413 +    .stall_a                (stall_a),
   1.414 +    .stall_f                (stall_f),
   1.415 +    .branch_predict_taken_d (branch_predict_taken_d),
   1.416 +    .valid_d                (valid_d),
   1.417 +    .address_a              (pc_a),
   1.418 +    .address_f              (pc_f),
   1.419 +    .read_enable_f          (icache_read_enable_f),
   1.420 +    .refill_ready           (icache_refill_ready),
   1.421 +    .refill_data            (icache_refill_data),
   1.422 +    .iflush                 (iflush),
   1.423 +    // ----- Outputs -----
   1.424 +    .stall_request          (icache_stall_request),
   1.425 +    .restart_request        (icache_restart_request),
   1.426 +    .refill_request         (icache_refill_request),
   1.427 +    .refill_address         (icache_refill_address),
   1.428 +    .refilling              (icache_refilling),
   1.429 +    .inst                   (icache_data_f)
   1.430 +    );
   1.431 +`endif
   1.432 +
   1.433 +/////////////////////////////////////////////////////
   1.434 +// Combinational Logic
   1.435 +/////////////////////////////////////////////////////
   1.436 +
   1.437 +`ifdef CFG_ICACHE_ENABLED
   1.438 +// Generate signal that indicates when instruction cache misses are valid
   1.439 +assign icache_read_enable_f =    (valid_f == `TRUE)
   1.440 +                              && (kill_f == `FALSE)
   1.441 +`ifdef CFG_DCACHE_ENABLED
   1.442 +                              && (dcache_restart_request == `FALSE)
   1.443 +`endif                         
   1.444 +`ifdef CFG_IROM_ENABLED 
   1.445 +                              && (irom_select_f == `FALSE)
   1.446 +`endif       
   1.447 +                              ;
   1.448 +`endif
   1.449 +
   1.450 +// Compute address of next instruction to fetch
   1.451 +always @(*)
   1.452 +begin
   1.453 +    // The request from the latest pipeline stage must take priority
   1.454 +`ifdef CFG_DCACHE_ENABLED
   1.455 +    if (dcache_restart_request == `TRUE)
   1.456 +        pc_a = restart_address;
   1.457 +    else 
   1.458 +`endif    
   1.459 +      if (branch_taken_m == `TRUE)
   1.460 +	if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE))
   1.461 +	  pc_a = pc_x;
   1.462 +	else
   1.463 +          pc_a = branch_target_m;
   1.464 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   1.465 +      else if (branch_taken_x == `TRUE)
   1.466 +        pc_a = branch_target_x;
   1.467 +`endif
   1.468 +      else
   1.469 +	if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) )
   1.470 +	  pc_a = branch_predict_address_d;
   1.471 +	else
   1.472 +`ifdef CFG_ICACHE_ENABLED
   1.473 +          if (icache_restart_request == `TRUE)
   1.474 +            pc_a = restart_address;
   1.475 +	  else 
   1.476 +`endif        
   1.477 +            pc_a = pc_f + 1'b1;
   1.478 +end
   1.479 +
   1.480 +// Select where instruction should be fetched from
   1.481 +`ifdef CFG_IROM_ENABLED
   1.482 +assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT);
   1.483 +`endif
   1.484 +                     
   1.485 +// Select instruction from selected source
   1.486 +`ifdef CFG_ICACHE_ENABLED
   1.487 +`ifdef CFG_IROM_ENABLED
   1.488 +assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f;
   1.489 +`else
   1.490 +assign instruction_f = icache_data_f;
   1.491 +`endif
   1.492 +`else
   1.493 +`ifdef CFG_IROM_ENABLED
   1.494 +`ifdef CFG_IWB_ENABLED
   1.495 +assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f;
   1.496 +`else
   1.497 +assign instruction_f = irom_data_f;
   1.498 +`endif
   1.499 +`else
   1.500 +assign instruction_f = wb_data_f;
   1.501 +`endif
   1.502 +`endif
   1.503 +
   1.504 +// Unused/constant Wishbone signals
   1.505 +`ifdef CFG_IWB_ENABLED
   1.506 +`ifdef CFG_HW_DEBUG_ENABLED
   1.507 +`else
   1.508 +assign i_dat_o = 32'd0;
   1.509 +assign i_we_o = `FALSE;
   1.510 +assign i_sel_o = 4'b1111;
   1.511 +`endif
   1.512 +assign i_bte_o = `LM32_BTYPE_LINEAR;
   1.513 +`endif
   1.514 +
   1.515 +`ifdef CFG_ICACHE_ENABLED
   1.516 +// Determine parameters for next cache refill Wishbone access                
   1.517 +generate
   1.518 +    case (bytes_per_line)
   1.519 +    4:
   1.520 +    begin
   1.521 +assign first_cycle_type = `LM32_CTYPE_END;
   1.522 +assign next_cycle_type = `LM32_CTYPE_END;
   1.523 +assign last_word = `TRUE;
   1.524 +assign first_address = icache_refill_address;
   1.525 +    end
   1.526 +    8:
   1.527 +    begin
   1.528 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
   1.529 +assign next_cycle_type = `LM32_CTYPE_END;
   1.530 +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
   1.531 +assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
   1.532 +    end
   1.533 +    16:
   1.534 +    begin
   1.535 +assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
   1.536 +assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
   1.537 +assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
   1.538 +assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
   1.539 +    end
   1.540 +    endcase
   1.541 +endgenerate
   1.542 +`endif
   1.543 +                     
   1.544 +/////////////////////////////////////////////////////
   1.545 +// Sequential Logic
   1.546 +/////////////////////////////////////////////////////
   1.547 +
   1.548 +// PC 
   1.549 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.550 +begin
   1.551 +    if (rst_i == `TRUE)
   1.552 +    begin
   1.553 +        pc_f <= (`CFG_EBA_RESET-4)/4;
   1.554 +        pc_d <= {`LM32_PC_WIDTH{1'b0}};
   1.555 +        pc_x <= {`LM32_PC_WIDTH{1'b0}};
   1.556 +        pc_m <= {`LM32_PC_WIDTH{1'b0}};
   1.557 +        pc_w <= {`LM32_PC_WIDTH{1'b0}};
   1.558 +    end
   1.559 +    else
   1.560 +    begin
   1.561 +        if (stall_f == `FALSE)
   1.562 +            pc_f <= pc_a;
   1.563 +        if (stall_d == `FALSE)
   1.564 +            pc_d <= pc_f;
   1.565 +        if (stall_x == `FALSE)
   1.566 +            pc_x <= pc_d;
   1.567 +        if (stall_m == `FALSE)
   1.568 +            pc_m <= pc_x;
   1.569 +        pc_w <= pc_m;
   1.570 +    end
   1.571 +end
   1.572 +
   1.573 +`ifdef LM32_CACHE_ENABLED
   1.574 +// Address to restart from after a cache miss has been handled
   1.575 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.576 +begin
   1.577 +    if (rst_i == `TRUE)
   1.578 +        restart_address <= {`LM32_PC_WIDTH{1'b0}};
   1.579 +    else
   1.580 +    begin
   1.581 +`ifdef CFG_DCACHE_ENABLED
   1.582 +`ifdef CFG_ICACHE_ENABLED        
   1.583 +            // D-cache restart address must take priority, otherwise instructions will be lost
   1.584 +            if (dcache_refill_request == `TRUE)
   1.585 +                restart_address <= pc_w;
   1.586 +            else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request))
   1.587 +                restart_address <= icache_refill_address;
   1.588 +`else
   1.589 +            if (dcache_refill_request == `TRUE)
   1.590 +                restart_address <= pc_w;
   1.591 +`endif
   1.592 +`else
   1.593 +`ifdef CFG_ICACHE_ENABLED        
   1.594 +            if (icache_refill_request == `TRUE)
   1.595 +                restart_address <= icache_refill_address;
   1.596 +`endif
   1.597 +`endif
   1.598 +    end
   1.599 +end
   1.600 +`endif
   1.601 +
   1.602 +// Record where instruction was fetched from
   1.603 +`ifdef CFG_IROM_ENABLED
   1.604 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.605 +begin
   1.606 +    if (rst_i == `TRUE)
   1.607 +        irom_select_f <= `FALSE;
   1.608 +    else
   1.609 +    begin
   1.610 +        if (stall_f == `FALSE)
   1.611 +            irom_select_f <= irom_select_a;
   1.612 +    end
   1.613 +end
   1.614 +`endif
   1.615 +
   1.616 +`ifdef CFG_HW_DEBUG_ENABLED
   1.617 +assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE);
   1.618 +always @(*)
   1.619 +begin
   1.620 +    case (jtag_address[1:0])
   1.621 +    2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG];
   1.622 +    2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG];
   1.623 +    2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG];
   1.624 +    2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG];
   1.625 +    endcase 
   1.626 +end
   1.627 +`endif
   1.628 +
   1.629 +`ifdef CFG_IWB_ENABLED
   1.630 +// Instruction Wishbone interface
   1.631 +`ifdef CFG_ICACHE_ENABLED                
   1.632 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.633 +begin
   1.634 +    if (rst_i == `TRUE)
   1.635 +    begin
   1.636 +        i_cyc_o <= `FALSE;
   1.637 +        i_stb_o <= `FALSE;
   1.638 +        i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
   1.639 +        i_cti_o <= `LM32_CTYPE_END;
   1.640 +        i_lock_o <= `FALSE;
   1.641 +        icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
   1.642 +        icache_refill_ready <= `FALSE;
   1.643 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.644 +        bus_error_f <= `FALSE;
   1.645 +`endif
   1.646 +`ifdef CFG_HW_DEBUG_ENABLED
   1.647 +        i_we_o <= `FALSE;
   1.648 +        i_sel_o <= 4'b1111;
   1.649 +        jtag_access <= `FALSE;
   1.650 +`endif
   1.651 +    end
   1.652 +    else
   1.653 +    begin   
   1.654 +        icache_refill_ready <= `FALSE;
   1.655 +        // Is a cycle in progress?
   1.656 +        if (i_cyc_o == `TRUE)
   1.657 +        begin
   1.658 +            // Has cycle completed?
   1.659 +            if ((i_ack_i == `TRUE) || (i_err_i == `TRUE))
   1.660 +            begin
   1.661 +`ifdef CFG_HW_DEBUG_ENABLED
   1.662 +                if (jtag_access == `TRUE)
   1.663 +                begin
   1.664 +                    i_cyc_o <= `FALSE;
   1.665 +                    i_stb_o <= `FALSE;       
   1.666 +                    i_we_o <= `FALSE;  
   1.667 +                    jtag_access <= `FALSE;    
   1.668 +                end
   1.669 +                else
   1.670 +`endif
   1.671 +                begin
   1.672 +                    if (last_word == `TRUE)
   1.673 +                    begin
   1.674 +                        // Cache line fill complete 
   1.675 +                        i_cyc_o <= `FALSE;
   1.676 +                        i_stb_o <= `FALSE;
   1.677 +                        i_lock_o <= `FALSE;
   1.678 +                    end
   1.679 +                    // Fetch next word in cache line
   1.680 +                    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
   1.681 +                    i_cti_o <= next_cycle_type;
   1.682 +                    // Write fetched data into instruction cache
   1.683 +                    icache_refill_ready <= `TRUE;
   1.684 +                    icache_refill_data <= i_dat_i;
   1.685 +                end
   1.686 +            end
   1.687 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.688 +            if (i_err_i == `TRUE)
   1.689 +            begin
   1.690 +                bus_error_f <= `TRUE;
   1.691 +                $display ("Instruction bus error. Address: %x", i_adr_o);
   1.692 +            end
   1.693 +`endif
   1.694 +        end
   1.695 +        else
   1.696 +        begin
   1.697 +            if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE))
   1.698 +            begin
   1.699 +                // Read first word of cache line
   1.700 +`ifdef CFG_HW_DEBUG_ENABLED     
   1.701 +                i_sel_o <= 4'b1111;
   1.702 +`endif
   1.703 +                i_adr_o <= {first_address, 2'b00};
   1.704 +                i_cyc_o <= `TRUE;
   1.705 +                i_stb_o <= `TRUE;                
   1.706 +                i_cti_o <= first_cycle_type;
   1.707 +                //i_lock_o <= `TRUE;
   1.708 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.709 +                bus_error_f <= `FALSE;
   1.710 +`endif
   1.711 +            end
   1.712 +`ifdef CFG_HW_DEBUG_ENABLED
   1.713 +            else
   1.714 +            begin
   1.715 +                if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
   1.716 +                begin
   1.717 +                    case (jtag_address[1:0])
   1.718 +                    2'b00: i_sel_o <= 4'b1000;
   1.719 +                    2'b01: i_sel_o <= 4'b0100;
   1.720 +                    2'b10: i_sel_o <= 4'b0010;
   1.721 +                    2'b11: i_sel_o <= 4'b0001;
   1.722 +                    endcase
   1.723 +                    i_adr_o <= jtag_address;
   1.724 +                    i_dat_o <= {4{jtag_write_data}};
   1.725 +                    i_cyc_o <= `TRUE;
   1.726 +                    i_stb_o <= `TRUE;
   1.727 +                    i_we_o <= jtag_write_enable;
   1.728 +                    i_cti_o <= `LM32_CTYPE_END;
   1.729 +                    jtag_access <= `TRUE;
   1.730 +                end
   1.731 +            end 
   1.732 +`endif                    
   1.733 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.734 +            // Clear bus error when exception taken, otherwise they would be 
   1.735 +            // continually generated if exception handler is cached
   1.736 +`ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   1.737 +            if (branch_taken_x == `TRUE)
   1.738 +                bus_error_f <= `FALSE;
   1.739 +`endif
   1.740 +            if (branch_taken_m == `TRUE)
   1.741 +                bus_error_f <= `FALSE;
   1.742 +`endif
   1.743 +        end
   1.744 +    end
   1.745 +end
   1.746 +`else
   1.747 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.748 +begin
   1.749 +    if (rst_i == `TRUE)
   1.750 +    begin
   1.751 +        i_cyc_o <= `FALSE;
   1.752 +        i_stb_o <= `FALSE;
   1.753 +        i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
   1.754 +        i_cti_o <= `LM32_CTYPE_END;
   1.755 +        i_lock_o <= `FALSE;
   1.756 +        wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
   1.757 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.758 +        bus_error_f <= `FALSE;
   1.759 +`endif
   1.760 +    end
   1.761 +    else
   1.762 +    begin   
   1.763 +        // Is a cycle in progress?
   1.764 +        if (i_cyc_o == `TRUE)
   1.765 +        begin
   1.766 +            // Has cycle completed?
   1.767 +            if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
   1.768 +            begin
   1.769 +                // Cycle complete
   1.770 +                i_cyc_o <= `FALSE;
   1.771 +                i_stb_o <= `FALSE;
   1.772 +                // Register fetched instruction
   1.773 +                wb_data_f <= i_dat_i;
   1.774 +            end
   1.775 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.776 +            if (i_err_i == `TRUE)
   1.777 +            begin
   1.778 +                bus_error_f <= `TRUE;
   1.779 +                $display ("Instruction bus error. Address: %x", i_adr_o);
   1.780 +            end
   1.781 +`endif
   1.782 +        end
   1.783 +        else
   1.784 +        begin
   1.785 +            // Wait for an instruction fetch from an external address 
   1.786 +            if (   (stall_a == `FALSE) 
   1.787 +`ifdef CFG_IROM_ENABLED 
   1.788 +                && (irom_select_a == `FALSE)
   1.789 +`endif       
   1.790 +               )
   1.791 +            begin
   1.792 +                // Fetch instruction
   1.793 +`ifdef CFG_HW_DEBUG_ENABLED     
   1.794 +                i_sel_o <= 4'b1111;
   1.795 +`endif
   1.796 +                i_adr_o <= {pc_a, 2'b00};
   1.797 +                i_cyc_o <= `TRUE;
   1.798 +                i_stb_o <= `TRUE;
   1.799 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.800 +                bus_error_f <= `FALSE;
   1.801 +`endif
   1.802 +            end
   1.803 +	    else
   1.804 +	    begin
   1.805 +	        if (   (stall_a == `FALSE) 
   1.806 +`ifdef CFG_IROM_ENABLED 
   1.807 +		    && (irom_select_a == `TRUE)
   1.808 +`endif       
   1.809 +	           )
   1.810 +		begin
   1.811 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.812 +		    bus_error_f <= `FALSE;
   1.813 +`endif
   1.814 +		end
   1.815 +	    end
   1.816 +        end
   1.817 +    end
   1.818 +end
   1.819 +`endif
   1.820 +`endif
   1.821 +
   1.822 +// Instruction register
   1.823 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.824 +begin
   1.825 +    if (rst_i == `TRUE)
   1.826 +    begin
   1.827 +        instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
   1.828 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.829 +        bus_error_d <= `FALSE;
   1.830 +`endif
   1.831 +    end
   1.832 +    else
   1.833 +    begin
   1.834 +        if (stall_d == `FALSE)
   1.835 +        begin
   1.836 +            instruction_d <= instruction_f;
   1.837 +`ifdef CFG_BUS_ERRORS_ENABLED
   1.838 +            bus_error_d <= bus_error_f;
   1.839 +`endif
   1.840 +        end
   1.841 +    end
   1.842 +end  
   1.843 +  
   1.844 +endmodule