1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/lm32_jtag.v Sun Apr 04 20:40:03 2010 +0100 1.3 @@ -0,0 +1,479 @@ 1.4 +// ============================================================================= 1.5 +// COPYRIGHT NOTICE 1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 +// ALL RIGHTS RESERVED 1.8 +// This confidential and proprietary software may be used only as authorised by 1.9 +// a licensing agreement from Lattice Semiconductor Corporation. 1.10 +// The entire notice above must be reproduced on all authorized copies and 1.11 +// copies may only be made to the extent permitted by a licensing agreement from 1.12 +// Lattice Semiconductor Corporation. 1.13 +// 1.14 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.15 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.16 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.17 +// U.S.A email: techsupport@latticesemi.com 1.18 +// =============================================================================/ 1.19 +// FILE DETAILS 1.20 +// Project : LatticeMico32 1.21 +// File : lm32_jtag.v 1.22 +// Title : JTAG interface 1.23 +// Dependencies : lm32_include.v 1.24 +// Version : 6.1.17 1.25 +// : Initial Release 1.26 +// Version : 7.0SP2, 3.0 1.27 +// : No Change 1.28 +// Version : 3.1 1.29 +// : No Change 1.30 +// ============================================================================= 1.31 + 1.32 +`include "lm32_include.v" 1.33 + 1.34 +`ifdef CFG_JTAG_ENABLED 1.35 + 1.36 +`define LM32_DP 3'b000 1.37 +`define LM32_TX 3'b001 1.38 +`define LM32_RX 3'b010 1.39 + 1.40 +// LM32 Debug Protocol commands IDs 1.41 +`define LM32_DP_RNG 3:0 1.42 +`define LM32_DP_READ_MEMORY 4'b0001 1.43 +`define LM32_DP_WRITE_MEMORY 4'b0010 1.44 +`define LM32_DP_READ_SEQUENTIAL 4'b0011 1.45 +`define LM32_DP_WRITE_SEQUENTIAL 4'b0100 1.46 +`define LM32_DP_WRITE_CSR 4'b0101 1.47 +`define LM32_DP_BREAK 4'b0110 1.48 +`define LM32_DP_RESET 4'b0111 1.49 + 1.50 +// States for FSM 1.51 +`define LM32_JTAG_STATE_RNG 3:0 1.52 +`define LM32_JTAG_STATE_READ_COMMAND 4'h0 1.53 +`define LM32_JTAG_STATE_READ_BYTE_0 4'h1 1.54 +`define LM32_JTAG_STATE_READ_BYTE_1 4'h2 1.55 +`define LM32_JTAG_STATE_READ_BYTE_2 4'h3 1.56 +`define LM32_JTAG_STATE_READ_BYTE_3 4'h4 1.57 +`define LM32_JTAG_STATE_READ_BYTE_4 4'h5 1.58 +`define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6 1.59 +`define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7 1.60 +`define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8 1.61 + 1.62 +///////////////////////////////////////////////////// 1.63 +// Module interface 1.64 +///////////////////////////////////////////////////// 1.65 + 1.66 +module lm32_jtag ( 1.67 + // ----- Inputs ------- 1.68 + clk_i, 1.69 + rst_i, 1.70 + jtag_clk, 1.71 + jtag_update, 1.72 + jtag_reg_q, 1.73 + jtag_reg_addr_q, 1.74 +`ifdef CFG_JTAG_UART_ENABLED 1.75 + csr, 1.76 + csr_write_enable, 1.77 + csr_write_data, 1.78 + stall_x, 1.79 +`endif 1.80 +`ifdef CFG_HW_DEBUG_ENABLED 1.81 + jtag_read_data, 1.82 + jtag_access_complete, 1.83 +`endif 1.84 +`ifdef CFG_DEBUG_ENABLED 1.85 + exception_q_w, 1.86 +`endif 1.87 + // ----- Outputs ------- 1.88 +`ifdef CFG_JTAG_UART_ENABLED 1.89 + jtx_csr_read_data, 1.90 + jrx_csr_read_data, 1.91 +`endif 1.92 +`ifdef CFG_HW_DEBUG_ENABLED 1.93 + jtag_csr_write_enable, 1.94 + jtag_csr_write_data, 1.95 + jtag_csr, 1.96 + jtag_read_enable, 1.97 + jtag_write_enable, 1.98 + jtag_write_data, 1.99 + jtag_address, 1.100 +`endif 1.101 +`ifdef CFG_DEBUG_ENABLED 1.102 + jtag_break, 1.103 + jtag_reset, 1.104 +`endif 1.105 + jtag_reg_d, 1.106 + jtag_reg_addr_d 1.107 + ); 1.108 + 1.109 + parameter lat_family = `LATTICE_FAMILY; 1.110 + 1.111 +///////////////////////////////////////////////////// 1.112 +// Inputs 1.113 +///////////////////////////////////////////////////// 1.114 + 1.115 +input clk_i; // Clock 1.116 +input rst_i; // Reset 1.117 + 1.118 +input jtag_clk; // JTAG clock 1.119 +input jtag_update; // JTAG data register has been updated 1.120 +input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register 1.121 +input [2:0] jtag_reg_addr_q; // JTAG data register 1.122 + 1.123 +`ifdef CFG_JTAG_UART_ENABLED 1.124 +input [`LM32_CSR_RNG] csr; // CSR to write 1.125 +input csr_write_enable; // CSR write enable 1.126 +input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR 1.127 +input stall_x; // Stall instruction in X stage 1.128 +`endif 1.129 +`ifdef CFG_HW_DEBUG_ENABLED 1.130 +input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address 1.131 +input jtag_access_complete; // Memory access if complete 1.132 +`endif 1.133 +`ifdef CFG_DEBUG_ENABLED 1.134 +input exception_q_w; // Indicates an exception has occured in W stage 1.135 +`endif 1.136 + 1.137 +///////////////////////////////////////////////////// 1.138 +// Outputs 1.139 +///////////////////////////////////////////////////// 1.140 + 1.141 +`ifdef CFG_JTAG_UART_ENABLED 1.142 +output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions 1.143 +wire [`LM32_WORD_RNG] jtx_csr_read_data; 1.144 +output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions 1.145 +wire [`LM32_WORD_RNG] jrx_csr_read_data; 1.146 +`endif 1.147 +`ifdef CFG_HW_DEBUG_ENABLED 1.148 +output jtag_csr_write_enable; // CSR write enable 1.149 +reg jtag_csr_write_enable; 1.150 +output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR 1.151 +wire [`LM32_WORD_RNG] jtag_csr_write_data; 1.152 +output [`LM32_CSR_RNG] jtag_csr; // CSR to write 1.153 +wire [`LM32_CSR_RNG] jtag_csr; 1.154 +output jtag_read_enable; // Memory read enable 1.155 +reg jtag_read_enable; 1.156 +output jtag_write_enable; // Memory write enable 1.157 +reg jtag_write_enable; 1.158 +output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address 1.159 +wire [`LM32_BYTE_RNG] jtag_write_data; 1.160 +output [`LM32_WORD_RNG] jtag_address; // Memory read/write address 1.161 +wire [`LM32_WORD_RNG] jtag_address; 1.162 +`endif 1.163 +`ifdef CFG_DEBUG_ENABLED 1.164 +output jtag_break; // Request to raise a breakpoint exception 1.165 +reg jtag_break; 1.166 +output jtag_reset; // Request to raise a reset exception 1.167 +reg jtag_reset; 1.168 +`endif 1.169 +output [`LM32_BYTE_RNG] jtag_reg_d; 1.170 +reg [`LM32_BYTE_RNG] jtag_reg_d; 1.171 +output [2:0] jtag_reg_addr_d; 1.172 +wire [2:0] jtag_reg_addr_d; 1.173 + 1.174 +///////////////////////////////////////////////////// 1.175 +// Internal nets and registers 1.176 +///////////////////////////////////////////////////// 1.177 + 1.178 +reg rx_toggle; // Clock-domain crossing registers 1.179 +reg rx_toggle_r; // Registered version of rx_toggle 1.180 +reg rx_toggle_r_r; // Registered version of rx_toggle_r 1.181 +reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r 1.182 + 1.183 +reg [`LM32_BYTE_RNG] rx_byte; 1.184 +reg [2:0] rx_addr; 1.185 + 1.186 +`ifdef CFG_JTAG_UART_ENABLED 1.187 +reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data 1.188 +reg uart_tx_valid; // TX data is valid 1.189 +reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data 1.190 +reg uart_rx_valid; // RX data is valid 1.191 +`endif 1.192 + 1.193 +reg [`LM32_DP_RNG] command; // The last received command 1.194 +`ifdef CFG_HW_DEBUG_ENABLED 1.195 +reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters 1.196 +reg [`LM32_BYTE_RNG] jtag_byte_1; 1.197 +reg [`LM32_BYTE_RNG] jtag_byte_2; 1.198 +reg [`LM32_BYTE_RNG] jtag_byte_3; 1.199 +reg [`LM32_BYTE_RNG] jtag_byte_4; 1.200 +reg processing; // Indicates if we're still processing a memory read/write 1.201 +`endif 1.202 + 1.203 +reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM 1.204 + 1.205 +///////////////////////////////////////////////////// 1.206 +// Combinational Logic 1.207 +///////////////////////////////////////////////////// 1.208 + 1.209 +`ifdef CFG_HW_DEBUG_ENABLED 1.210 +assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; 1.211 +assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG]; 1.212 +assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3}; 1.213 +assign jtag_write_data = jtag_byte_4; 1.214 +`endif 1.215 + 1.216 +// Generate status flags for reading via the JTAG interface 1.217 +`ifdef CFG_JTAG_UART_ENABLED 1.218 +assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid}; 1.219 +`else 1.220 +assign jtag_reg_addr_d[1:0] = 2'b00; 1.221 +`endif 1.222 +`ifdef CFG_HW_DEBUG_ENABLED 1.223 +assign jtag_reg_addr_d[2] = processing; 1.224 +`else 1.225 +assign jtag_reg_addr_d[2] = 1'b0; 1.226 +`endif 1.227 + 1.228 +`ifdef CFG_JTAG_UART_ENABLED 1.229 +assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00}; 1.230 +assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte}; 1.231 +`endif 1.232 + 1.233 +///////////////////////////////////////////////////// 1.234 +// Sequential Logic 1.235 +///////////////////////////////////////////////////// 1.236 + 1.237 +// Toggle a flag when a JTAG write occurs 1.238 + 1.239 +always @(negedge jtag_update `CFG_RESET_SENSITIVITY) 1.240 +begin 1.241 +if (rst_i == `TRUE) 1.242 + rx_toggle <= 1'b0; 1.243 +else 1.244 + rx_toggle <= ~rx_toggle; 1.245 +end 1.246 + 1.247 +always @(*) 1.248 +begin 1.249 + rx_byte = jtag_reg_q; 1.250 + rx_addr = jtag_reg_addr_q; 1.251 +end 1.252 + 1.253 +// Clock domain crossing from JTAG clock domain to CPU clock domain 1.254 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.255 +begin 1.256 + if (rst_i == `TRUE) 1.257 + begin 1.258 + rx_toggle_r <= 1'b0; 1.259 + rx_toggle_r_r <= 1'b0; 1.260 + rx_toggle_r_r_r <= 1'b0; 1.261 + end 1.262 + else 1.263 + begin 1.264 + rx_toggle_r <= rx_toggle; 1.265 + rx_toggle_r_r <= rx_toggle_r; 1.266 + rx_toggle_r_r_r <= rx_toggle_r_r; 1.267 + end 1.268 +end 1.269 + 1.270 +// LM32 debug protocol state machine 1.271 +always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.272 +begin 1.273 + if (rst_i == `TRUE) 1.274 + begin 1.275 + state <= `LM32_JTAG_STATE_READ_COMMAND; 1.276 + command <= 4'b0000; 1.277 + jtag_reg_d <= 8'h00; 1.278 +`ifdef CFG_HW_DEBUG_ENABLED 1.279 + processing <= `FALSE; 1.280 + jtag_csr_write_enable <= `FALSE; 1.281 + jtag_read_enable <= `FALSE; 1.282 + jtag_write_enable <= `FALSE; 1.283 +`endif 1.284 +`ifdef CFG_DEBUG_ENABLED 1.285 + jtag_break <= `FALSE; 1.286 + jtag_reset <= `FALSE; 1.287 +`endif 1.288 +`ifdef CFG_JTAG_UART_ENABLED 1.289 + uart_tx_byte <= 8'h00; 1.290 + uart_tx_valid <= `FALSE; 1.291 + uart_rx_byte <= 8'h00; 1.292 + uart_rx_valid <= `FALSE; 1.293 +`endif 1.294 + end 1.295 + else 1.296 + begin 1.297 +`ifdef CFG_JTAG_UART_ENABLED 1.298 + if ((csr_write_enable == `TRUE) && (stall_x == `FALSE)) 1.299 + begin 1.300 + case (csr) 1.301 + `LM32_CSR_JTX: 1.302 + begin 1.303 + // Set flag indicating data is available 1.304 + uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG]; 1.305 + uart_tx_valid <= `TRUE; 1.306 + end 1.307 + `LM32_CSR_JRX: 1.308 + begin 1.309 + // Clear flag indidicating data has been received 1.310 + uart_rx_valid <= `FALSE; 1.311 + end 1.312 + endcase 1.313 + end 1.314 +`endif 1.315 +`ifdef CFG_DEBUG_ENABLED 1.316 + // When an exception has occured, clear the requests 1.317 + if (exception_q_w == `TRUE) 1.318 + begin 1.319 + jtag_break <= `FALSE; 1.320 + jtag_reset <= `FALSE; 1.321 + end 1.322 +`endif 1.323 + case (state) 1.324 + `LM32_JTAG_STATE_READ_COMMAND: 1.325 + begin 1.326 + // Wait for rx register to toggle which indicates new data is available 1.327 + if (rx_toggle_r_r != rx_toggle_r_r_r) 1.328 + begin 1.329 + command <= rx_byte[7:4]; 1.330 + case (rx_addr) 1.331 +`ifdef CFG_DEBUG_ENABLED 1.332 + `LM32_DP: 1.333 + begin 1.334 + case (rx_byte[7:4]) 1.335 +`ifdef CFG_HW_DEBUG_ENABLED 1.336 + `LM32_DP_READ_MEMORY: 1.337 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 1.338 + `LM32_DP_READ_SEQUENTIAL: 1.339 + begin 1.340 + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 1.341 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 1.342 + end 1.343 + `LM32_DP_WRITE_MEMORY: 1.344 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 1.345 + `LM32_DP_WRITE_SEQUENTIAL: 1.346 + begin 1.347 + {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1; 1.348 + state <= 5; 1.349 + end 1.350 + `LM32_DP_WRITE_CSR: 1.351 + state <= `LM32_JTAG_STATE_READ_BYTE_0; 1.352 +`endif 1.353 + `LM32_DP_BREAK: 1.354 + begin 1.355 +`ifdef CFG_JTAG_UART_ENABLED 1.356 + uart_rx_valid <= `FALSE; 1.357 + uart_tx_valid <= `FALSE; 1.358 +`endif 1.359 + jtag_break <= `TRUE; 1.360 + end 1.361 + `LM32_DP_RESET: 1.362 + begin 1.363 +`ifdef CFG_JTAG_UART_ENABLED 1.364 + uart_rx_valid <= `FALSE; 1.365 + uart_tx_valid <= `FALSE; 1.366 +`endif 1.367 + jtag_reset <= `TRUE; 1.368 + end 1.369 + endcase 1.370 + end 1.371 +`endif 1.372 +`ifdef CFG_JTAG_UART_ENABLED 1.373 + `LM32_TX: 1.374 + begin 1.375 + uart_rx_byte <= rx_byte; 1.376 + uart_rx_valid <= `TRUE; 1.377 + end 1.378 + `LM32_RX: 1.379 + begin 1.380 + jtag_reg_d <= uart_tx_byte; 1.381 + uart_tx_valid <= `FALSE; 1.382 + end 1.383 +`endif 1.384 + default: 1.385 + ; 1.386 + endcase 1.387 + end 1.388 + end 1.389 +`ifdef CFG_HW_DEBUG_ENABLED 1.390 + `LM32_JTAG_STATE_READ_BYTE_0: 1.391 + begin 1.392 + if (rx_toggle_r_r != rx_toggle_r_r_r) 1.393 + begin 1.394 + jtag_byte_0 <= rx_byte; 1.395 + state <= `LM32_JTAG_STATE_READ_BYTE_1; 1.396 + end 1.397 + end 1.398 + `LM32_JTAG_STATE_READ_BYTE_1: 1.399 + begin 1.400 + if (rx_toggle_r_r != rx_toggle_r_r_r) 1.401 + begin 1.402 + jtag_byte_1 <= rx_byte; 1.403 + state <= `LM32_JTAG_STATE_READ_BYTE_2; 1.404 + end 1.405 + end 1.406 + `LM32_JTAG_STATE_READ_BYTE_2: 1.407 + begin 1.408 + if (rx_toggle_r_r != rx_toggle_r_r_r) 1.409 + begin 1.410 + jtag_byte_2 <= rx_byte; 1.411 + state <= `LM32_JTAG_STATE_READ_BYTE_3; 1.412 + end 1.413 + end 1.414 + `LM32_JTAG_STATE_READ_BYTE_3: 1.415 + begin 1.416 + if (rx_toggle_r_r != rx_toggle_r_r_r) 1.417 + begin 1.418 + jtag_byte_3 <= rx_byte; 1.419 + if (command == `LM32_DP_READ_MEMORY) 1.420 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 1.421 + else 1.422 + state <= `LM32_JTAG_STATE_READ_BYTE_4; 1.423 + end 1.424 + end 1.425 + `LM32_JTAG_STATE_READ_BYTE_4: 1.426 + begin 1.427 + if (rx_toggle_r_r != rx_toggle_r_r_r) 1.428 + begin 1.429 + jtag_byte_4 <= rx_byte; 1.430 + state <= `LM32_JTAG_STATE_PROCESS_COMMAND; 1.431 + end 1.432 + end 1.433 + `LM32_JTAG_STATE_PROCESS_COMMAND: 1.434 + begin 1.435 + case (command) 1.436 + `LM32_DP_READ_MEMORY, 1.437 + `LM32_DP_READ_SEQUENTIAL: 1.438 + begin 1.439 + jtag_read_enable <= `TRUE; 1.440 + processing <= `TRUE; 1.441 + state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 1.442 + end 1.443 + `LM32_DP_WRITE_MEMORY, 1.444 + `LM32_DP_WRITE_SEQUENTIAL: 1.445 + begin 1.446 + jtag_write_enable <= `TRUE; 1.447 + processing <= `TRUE; 1.448 + state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY; 1.449 + end 1.450 + `LM32_DP_WRITE_CSR: 1.451 + begin 1.452 + jtag_csr_write_enable <= `TRUE; 1.453 + processing <= `TRUE; 1.454 + state <= `LM32_JTAG_STATE_WAIT_FOR_CSR; 1.455 + end 1.456 + endcase 1.457 + end 1.458 + `LM32_JTAG_STATE_WAIT_FOR_MEMORY: 1.459 + begin 1.460 + if (jtag_access_complete == `TRUE) 1.461 + begin 1.462 + jtag_read_enable <= `FALSE; 1.463 + jtag_reg_d <= jtag_read_data; 1.464 + jtag_write_enable <= `FALSE; 1.465 + processing <= `FALSE; 1.466 + state <= `LM32_JTAG_STATE_READ_COMMAND; 1.467 + end 1.468 + end 1.469 + `LM32_JTAG_STATE_WAIT_FOR_CSR: 1.470 + begin 1.471 + jtag_csr_write_enable <= `FALSE; 1.472 + processing <= `FALSE; 1.473 + state <= `LM32_JTAG_STATE_READ_COMMAND; 1.474 + end 1.475 +`endif 1.476 + endcase 1.477 + end 1.478 +end 1.479 + 1.480 +endmodule 1.481 + 1.482 +`endif