lm32_monitor.v

changeset 0
cd0b58aa6f83
child 8
07be9df9fee8
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/lm32_monitor.v	Sun Apr 04 20:40:03 2010 +0100
     1.3 @@ -0,0 +1,173 @@
     1.4 +// =============================================================================
     1.5 +//                           COPYRIGHT NOTICE
     1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 +// ALL RIGHTS RESERVED
     1.8 +// This confidential and proprietary software may be used only as authorised by
     1.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 +// The entire notice above must be reproduced on all authorized copies and
    1.11 +// copies may only be made to the extent permitted by a licensing agreement from
    1.12 +// Lattice Semiconductor Corporation.
    1.13 +//
    1.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.17 +// U.S.A                                   email: techsupport@latticesemi.com
    1.18 +// =============================================================================/
    1.19 +//                         FILE DETAILS
    1.20 +// Project          : LatticeMico32
    1.21 +// File             : lm32_monitor.v
    1.22 +// Title            : Debug monitor memory Wishbone interface
    1.23 +// Version          : 6.1.17
    1.24 +//                  : Initial Release
    1.25 +// Version          : 7.0SP2, 3.0
    1.26 +//                  : No Change
    1.27 +// Version          : 3.3
    1.28 +//                  : Removed port mismatch in instantiation of module
    1.29 +//                  : lm32_monitor_ram.
    1.30 +// =============================================================================
    1.31 +
    1.32 +`include "system_conf.v"
    1.33 +`include "lm32_include.v"
    1.34 +
    1.35 +/////////////////////////////////////////////////////
    1.36 +// Module interface
    1.37 +/////////////////////////////////////////////////////
    1.38 +
    1.39 +module lm32_monitor (
    1.40 +    // ----- Inputs -------
    1.41 +    clk_i, 
    1.42 +    rst_i,
    1.43 +    MON_ADR_I,
    1.44 +    MON_CYC_I,
    1.45 +    MON_DAT_I,
    1.46 +    MON_SEL_I,
    1.47 +    MON_STB_I,
    1.48 +    MON_WE_I,
    1.49 +    MON_LOCK_I,
    1.50 +    MON_CTI_I,
    1.51 +    MON_BTE_I,
    1.52 +    // ----- Outputs -------
    1.53 +    MON_ACK_O,
    1.54 +    MON_RTY_O,
    1.55 +    MON_DAT_O,
    1.56 +    MON_ERR_O
    1.57 +    );
    1.58 +
    1.59 +/////////////////////////////////////////////////////
    1.60 +// Inputs
    1.61 +/////////////////////////////////////////////////////
    1.62 +
    1.63 +input clk_i;                                        // Wishbone clock
    1.64 +input rst_i;                                        // Wishbone reset
    1.65 +input [`LM32_WORD_RNG] MON_ADR_I;                   // Wishbone address
    1.66 +input MON_STB_I;                                    // Wishbone strobe
    1.67 +input MON_CYC_I;                                    // Wishbone cycle
    1.68 +input [`LM32_WORD_RNG] MON_DAT_I;                   // Wishbone write data
    1.69 +input [`LM32_BYTE_SELECT_RNG] MON_SEL_I;            // Wishbone byte select
    1.70 +input MON_WE_I;                                     // Wishbone write enable
    1.71 +input MON_LOCK_I;                                   // Wishbone locked transfer
    1.72 +input [`LM32_CTYPE_RNG] MON_CTI_I;                  // Wishbone cycle type
    1.73 +input [`LM32_BTYPE_RNG] MON_BTE_I;                  // Wishbone burst type
    1.74 +   
    1.75 +/////////////////////////////////////////////////////
    1.76 +// Outputs
    1.77 +/////////////////////////////////////////////////////
    1.78 +
    1.79 +output MON_ACK_O;                                   // Wishbone acknowlege
    1.80 +reg    MON_ACK_O;
    1.81 +output [`LM32_WORD_RNG] MON_DAT_O;                  // Wishbone data output
    1.82 +reg    [`LM32_WORD_RNG] MON_DAT_O;
    1.83 +output MON_RTY_O;                                   // Wishbone retry
    1.84 +wire   MON_RTY_O;       
    1.85 +output MON_ERR_O;                                   // Wishbone error
    1.86 +wire   MON_ERR_O;
    1.87 +   
    1.88 +/////////////////////////////////////////////////////
    1.89 +// Internal nets and registers 
    1.90 +/////////////////////////////////////////////////////
    1.91 +
    1.92 +reg [1:0] state;                                    // Current state of FSM
    1.93 +wire [`LM32_WORD_RNG] data, dataB;                  // Data read from RAM
    1.94 +reg write_enable;                                   // RAM write enable
    1.95 +reg [`LM32_WORD_RNG] write_data;                    // RAM write data
    1.96 + 
    1.97 +/////////////////////////////////////////////////////
    1.98 +// Instantiations
    1.99 +/////////////////////////////////////////////////////
   1.100 +
   1.101 +lm32_monitor_ram ram (
   1.102 +    // ----- Inputs -------
   1.103 +    .ClockA             (clk_i),
   1.104 +    .ClockB             (clk_i),
   1.105 +    .ResetA             (rst_i),
   1.106 +    .ResetB             (rst_i),
   1.107 +    .ClockEnA           (`TRUE),
   1.108 +    .ClockEnB           (`FALSE),
   1.109 +    .AddressA           (MON_ADR_I[10:2]),
   1.110 +    .AddressB           (9'b0),
   1.111 +    .DataInA            (write_data),
   1.112 +    .DataInB            (32'b0),
   1.113 +    .WrA                (write_enable),
   1.114 +    .WrB                (`FALSE),
   1.115 +    // ----- Outputs -------
   1.116 +    .QA                 (data),
   1.117 +    .QB                 (dataB)
   1.118 +    );
   1.119 +
   1.120 +/////////////////////////////////////////////////////
   1.121 +// Combinational Logic
   1.122 +/////////////////////////////////////////////////////
   1.123 +
   1.124 +assign MON_RTY_O = `FALSE;
   1.125 +assign MON_ERR_O = `FALSE;
   1.126 +
   1.127 +/////////////////////////////////////////////////////
   1.128 +// Sequential Logic
   1.129 +/////////////////////////////////////////////////////
   1.130 +
   1.131 +always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.132 +begin
   1.133 +    if (rst_i == `TRUE)
   1.134 +    begin
   1.135 +        write_enable <= `FALSE;
   1.136 +        MON_ACK_O <= `FALSE;
   1.137 +        MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
   1.138 +        state <= 2'b00;
   1.139 +    end
   1.140 +    else
   1.141 +    begin
   1.142 +        case (state)
   1.143 +        2'b00:
   1.144 +        begin
   1.145 +            // Wait for a Wishbone access
   1.146 +            if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
   1.147 +                state <= 2'b01;
   1.148 +        end
   1.149 +        2'b01:
   1.150 +        begin
   1.151 +            // Output read data to Wishbone
   1.152 +            MON_ACK_O <= `TRUE;
   1.153 +            MON_DAT_O <= data;
   1.154 +            // Sub-word writes are performed using read-modify-write  
   1.155 +            // as the Lattice EBRs don't support byte enables
   1.156 +            if (MON_WE_I == `TRUE)
   1.157 +                write_enable <= `TRUE;
   1.158 +            write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
   1.159 +            write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
   1.160 +            write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
   1.161 +            write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
   1.162 +            state <= 2'b10;
   1.163 +        end
   1.164 +        2'b10:
   1.165 +        begin
   1.166 +            // Wishbone access occurs in this cycle
   1.167 +            write_enable <= `FALSE;
   1.168 +            MON_ACK_O <= `FALSE;
   1.169 +            MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
   1.170 +            state <= 2'b00;
   1.171 +        end
   1.172 +        endcase        
   1.173 +    end
   1.174 +end
   1.175 +
   1.176 +endmodule