1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/spiprog.v Sun Apr 04 20:40:03 2010 +0100 1.3 @@ -0,0 +1,193 @@ 1.4 +// ============================================================================= 1.5 +// COPYRIGHT NOTICE 1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation 1.7 +// ALL RIGHTS RESERVED 1.8 +// This confidential and proprietary software may be used only as authorised by 1.9 +// a licensing agreement from Lattice Semiconductor Corporation. 1.10 +// The entire notice above must be reproduced on all authorized copies and 1.11 +// copies may only be made to the extent permitted by a licensing agreement from 1.12 +// Lattice Semiconductor Corporation. 1.13 +// 1.14 +// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) 1.15 +// 5555 NE Moore Court 408-826-6000 (other locations) 1.16 +// Hillsboro, OR 97124 web : http://www.latticesemi.com/ 1.17 +// U.S.A email: techsupport@latticesemi.com 1.18 +// =============================================================================/ 1.19 +// FILE DETAILS 1.20 +// Project : LatticeMico32 1.21 +// File : SPIPROG.v 1.22 +// This module contains the ER2 regsiters of SPI Serial FLASH programmer IP 1.23 +// core. There are only three ER2 registers, one control register and two 1.24 +// data registers, in this IP core. The control register is a 8-bit wide 1.25 +// register for selecting which data register will be accessed when the 1.26 +// Control/Data# bit in ER1 register is low. Data register 0 is a readonly 1.27 +// ID register. It is composed of three register fields -- an 8-bit 1.28 +// "implementer", a 16-bit "IP_functionality", and a 12-bit "revision". 1.29 +// Data register 1 is a variable length register for sending commands to or 1.30 +// receiving readback data from the SPI Serial FLASH device. 1.31 +// Dependencies : None 1.32 +// Version : 6.1.17 1.33 +// 1. Reduced the the ID register (DR0) length from 36 bits to 8 bits. 1.34 +// 2. Same as TYPEA and TYPEB modules, use falling edge clock 1.35 +// for all TCK Flip-Flops. 1.36 +// 3. Added 7 delay Flip-Flops so that the DR1 readback data from 1.37 +// SPI Serial FLASH is in the byte boundary. 1.38 +// Version : 7.0SP2, 3.0 1.39 +// : No Change 1.40 +// Version : 3.1 1.41 +// : No Change 1.42 +// ============================================================================= 1.43 +//--------------------------------------------------------------------------- 1.44 +// 1.45 +//Name : SPIPROG.v 1.46 +// 1.47 +//Description: 1.48 +// 1.49 +// This module contains the ER2 regsiters of SPI Serial FLASH programmer IP 1.50 +// core. There are only three ER2 registers, one control register and two 1.51 +// data registers, in this IP core. The control register is a 8-bit wide 1.52 +// register for selecting which data register will be accessed when the 1.53 +// Control/Data# bit in ER1 register is low. Data register 0 is a readonly 1.54 +// ID register. It is composed of three register fields -- an 8-bit 1.55 +// "implementer", a 16-bit "IP_functionality", and a 12-bit "revision". 1.56 +// Data register 1 is a variable length register for sending commands to or 1.57 +// receiving readback data from the SPI Serial FLASH device. 1.58 +// 1.59 +//$Log: spiprog.vhd,v $ 1.60 +//Revision 1.2 2004-09-09 11:43:26-07 jhsin 1.61 +//1. Reduced the the ID register (DR0) length from 36 bits to 8 bits. 1.62 +//2. Same as TYPEA and TYPEB modules, use falling edge clock 1.63 +// for all TCK Flip-Flops. 1.64 +// 1.65 +//Revision 1.1 2004-08-12 13:22:05-07 jhsin 1.66 +//Added 7 delay Flip-Flops so that the DR1 readback data from SPI Serial FLASH is in the byte boundary. 1.67 +// 1.68 +//Revision 1.0 2004-08-03 18:35:56-07 jhsin 1.69 +//Initial revision 1.70 +// 1.71 +// 1.72 + 1.73 +module SPIPROG (input JTCK , 1.74 + input JTDI , 1.75 + output JTDO2 , 1.76 + input JSHIFT , 1.77 + input JUPDATE , 1.78 + input JRSTN , 1.79 + input JCE2 , 1.80 + input SPIPROG_ENABLE , 1.81 + input CONTROL_DATAN , 1.82 + output SPI_C , 1.83 + output SPI_D , 1.84 + output SPI_SN , 1.85 + input SPI_Q); 1.86 + 1.87 + wire er2Cr_enable ; 1.88 + wire er2Dr0_enable; 1.89 + wire er2Dr1_enable; 1.90 + 1.91 + wire tdo_er2Cr ; 1.92 + wire tdo_er2Dr0; 1.93 + wire tdo_er2Dr1; 1.94 + 1.95 + wire [7:0] encodedDrSelBits ; 1.96 + wire [8:0] er2CrTdiBit ; 1.97 + wire [8:0] er2Dr0TdiBit ; 1.98 + 1.99 + wire captureDrER2; 1.100 + reg spi_s ; 1.101 + reg [6:0] spi_q_dly; 1.102 + 1.103 + wire [7:0] ip_functionality_id; 1.104 + 1.105 + genvar i; 1.106 + 1.107 + // ------ Control Register 0 ------ 1.108 + 1.109 + assign er2Cr_enable = JCE2 & SPIPROG_ENABLE & CONTROL_DATAN; 1.110 + 1.111 + assign tdo_er2Cr = er2CrTdiBit[0]; 1.112 + 1.113 + // CR_BIT0_BIT7 1.114 + generate 1.115 + for(i=0; i<=7; i=i+1) 1.116 + begin:CR_BIT0_BIT7 1.117 + TYPEA BIT_N (.CLK (JTCK), 1.118 + .RESET_N (JRSTN), 1.119 + .CLKEN (er2Cr_enable), 1.120 + .TDI (er2CrTdiBit[i + 1]), 1.121 + .TDO (er2CrTdiBit[i]), 1.122 + .DATA_OUT (encodedDrSelBits[i]), 1.123 + .DATA_IN (encodedDrSelBits[i]), 1.124 + .CAPTURE_DR (captureDrER2), 1.125 + .UPDATE_DR (JUPDATE)); 1.126 + end 1.127 + endgenerate // CR_BIT0_BIT7 1.128 + 1.129 + assign er2CrTdiBit[8] = JTDI; 1.130 + 1.131 +// ------ Data Register 0 ------ 1.132 + assign er2Dr0_enable = (JCE2 & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000000)) ? 1'b1 : 1'b0; 1.133 + 1.134 + assign tdo_er2Dr0 = er2Dr0TdiBit[0]; 1.135 + 1.136 + assign ip_functionality_id = 8'b00000001; //-- SPI Serial FLASH Programmer (0x01) 1.137 + 1.138 +// DR0_BIT0_BIT7 1.139 + generate 1.140 + for(i=0; i<=7; i=i+1) 1.141 + begin:DR0_BIT0_BIT7 1.142 + TYPEB BIT_N (.CLK (JTCK), 1.143 + .RESET_N (JRSTN), 1.144 + .CLKEN (er2Dr0_enable), 1.145 + .TDI (er2Dr0TdiBit[i + 1]), 1.146 + .TDO (er2Dr0TdiBit[i]), 1.147 + .DATA_IN (ip_functionality_id[i]), 1.148 + .CAPTURE_DR (captureDrER2)); 1.149 + end 1.150 + endgenerate // DR0_BIT0_BIT7 1.151 + 1.152 + assign er2Dr0TdiBit[8] = JTDI; 1.153 + 1.154 +// ------ Data Register 1 ------ 1.155 + 1.156 + assign er2Dr1_enable = (JCE2 & JSHIFT & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000001)) ? 1'b1 : 1'b0; 1.157 + 1.158 + assign SPI_C = ~ (JTCK & er2Dr1_enable & spi_s); 1.159 + 1.160 + assign SPI_D = JTDI & er2Dr1_enable; 1.161 + 1.162 + // SPI_S_Proc 1.163 + always @(negedge JTCK or negedge JRSTN) 1.164 + begin 1.165 + if (~JRSTN) 1.166 + spi_s <= 1'b0; 1.167 + else 1.168 + if (JUPDATE) 1.169 + spi_s <= 1'b0; 1.170 + else 1.171 + spi_s <= er2Dr1_enable; 1.172 + end 1.173 + 1.174 + assign SPI_SN = ~spi_s; 1.175 + 1.176 + // SPI_Q_Proc 1.177 + always @(negedge JTCK or negedge JRSTN) 1.178 + begin 1.179 + if (~JRSTN) 1.180 + spi_q_dly <= 'b0; 1.181 + else 1.182 + if (er2Dr1_enable) 1.183 + spi_q_dly <= {spi_q_dly[5:0],SPI_Q}; 1.184 + end 1.185 + 1.186 + assign tdo_er2Dr1 = spi_q_dly[6]; 1.187 + 1.188 + // ------ JTDO2 MUX ------ 1.189 + 1.190 + assign JTDO2 = CONTROL_DATAN ? tdo_er2Cr : 1.191 + (encodedDrSelBits == 8'b00000000) ? tdo_er2Dr0 : 1.192 + (encodedDrSelBits == 8'b00000001) ? tdo_er2Dr1 : 1'b0; 1.193 + 1.194 + assign captureDrER2 = ~JSHIFT & JCE2; 1.195 + 1.196 +endmodule