typea.v

changeset 0
cd0b58aa6f83
child 26
73de224304c1
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/typea.v	Sun Apr 04 20:40:03 2010 +0100
     1.3 @@ -0,0 +1,81 @@
     1.4 +// =============================================================================
     1.5 +//                           COPYRIGHT NOTICE
     1.6 +// Copyright 2006 (c) Lattice Semiconductor Corporation
     1.7 +// ALL RIGHTS RESERVED
     1.8 +// This confidential and proprietary software may be used only as authorised by
     1.9 +// a licensing agreement from Lattice Semiconductor Corporation.
    1.10 +// The entire notice above must be reproduced on all authorized copies and
    1.11 +// copies may only be made to the extent permitted by a licensing agreement from
    1.12 +// Lattice Semiconductor Corporation.
    1.13 +//
    1.14 +// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    1.15 +// 5555 NE Moore Court                            408-826-6000 (other locations)
    1.16 +// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    1.17 +// U.S.A                                   email: techsupport@latticesemi.com
    1.18 +// =============================================================================/
    1.19 +//                         FILE DETAILS
    1.20 +// Project          : LatticeMico32
    1.21 +// File             : TYPEA.v
    1.22 +// Description:
    1.23 +//    This is one of the two types of cells that are used to create ER1/ER2
    1.24 +//    register bits.
    1.25 +// Dependencies     : None
    1.26 +// Version          : 6.1.17
    1.27 +//   The SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 signals of the
    1.28 +//   dedicate logic JTAG_PORT didn't act as what their names implied.
    1.29 +//   The SHIFT_DR_CAPTURE_DR actually acts as SHIFT_DR.
    1.30 +//   The ENABLE_ER1/2 actually acts as SHIFT_DR_CAPTURE_DR.
    1.31 +//   These had caused a lot of headaches for a long time and now they are
    1.32 +//   fixed by:
    1.33 +//   (1) Use SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 to create
    1.34 +//       CAPTURE_DR for all typeA, typeB bits in the ER1, ER2 registers.
    1.35 +//   (2) Use ENABLE_ER1 or the enESR, enCSR, enBAR (these 3 signals
    1.36 +//       have the same waveform of ENABLE_ER2) directly to be the CLKEN
    1.37 +//       of all typeA, typeB bits in the ER1, ER2 registers.
    1.38 +//   (3) Modify typea.vhd to use only UPDATE_DR signal for the clock enable
    1.39 +//       of the holding flip-flop.
    1.40 +//   These changes caused ispTracy.vhd and cge.dat changes and the new
    1.41 +//   CGE.exe version will be 1.3.5.
    1.42 +// Version          : 7.0SP2, 3.0
    1.43 +//                  : No Change
    1.44 +// Version          : 3.1
    1.45 +//                  : No Change
    1.46 +// =============================================================================
    1.47 +module TYPEA(
    1.48 +      input CLK,
    1.49 +      input RESET_N,
    1.50 +      input CLKEN,
    1.51 +      input TDI,
    1.52 +      output TDO,
    1.53 +      output reg DATA_OUT,
    1.54 +      input DATA_IN,
    1.55 +      input CAPTURE_DR,
    1.56 +      input UPDATE_DR
    1.57 +   );
    1.58 +  
    1.59 +  reg tdoInt;
    1.60 +
    1.61 +
    1.62 +  always @ (negedge CLK or negedge RESET_N)
    1.63 +  begin
    1.64 +      if (RESET_N == 1'b0)
    1.65 +         tdoInt <= 1'b0;
    1.66 +      else if (CLK == 1'b0)
    1.67 +         if (CLKEN == 1'b1)
    1.68 +            if (CAPTURE_DR == 1'b0)
    1.69 +               tdoInt <= TDI;
    1.70 +            else
    1.71 +               tdoInt <= DATA_IN;
    1.72 +  end
    1.73 +
    1.74 +   assign TDO = tdoInt;
    1.75 +
    1.76 +  always @ (negedge CLK or negedge RESET_N)
    1.77 +   begin
    1.78 +      if (RESET_N == 1'b0)
    1.79 +         DATA_OUT <= 1'b0;
    1.80 +      else if (CLK == 1'b0)
    1.81 +         if (UPDATE_DR == 1'b1)
    1.82 +            DATA_OUT <= tdoInt;
    1.83 +   end
    1.84 +endmodule