lm32_cpu.v

changeset 27
d6c693415d59
parent 26
73de224304c1
     1.1 --- a/lm32_cpu.v	Sat Aug 06 00:02:46 2011 +0100
     1.2 +++ b/lm32_cpu.v	Sat Aug 06 01:26:56 2011 +0100
     1.3 @@ -1298,15 +1298,15 @@
     1.4     always @(posedge clk_i `CFG_RESET_SENSITIVITY)
     1.5       if (rst_i == `TRUE)
     1.6         begin
     1.7 -	  regfile_raw_0 <= #1 1'b0;
     1.8 -	  regfile_raw_1 <= #1 1'b0;
     1.9 -	  w_result_d <= #1 32'b0;
    1.10 +	  regfile_raw_0 <= 1'b0;
    1.11 +	  regfile_raw_1 <= 1'b0;
    1.12 +	  w_result_d <= 32'b0;
    1.13         end
    1.14       else
    1.15         begin
    1.16 -	  regfile_raw_0 <= #1 regfile_raw_0_nxt;
    1.17 -	  regfile_raw_1 <= #1 regfile_raw_1_nxt;
    1.18 -	  w_result_d <= #1 w_result;
    1.19 +	  regfile_raw_0 <= regfile_raw_0_nxt;
    1.20 +	  regfile_raw_1 <= regfile_raw_1_nxt;
    1.21 +	  w_result_d <= w_result;
    1.22         end
    1.23     
    1.24     /*----------------------------------------------------------------------
    1.25 @@ -2132,14 +2132,14 @@
    1.26  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.27  begin
    1.28      if (rst_i == `TRUE)
    1.29 -        eba <= #1 eba_reset[`LM32_PC_WIDTH+2-1:8];
    1.30 +        eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
    1.31      else
    1.32      begin
    1.33          if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
    1.34 -            eba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8];
    1.35 +            eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
    1.36  `ifdef CFG_HW_DEBUG_ENABLED
    1.37          if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
    1.38 -            eba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
    1.39 +            eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
    1.40  `endif
    1.41      end
    1.42  end
    1.43 @@ -2149,14 +2149,14 @@
    1.44  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.45  begin
    1.46      if (rst_i == `TRUE)
    1.47 -        deba <= #1 deba_reset[`LM32_PC_WIDTH+2-1:8];
    1.48 +        deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
    1.49      else
    1.50      begin
    1.51          if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
    1.52 -            deba <= #1 operand_1_x[`LM32_PC_WIDTH+2-1:8];
    1.53 +            deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
    1.54  `ifdef CFG_HW_DEBUG_ENABLED
    1.55          if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
    1.56 -            deba <= #1 jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
    1.57 +            deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
    1.58  `endif
    1.59      end
    1.60  end
    1.61 @@ -2167,9 +2167,9 @@
    1.62  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.63  begin
    1.64      if (rst_i == `TRUE)
    1.65 -        cc <= #1 {`LM32_WORD_WIDTH{1'b0}};
    1.66 +        cc <= {`LM32_WORD_WIDTH{1'b0}};
    1.67      else
    1.68 -        cc <= #1 cc + 1'b1;
    1.69 +        cc <= cc + 1'b1;
    1.70  end
    1.71  `endif
    1.72  
    1.73 @@ -2178,15 +2178,15 @@
    1.74  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.75  begin
    1.76      if (rst_i == `TRUE)
    1.77 -        data_bus_error_seen <= #1 `FALSE;
    1.78 +        data_bus_error_seen <= `FALSE;
    1.79      else
    1.80      begin
    1.81          // Set flag when bus error is detected
    1.82          if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
    1.83 -            data_bus_error_seen <= #1 `TRUE;
    1.84 +            data_bus_error_seen <= `TRUE;
    1.85          // Clear flag when exception is taken
    1.86          if ((exception_m == `TRUE) && (kill_m == `FALSE))
    1.87 -            data_bus_error_seen <= #1 `FALSE;
    1.88 +            data_bus_error_seen <= `FALSE;
    1.89      end
    1.90  end
    1.91  `endif
    1.92 @@ -2237,48 +2237,48 @@
    1.93  begin
    1.94      if (rst_i == `TRUE)
    1.95      begin
    1.96 -        valid_f <= #1 `FALSE;
    1.97 -        valid_d <= #1 `FALSE;
    1.98 -        valid_x <= #1 `FALSE;
    1.99 -        valid_m <= #1 `FALSE;
   1.100 -        valid_w <= #1 `FALSE;
   1.101 +        valid_f <= `FALSE;
   1.102 +        valid_d <= `FALSE;
   1.103 +        valid_x <= `FALSE;
   1.104 +        valid_m <= `FALSE;
   1.105 +        valid_w <= `FALSE;
   1.106      end
   1.107      else
   1.108      begin    
   1.109          if ((kill_f == `TRUE) || (stall_a == `FALSE))
   1.110  `ifdef LM32_CACHE_ENABLED
   1.111 -            valid_f <= #1 valid_a;    
   1.112 +            valid_f <= valid_a;    
   1.113  `else
   1.114 -            valid_f <= #1 `TRUE;
   1.115 +            valid_f <= `TRUE;
   1.116  `endif            
   1.117          else if (stall_f == `FALSE)
   1.118 -            valid_f <= #1 `FALSE;            
   1.119 +            valid_f <= `FALSE;            
   1.120  
   1.121          if (kill_d == `TRUE)
   1.122 -            valid_d <= #1 `FALSE;
   1.123 +            valid_d <= `FALSE;
   1.124          else if (stall_f == `FALSE)
   1.125 -            valid_d <= #1 valid_f & !kill_f;
   1.126 +            valid_d <= valid_f & !kill_f;
   1.127          else if (stall_d == `FALSE)
   1.128 -            valid_d <= #1 `FALSE;
   1.129 +            valid_d <= `FALSE;
   1.130         
   1.131          if (stall_d == `FALSE)
   1.132 -            valid_x <= #1 valid_d & !kill_d;
   1.133 +            valid_x <= valid_d & !kill_d;
   1.134          else if (kill_x == `TRUE)
   1.135 -            valid_x <= #1 `FALSE;
   1.136 +            valid_x <= `FALSE;
   1.137          else if (stall_x == `FALSE)
   1.138 -            valid_x <= #1 `FALSE;
   1.139 +            valid_x <= `FALSE;
   1.140  
   1.141          if (kill_m == `TRUE)
   1.142 -            valid_m <= #1 `FALSE;
   1.143 +            valid_m <= `FALSE;
   1.144          else if (stall_x == `FALSE)
   1.145 -            valid_m <= #1 valid_x & !kill_x;
   1.146 +            valid_m <= valid_x & !kill_x;
   1.147          else if (stall_m == `FALSE)
   1.148 -            valid_m <= #1 `FALSE;
   1.149 +            valid_m <= `FALSE;
   1.150  
   1.151          if (stall_m == `FALSE)
   1.152 -            valid_w <= #1 valid_m & !kill_m;
   1.153 +            valid_w <= valid_m & !kill_m;
   1.154          else 
   1.155 -            valid_w <= #1 `FALSE;        
   1.156 +            valid_w <= `FALSE;        
   1.157      end
   1.158  end
   1.159  
   1.160 @@ -2288,113 +2288,113 @@
   1.161      if (rst_i == `TRUE)
   1.162      begin
   1.163  `ifdef CFG_USER_ENABLED
   1.164 -        user_opcode <= #1 {`LM32_USER_OPCODE_WIDTH{1'b0}};       
   1.165 +        user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};       
   1.166  `endif        
   1.167 -        operand_0_x <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.168 -        operand_1_x <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.169 -        store_operand_x <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.170 -        branch_target_x <= #1 {`LM32_WORD_WIDTH{1'b0}};        
   1.171 -        x_result_sel_csr_x <= #1 `FALSE;
   1.172 +        operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
   1.173 +        operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
   1.174 +        store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
   1.175 +        branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};        
   1.176 +        x_result_sel_csr_x <= `FALSE;
   1.177  `ifdef LM32_MC_ARITHMETIC_ENABLED
   1.178 -        x_result_sel_mc_arith_x <= #1 `FALSE;
   1.179 +        x_result_sel_mc_arith_x <= `FALSE;
   1.180  `endif
   1.181  `ifdef LM32_NO_BARREL_SHIFT    
   1.182 -        x_result_sel_shift_x <= #1 `FALSE;
   1.183 +        x_result_sel_shift_x <= `FALSE;
   1.184  `endif
   1.185  `ifdef CFG_SIGN_EXTEND_ENABLED
   1.186 -        x_result_sel_sext_x <= #1 `FALSE;
   1.187 +        x_result_sel_sext_x <= `FALSE;
   1.188  `endif  
   1.189 -	x_result_sel_logic_x <= #1 `FALSE;
   1.190 +	x_result_sel_logic_x <= `FALSE;
   1.191  `ifdef CFG_USER_ENABLED
   1.192 -        x_result_sel_user_x <= #1 `FALSE;
   1.193 +        x_result_sel_user_x <= `FALSE;
   1.194  `endif
   1.195 -        x_result_sel_add_x <= #1 `FALSE;
   1.196 -        m_result_sel_compare_x <= #1 `FALSE;
   1.197 +        x_result_sel_add_x <= `FALSE;
   1.198 +        m_result_sel_compare_x <= `FALSE;
   1.199  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.200 -        m_result_sel_shift_x <= #1 `FALSE;
   1.201 +        m_result_sel_shift_x <= `FALSE;
   1.202  `endif    
   1.203 -        w_result_sel_load_x <= #1 `FALSE;
   1.204 +        w_result_sel_load_x <= `FALSE;
   1.205  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.206 -        w_result_sel_mul_x <= #1 `FALSE;
   1.207 +        w_result_sel_mul_x <= `FALSE;
   1.208  `endif
   1.209 -        x_bypass_enable_x <= #1 `FALSE;
   1.210 -        m_bypass_enable_x <= #1 `FALSE;
   1.211 -        write_enable_x <= #1 `FALSE;
   1.212 -        write_idx_x <= #1 {`LM32_REG_IDX_WIDTH{1'b0}};
   1.213 -        csr_x <= #1 {`LM32_CSR_WIDTH{1'b0}};
   1.214 -        load_x <= #1 `FALSE;
   1.215 -        store_x <= #1 `FALSE;
   1.216 -        size_x <= #1 {`LM32_SIZE_WIDTH{1'b0}};
   1.217 -        sign_extend_x <= #1 `FALSE;
   1.218 -        adder_op_x <= #1 `FALSE;
   1.219 -        adder_op_x_n <= #1 `FALSE;
   1.220 -        logic_op_x <= #1 4'h0;
   1.221 +        x_bypass_enable_x <= `FALSE;
   1.222 +        m_bypass_enable_x <= `FALSE;
   1.223 +        write_enable_x <= `FALSE;
   1.224 +        write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
   1.225 +        csr_x <= {`LM32_CSR_WIDTH{1'b0}};
   1.226 +        load_x <= `FALSE;
   1.227 +        store_x <= `FALSE;
   1.228 +        size_x <= {`LM32_SIZE_WIDTH{1'b0}};
   1.229 +        sign_extend_x <= `FALSE;
   1.230 +        adder_op_x <= `FALSE;
   1.231 +        adder_op_x_n <= `FALSE;
   1.232 +        logic_op_x <= 4'h0;
   1.233  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.234 -        direction_x <= #1 `FALSE;
   1.235 +        direction_x <= `FALSE;
   1.236  `endif
   1.237  `ifdef CFG_ROTATE_ENABLED
   1.238 -        rotate_x <= #1 `FALSE;
   1.239 +        rotate_x <= `FALSE;
   1.240  
   1.241  `endif
   1.242 -        branch_x <= #1 `FALSE;
   1.243 -        branch_predict_x <= #1 `FALSE;
   1.244 -        branch_predict_taken_x <= #1 `FALSE;
   1.245 -        condition_x <= #1 `LM32_CONDITION_U1;
   1.246 +        branch_x <= `FALSE;
   1.247 +        branch_predict_x <= `FALSE;
   1.248 +        branch_predict_taken_x <= `FALSE;
   1.249 +        condition_x <= `LM32_CONDITION_U1;
   1.250  `ifdef CFG_DEBUG_ENABLED
   1.251 -        break_x <= #1 `FALSE;
   1.252 +        break_x <= `FALSE;
   1.253  `endif
   1.254 -        scall_x <= #1 `FALSE;
   1.255 -        eret_x <= #1 `FALSE;
   1.256 +        scall_x <= `FALSE;
   1.257 +        eret_x <= `FALSE;
   1.258  `ifdef CFG_DEBUG_ENABLED
   1.259 -        bret_x <= #1 `FALSE;
   1.260 +        bret_x <= `FALSE;
   1.261  `endif
   1.262  `ifdef CFG_BUS_ERRORS_ENABLED
   1.263 -        bus_error_x <= #1 `FALSE;
   1.264 -        data_bus_error_exception_m <= #1 `FALSE;
   1.265 +        bus_error_x <= `FALSE;
   1.266 +        data_bus_error_exception_m <= `FALSE;
   1.267  `endif
   1.268 -        csr_write_enable_x <= #1 `FALSE;
   1.269 -        operand_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.270 -        branch_target_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.271 -        m_result_sel_compare_m <= #1 `FALSE;
   1.272 +        csr_write_enable_x <= `FALSE;
   1.273 +        operand_m <= {`LM32_WORD_WIDTH{1'b0}};
   1.274 +        branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
   1.275 +        m_result_sel_compare_m <= `FALSE;
   1.276  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.277 -        m_result_sel_shift_m <= #1 `FALSE;
   1.278 +        m_result_sel_shift_m <= `FALSE;
   1.279  `endif    
   1.280 -        w_result_sel_load_m <= #1 `FALSE;
   1.281 +        w_result_sel_load_m <= `FALSE;
   1.282  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.283 -        w_result_sel_mul_m <= #1 `FALSE;
   1.284 +        w_result_sel_mul_m <= `FALSE;
   1.285  `endif
   1.286 -        m_bypass_enable_m <= #1 `FALSE;
   1.287 -        branch_m <= #1 `FALSE;
   1.288 -        branch_predict_m <= #1 `FALSE;
   1.289 -	branch_predict_taken_m <= #1 `FALSE;
   1.290 -        exception_m <= #1 `FALSE;
   1.291 -        load_m <= #1 `FALSE;
   1.292 -        store_m <= #1 `FALSE;
   1.293 -        write_enable_m <= #1 `FALSE;            
   1.294 -        write_idx_m <= #1 {`LM32_REG_IDX_WIDTH{1'b0}};
   1.295 -        condition_met_m <= #1 `FALSE;
   1.296 +        m_bypass_enable_m <= `FALSE;
   1.297 +        branch_m <= `FALSE;
   1.298 +        branch_predict_m <= `FALSE;
   1.299 +	branch_predict_taken_m <= `FALSE;
   1.300 +        exception_m <= `FALSE;
   1.301 +        load_m <= `FALSE;
   1.302 +        store_m <= `FALSE;
   1.303 +        write_enable_m <= `FALSE;            
   1.304 +        write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
   1.305 +        condition_met_m <= `FALSE;
   1.306  `ifdef CFG_DCACHE_ENABLED
   1.307 -        dflush_m <= #1 `FALSE;
   1.308 +        dflush_m <= `FALSE;
   1.309  `endif
   1.310  `ifdef CFG_DEBUG_ENABLED
   1.311 -        debug_exception_m <= #1 `FALSE;
   1.312 -        non_debug_exception_m <= #1 `FALSE;        
   1.313 +        debug_exception_m <= `FALSE;
   1.314 +        non_debug_exception_m <= `FALSE;        
   1.315  `endif
   1.316 -        operand_w <= #1 {`LM32_WORD_WIDTH{1'b0}};        
   1.317 -        w_result_sel_load_w <= #1 `FALSE;
   1.318 +        operand_w <= {`LM32_WORD_WIDTH{1'b0}};        
   1.319 +        w_result_sel_load_w <= `FALSE;
   1.320  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.321 -        w_result_sel_mul_w <= #1 `FALSE;
   1.322 +        w_result_sel_mul_w <= `FALSE;
   1.323  `endif
   1.324 -        write_idx_w <= #1 {`LM32_REG_IDX_WIDTH{1'b0}};        
   1.325 -        write_enable_w <= #1 `FALSE;
   1.326 +        write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};        
   1.327 +        write_enable_w <= `FALSE;
   1.328  `ifdef CFG_DEBUG_ENABLED
   1.329 -        debug_exception_w <= #1 `FALSE;
   1.330 -        non_debug_exception_w <= #1 `FALSE;        
   1.331 +        debug_exception_w <= `FALSE;
   1.332 +        non_debug_exception_w <= `FALSE;        
   1.333  `else
   1.334 -        exception_w <= #1 `FALSE;
   1.335 +        exception_w <= `FALSE;
   1.336  `endif
   1.337  `ifdef CFG_BUS_ERRORS_ENABLED
   1.338 -        memop_pc_w <= #1 {`LM32_PC_WIDTH{1'b0}};
   1.339 +        memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
   1.340  `endif
   1.341      end
   1.342      else
   1.343 @@ -2404,105 +2404,105 @@
   1.344          if (stall_x == `FALSE)
   1.345          begin
   1.346  `ifdef CFG_USER_ENABLED
   1.347 -            user_opcode <= #1 user_opcode_d;       
   1.348 +            user_opcode <= user_opcode_d;       
   1.349  `endif        
   1.350 -            operand_0_x <= #1 d_result_0;
   1.351 -            operand_1_x <= #1 d_result_1;
   1.352 -            store_operand_x <= #1 bypass_data_1;
   1.353 -            branch_target_x <= #1 branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;            
   1.354 -            x_result_sel_csr_x <= #1 x_result_sel_csr_d;
   1.355 +            operand_0_x <= d_result_0;
   1.356 +            operand_1_x <= d_result_1;
   1.357 +            store_operand_x <= bypass_data_1;
   1.358 +            branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;            
   1.359 +            x_result_sel_csr_x <= x_result_sel_csr_d;
   1.360  `ifdef LM32_MC_ARITHMETIC_ENABLED
   1.361 -            x_result_sel_mc_arith_x <= #1 x_result_sel_mc_arith_d;
   1.362 +            x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
   1.363  `endif
   1.364  `ifdef LM32_NO_BARREL_SHIFT    
   1.365 -            x_result_sel_shift_x <= #1 x_result_sel_shift_d;
   1.366 +            x_result_sel_shift_x <= x_result_sel_shift_d;
   1.367  `endif
   1.368  `ifdef CFG_SIGN_EXTEND_ENABLED
   1.369 -            x_result_sel_sext_x <= #1 x_result_sel_sext_d;
   1.370 +            x_result_sel_sext_x <= x_result_sel_sext_d;
   1.371  `endif    
   1.372 -	    x_result_sel_logic_x <= #1 x_result_sel_logic_d;
   1.373 +	    x_result_sel_logic_x <= x_result_sel_logic_d;
   1.374  `ifdef CFG_USER_ENABLED
   1.375 -            x_result_sel_user_x <= #1 x_result_sel_user_d;
   1.376 +            x_result_sel_user_x <= x_result_sel_user_d;
   1.377  `endif
   1.378 -            x_result_sel_add_x <= #1 x_result_sel_add_d;
   1.379 -            m_result_sel_compare_x <= #1 m_result_sel_compare_d;
   1.380 +            x_result_sel_add_x <= x_result_sel_add_d;
   1.381 +            m_result_sel_compare_x <= m_result_sel_compare_d;
   1.382  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.383 -            m_result_sel_shift_x <= #1 m_result_sel_shift_d;
   1.384 +            m_result_sel_shift_x <= m_result_sel_shift_d;
   1.385  `endif    
   1.386 -            w_result_sel_load_x <= #1 w_result_sel_load_d;
   1.387 +            w_result_sel_load_x <= w_result_sel_load_d;
   1.388  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.389 -            w_result_sel_mul_x <= #1 w_result_sel_mul_d;
   1.390 +            w_result_sel_mul_x <= w_result_sel_mul_d;
   1.391  `endif
   1.392 -            x_bypass_enable_x <= #1 x_bypass_enable_d;
   1.393 -            m_bypass_enable_x <= #1 m_bypass_enable_d;
   1.394 -            load_x <= #1 load_d;
   1.395 -            store_x <= #1 store_d;
   1.396 -            branch_x <= #1 branch_d;
   1.397 -	    branch_predict_x <= #1 branch_predict_d;
   1.398 -	    branch_predict_taken_x <= #1 branch_predict_taken_d;
   1.399 -	    write_idx_x <= #1 write_idx_d;
   1.400 -            csr_x <= #1 csr_d;
   1.401 -            size_x <= #1 size_d;
   1.402 -            sign_extend_x <= #1 sign_extend_d;
   1.403 -            adder_op_x <= #1 adder_op_d;
   1.404 -            adder_op_x_n <= #1 ~adder_op_d;
   1.405 -            logic_op_x <= #1 logic_op_d;
   1.406 +            x_bypass_enable_x <= x_bypass_enable_d;
   1.407 +            m_bypass_enable_x <= m_bypass_enable_d;
   1.408 +            load_x <= load_d;
   1.409 +            store_x <= store_d;
   1.410 +            branch_x <= branch_d;
   1.411 +	    branch_predict_x <= branch_predict_d;
   1.412 +	    branch_predict_taken_x <= branch_predict_taken_d;
   1.413 +	    write_idx_x <= write_idx_d;
   1.414 +            csr_x <= csr_d;
   1.415 +            size_x <= size_d;
   1.416 +            sign_extend_x <= sign_extend_d;
   1.417 +            adder_op_x <= adder_op_d;
   1.418 +            adder_op_x_n <= ~adder_op_d;
   1.419 +            logic_op_x <= logic_op_d;
   1.420  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.421 -            direction_x <= #1 direction_d;
   1.422 +            direction_x <= direction_d;
   1.423  `endif
   1.424  `ifdef CFG_ROTATE_ENABLED
   1.425 -            rotate_x <= #1 rotate_d;
   1.426 +            rotate_x <= rotate_d;
   1.427  `endif
   1.428 -            condition_x <= #1 condition_d;
   1.429 -            csr_write_enable_x <= #1 csr_write_enable_d;
   1.430 +            condition_x <= condition_d;
   1.431 +            csr_write_enable_x <= csr_write_enable_d;
   1.432  `ifdef CFG_DEBUG_ENABLED
   1.433 -            break_x <= #1 break_d;
   1.434 +            break_x <= break_d;
   1.435  `endif
   1.436 -            scall_x <= #1 scall_d;
   1.437 +            scall_x <= scall_d;
   1.438  `ifdef CFG_BUS_ERRORS_ENABLED
   1.439 -            bus_error_x <= #1 bus_error_d;
   1.440 +            bus_error_x <= bus_error_d;
   1.441  `endif
   1.442 -            eret_x <= #1 eret_d;
   1.443 +            eret_x <= eret_d;
   1.444  `ifdef CFG_DEBUG_ENABLED
   1.445 -            bret_x <= #1 bret_d; 
   1.446 +            bret_x <= bret_d; 
   1.447  `endif
   1.448 -            write_enable_x <= #1 write_enable_d;
   1.449 +            write_enable_x <= write_enable_d;
   1.450          end
   1.451          
   1.452          // X/M stage registers
   1.453  
   1.454          if (stall_m == `FALSE)
   1.455          begin
   1.456 -            operand_m <= #1 x_result;
   1.457 -            m_result_sel_compare_m <= #1 m_result_sel_compare_x;
   1.458 +            operand_m <= x_result;
   1.459 +            m_result_sel_compare_m <= m_result_sel_compare_x;
   1.460  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.461 -            m_result_sel_shift_m <= #1 m_result_sel_shift_x;
   1.462 +            m_result_sel_shift_m <= m_result_sel_shift_x;
   1.463  `endif    
   1.464              if (exception_x == `TRUE)
   1.465              begin
   1.466 -                w_result_sel_load_m <= #1 `FALSE;
   1.467 +                w_result_sel_load_m <= `FALSE;
   1.468  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.469 -                w_result_sel_mul_m <= #1 `FALSE;
   1.470 +                w_result_sel_mul_m <= `FALSE;
   1.471  `endif
   1.472              end
   1.473              else
   1.474              begin
   1.475 -                w_result_sel_load_m <= #1 w_result_sel_load_x;
   1.476 +                w_result_sel_load_m <= w_result_sel_load_x;
   1.477  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.478 -                w_result_sel_mul_m <= #1 w_result_sel_mul_x;
   1.479 +                w_result_sel_mul_m <= w_result_sel_mul_x;
   1.480  `endif
   1.481              end
   1.482 -            m_bypass_enable_m <= #1 m_bypass_enable_x;
   1.483 +            m_bypass_enable_m <= m_bypass_enable_x;
   1.484  `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   1.485  `endif
   1.486 -            load_m <= #1 load_x;
   1.487 -            store_m <= #1 store_x;
   1.488 +            load_m <= load_x;
   1.489 +            store_m <= store_x;
   1.490  `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   1.491 -            branch_m <= #1 branch_x && !branch_taken_x;
   1.492 +            branch_m <= branch_x && !branch_taken_x;
   1.493  `else
   1.494 -            branch_m <= #1 branch_x;
   1.495 -	    branch_predict_m <= #1 branch_predict_x;
   1.496 -	    branch_predict_taken_m <= #1 branch_predict_taken_x;
   1.497 +            branch_m <= branch_x;
   1.498 +	    branch_predict_m <= branch_predict_x;
   1.499 +	    branch_predict_taken_m <= branch_predict_taken_x;
   1.500  `endif
   1.501  `ifdef CFG_DEBUG_ENABLED
   1.502  	   // Data bus errors are generated by the wishbone and are
   1.503 @@ -2511,18 +2511,18 @@
   1.504  	   // in same cycle (causing a debug exception). Handle non
   1.505  	   // -debug exception first!
   1.506              if (non_debug_exception_x == `TRUE) 
   1.507 -                write_idx_m <= #1 `LM32_EA_REG;
   1.508 +                write_idx_m <= `LM32_EA_REG;
   1.509              else if (debug_exception_x == `TRUE)
   1.510 -                write_idx_m <= #1 `LM32_BA_REG;
   1.511 +                write_idx_m <= `LM32_BA_REG;
   1.512              else 
   1.513 -                write_idx_m <= #1 write_idx_x;
   1.514 +                write_idx_m <= write_idx_x;
   1.515  `else
   1.516              if (exception_x == `TRUE)
   1.517 -                write_idx_m <= #1 `LM32_EA_REG;
   1.518 +                write_idx_m <= `LM32_EA_REG;
   1.519              else 
   1.520 -                write_idx_m <= #1 write_idx_x;
   1.521 +                write_idx_m <= write_idx_x;
   1.522  `endif
   1.523 -            condition_met_m <= #1 condition_met_x;
   1.524 +            condition_met_m <= condition_met_x;
   1.525  `ifdef CFG_DEBUG_ENABLED
   1.526  	   if (exception_x == `TRUE)
   1.527  	     if ((dc_re == `TRUE)
   1.528 @@ -2531,28 +2531,28 @@
   1.529   `endif
   1.530  		 || ((debug_exception_x == `TRUE) 
   1.531  		     && (non_debug_exception_x == `FALSE)))
   1.532 -	       branch_target_m <= #1 {deba, eid_x, {3{1'b0}}};
   1.533 +	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
   1.534  	     else
   1.535 -	       branch_target_m <= #1 {eba, eid_x, {3{1'b0}}};
   1.536 +	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
   1.537  	   else
   1.538 -	     branch_target_m <= #1 branch_target_x;
   1.539 +	     branch_target_m <= branch_target_x;
   1.540  `else
   1.541 -            branch_target_m <= #1 exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
   1.542 +            branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
   1.543  `endif
   1.544  `ifdef CFG_TRACE_ENABLED
   1.545 -            eid_m <= #1 eid_x;
   1.546 +            eid_m <= eid_x;
   1.547  `endif
   1.548  `ifdef CFG_DCACHE_ENABLED
   1.549 -            dflush_m <= #1 dflush_x;
   1.550 +            dflush_m <= dflush_x;
   1.551  `endif
   1.552 -            eret_m <= #1 eret_q_x;
   1.553 +            eret_m <= eret_q_x;
   1.554  `ifdef CFG_DEBUG_ENABLED
   1.555 -            bret_m <= #1 bret_q_x; 
   1.556 +            bret_m <= bret_q_x; 
   1.557  `endif
   1.558 -            write_enable_m <= #1 exception_x == `TRUE ? `TRUE : write_enable_x;            
   1.559 +            write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;            
   1.560  `ifdef CFG_DEBUG_ENABLED
   1.561 -            debug_exception_m <= #1 debug_exception_x;
   1.562 -            non_debug_exception_m <= #1 non_debug_exception_x;        
   1.563 +            debug_exception_m <= debug_exception_x;
   1.564 +            non_debug_exception_m <= non_debug_exception_x;        
   1.565  `endif
   1.566          end
   1.567          
   1.568 @@ -2560,11 +2560,11 @@
   1.569          if (stall_m == `FALSE)
   1.570          begin
   1.571              if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
   1.572 -                exception_m <= #1 `TRUE;
   1.573 +                exception_m <= `TRUE;
   1.574              else 
   1.575 -                exception_m <= #1 `FALSE;
   1.576 +                exception_m <= `FALSE;
   1.577  `ifdef CFG_BUS_ERRORS_ENABLED
   1.578 -	   data_bus_error_exception_m <= #1    (data_bus_error_exception == `TRUE) 
   1.579 +	   data_bus_error_exception_m <=    (data_bus_error_exception == `TRUE) 
   1.580  `ifdef CFG_DEBUG_ENABLED
   1.581  					 && (reset_exception == `FALSE)
   1.582  `endif
   1.583 @@ -2574,28 +2574,28 @@
   1.584                  
   1.585          // M/W stage registers
   1.586  `ifdef CFG_BUS_ERRORS_ENABLED
   1.587 -        operand_w <= #1 exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
   1.588 +        operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
   1.589  `else
   1.590 -        operand_w <= #1 exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
   1.591 +        operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
   1.592  `endif
   1.593 -        w_result_sel_load_w <= #1 w_result_sel_load_m;
   1.594 +        w_result_sel_load_w <= w_result_sel_load_m;
   1.595  `ifdef CFG_PL_MULTIPLY_ENABLED
   1.596 -        w_result_sel_mul_w <= #1 w_result_sel_mul_m;
   1.597 +        w_result_sel_mul_w <= w_result_sel_mul_m;
   1.598  `endif
   1.599 -        write_idx_w <= #1 write_idx_m;
   1.600 +        write_idx_w <= write_idx_m;
   1.601  `ifdef CFG_TRACE_ENABLED
   1.602 -        eid_w <= #1 eid_m;
   1.603 -        eret_w <= #1 eret_m;
   1.604 +        eid_w <= eid_m;
   1.605 +        eret_w <= eret_m;
   1.606  `ifdef CFG_DEBUG_ENABLED
   1.607 -        bret_w <= #1 bret_m; 
   1.608 +        bret_w <= bret_m; 
   1.609  `endif
   1.610  `endif
   1.611 -        write_enable_w <= #1 write_enable_m;
   1.612 +        write_enable_w <= write_enable_m;
   1.613  `ifdef CFG_DEBUG_ENABLED
   1.614 -        debug_exception_w <= #1 debug_exception_m;
   1.615 -        non_debug_exception_w <= #1 non_debug_exception_m;
   1.616 +        debug_exception_w <= debug_exception_m;
   1.617 +        non_debug_exception_w <= non_debug_exception_m;
   1.618  `else
   1.619 -        exception_w <= #1 exception_m;
   1.620 +        exception_w <= exception_m;
   1.621  `endif
   1.622  `ifdef CFG_BUS_ERRORS_ENABLED
   1.623          if (   (stall_m == `FALSE)
   1.624 @@ -2604,7 +2604,7 @@
   1.625                  || (store_q_m == `TRUE)
   1.626                 )
   1.627  	   )
   1.628 -          memop_pc_w <= #1 pc_m;
   1.629 +          memop_pc_w <= pc_m;
   1.630  `endif
   1.631      end
   1.632  end
   1.633 @@ -2616,26 +2616,26 @@
   1.634  begin
   1.635      if (rst_i == `TRUE)
   1.636      begin
   1.637 -        use_buf <= #1 `FALSE;
   1.638 -        reg_data_buf_0 <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.639 -        reg_data_buf_1 <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.640 +        use_buf <= `FALSE;
   1.641 +        reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
   1.642 +        reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
   1.643      end
   1.644      else
   1.645      begin
   1.646          if (stall_d == `FALSE)
   1.647 -            use_buf <= #1 `FALSE;
   1.648 +            use_buf <= `FALSE;
   1.649          else if (use_buf == `FALSE)
   1.650          begin        
   1.651 -            reg_data_buf_0 <= #1 reg_data_live_0;
   1.652 -            reg_data_buf_1 <= #1 reg_data_live_1;
   1.653 -            use_buf <= #1 `TRUE;
   1.654 +            reg_data_buf_0 <= reg_data_live_0;
   1.655 +            reg_data_buf_1 <= reg_data_live_1;
   1.656 +            use_buf <= `TRUE;
   1.657          end        
   1.658          if (reg_write_enable_q_w == `TRUE)
   1.659          begin
   1.660              if (write_idx_w == read_idx_0_d)
   1.661 -                reg_data_buf_0 <= #1 w_result;
   1.662 +                reg_data_buf_0 <= w_result;
   1.663              if (write_idx_w == read_idx_1_d)
   1.664 -                reg_data_buf_1 <= #1 w_result;
   1.665 +                reg_data_buf_1 <= w_result;
   1.666          end
   1.667      end
   1.668  end
   1.669 @@ -2647,42 +2647,42 @@
   1.670  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.671  begin
   1.672      if (rst_i == `TRUE) begin
   1.673 -        registers[0] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.674 -        registers[1] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.675 -        registers[2] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.676 -        registers[3] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.677 -        registers[4] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.678 -        registers[5] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.679 -        registers[6] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.680 -        registers[7] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.681 -        registers[8] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.682 -        registers[9] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.683 -        registers[10] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.684 -        registers[11] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.685 -        registers[12] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.686 -        registers[13] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.687 -        registers[14] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.688 -        registers[15] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.689 -        registers[16] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.690 -        registers[17] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.691 -        registers[18] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.692 -        registers[19] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.693 -        registers[20] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.694 -        registers[21] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.695 -        registers[22] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.696 -        registers[23] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.697 -        registers[24] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.698 -        registers[25] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.699 -        registers[26] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.700 -        registers[27] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.701 -        registers[28] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.702 -        registers[29] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.703 -        registers[30] <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.704 -        registers[31] <= #1 {`LM32_WORD_WIDTH{1'b0}}; 
   1.705 +        registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
   1.706 +        registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
   1.707 +        registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
   1.708 +        registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
   1.709 +        registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
   1.710 +        registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
   1.711 +        registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
   1.712 +        registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
   1.713 +        registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
   1.714 +        registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
   1.715 +        registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
   1.716 +        registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
   1.717 +        registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
   1.718 +        registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
   1.719 +        registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
   1.720 +        registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
   1.721 +        registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
   1.722 +        registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
   1.723 +        registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
   1.724 +        registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
   1.725 +        registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
   1.726 +        registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
   1.727 +        registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
   1.728 +        registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
   1.729 +        registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
   1.730 +        registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
   1.731 +        registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
   1.732 +        registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
   1.733 +        registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
   1.734 +        registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
   1.735 +        registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
   1.736 +        registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 
   1.737          end
   1.738      else begin
   1.739          if (reg_write_enable_q_w == `TRUE)
   1.740 -          registers[write_idx_w] <= #1 w_result;
   1.741 +          registers[write_idx_w] <= w_result;
   1.742          end
   1.743  end
   1.744  `endif
   1.745 @@ -2693,19 +2693,19 @@
   1.746  begin
   1.747      if (rst_i == `TRUE)
   1.748      begin
   1.749 -        trace_pc_valid <= #1 `FALSE;
   1.750 -        trace_pc <= #1 {`LM32_PC_WIDTH{1'b0}};
   1.751 -        trace_exception <= #1 `FALSE;
   1.752 -        trace_eid <= #1 `LM32_EID_RESET;
   1.753 -        trace_eret <= #1 `FALSE;
   1.754 +        trace_pc_valid <= `FALSE;
   1.755 +        trace_pc <= {`LM32_PC_WIDTH{1'b0}};
   1.756 +        trace_exception <= `FALSE;
   1.757 +        trace_eid <= `LM32_EID_RESET;
   1.758 +        trace_eret <= `FALSE;
   1.759  `ifdef CFG_DEBUG_ENABLED
   1.760 -        trace_bret <= #1 `FALSE;
   1.761 +        trace_bret <= `FALSE;
   1.762  `endif
   1.763 -        pc_c <= #1 `CFG_EBA_RESET/4;
   1.764 +        pc_c <= `CFG_EBA_RESET/4;
   1.765      end
   1.766      else
   1.767      begin
   1.768 -        trace_pc_valid <= #1 `FALSE;
   1.769 +        trace_pc_valid <= `FALSE;
   1.770          // Has an exception occured
   1.771  `ifdef CFG_DEBUG_ENABLED
   1.772          if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
   1.773 @@ -2713,13 +2713,13 @@
   1.774          if (exception_q_w == `TRUE)
   1.775  `endif
   1.776          begin        
   1.777 -            trace_exception <= #1 `TRUE;
   1.778 -            trace_pc_valid <= #1 `TRUE;
   1.779 -            trace_pc <= #1 pc_w;
   1.780 -            trace_eid <= #1 eid_w;
   1.781 +            trace_exception <= `TRUE;
   1.782 +            trace_pc_valid <= `TRUE;
   1.783 +            trace_pc <= pc_w;
   1.784 +            trace_eid <= eid_w;
   1.785          end
   1.786          else
   1.787 -            trace_exception <= #1 `FALSE;
   1.788 +            trace_exception <= `FALSE;
   1.789          
   1.790          if ((valid_w == `TRUE) && (!kill_w))
   1.791          begin
   1.792 @@ -2727,22 +2727,22 @@
   1.793              if (pc_c + 1'b1 != pc_w)
   1.794              begin
   1.795                  // Non-sequential instruction
   1.796 -                trace_pc_valid <= #1 `TRUE;
   1.797 -                trace_pc <= #1 pc_w;
   1.798 +                trace_pc_valid <= `TRUE;
   1.799 +                trace_pc <= pc_w;
   1.800              end
   1.801              // Record PC so we can determine if next instruction is sequential or not
   1.802 -            pc_c <= #1 pc_w;
   1.803 +            pc_c <= pc_w;
   1.804              // Indicate if it was an eret/bret instruction
   1.805 -            trace_eret <= #1 eret_w;
   1.806 +            trace_eret <= eret_w;
   1.807  `ifdef CFG_DEBUG_ENABLED
   1.808 -            trace_bret <= #1 bret_w;
   1.809 +            trace_bret <= bret_w;
   1.810  `endif
   1.811          end
   1.812          else
   1.813          begin
   1.814 -            trace_eret <= #1 `FALSE;
   1.815 +            trace_eret <= `FALSE;
   1.816  `ifdef CFG_DEBUG_ENABLED
   1.817 -            trace_bret <= #1 `FALSE;
   1.818 +            trace_bret <= `FALSE;
   1.819  `endif
   1.820          end
   1.821      end