1.1 --- a/lm32_dcache.v Sat Aug 06 00:02:46 2011 +0100 1.2 +++ b/lm32_dcache.v Sat Aug 06 01:26:56 2011 +0100 1.3 @@ -441,11 +441,11 @@ 1.4 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.5 begin 1.6 if (rst_i == `TRUE) 1.7 - refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1}; 1.8 + refill_way_select <= {{associativity-1{1'b0}}, 1'b1}; 1.9 else 1.10 begin 1.11 if (refill_request == `TRUE) 1.12 - refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]}; 1.13 + refill_way_select <= {refill_way_select[0], refill_way_select[1]}; 1.14 end 1.15 end 1.16 end 1.17 @@ -455,9 +455,9 @@ 1.18 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.19 begin 1.20 if (rst_i == `TRUE) 1.21 - refilling <= #1 `FALSE; 1.22 + refilling <= `FALSE; 1.23 else 1.24 - refilling <= #1 refill; 1.25 + refilling <= refill; 1.26 end 1.27 1.28 // Instruction cache control FSM 1.29 @@ -465,11 +465,11 @@ 1.30 begin 1.31 if (rst_i == `TRUE) 1.32 begin 1.33 - state <= #1 `LM32_DC_STATE_FLUSH; 1.34 - flush_set <= #1 {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 1.35 - refill_request <= #1 `FALSE; 1.36 - refill_address <= #1 {`LM32_WORD_WIDTH{1'bx}}; 1.37 - restart_request <= #1 `FALSE; 1.38 + state <= `LM32_DC_STATE_FLUSH; 1.39 + flush_set <= {`LM32_DC_TMEM_ADDR_WIDTH{1'b1}}; 1.40 + refill_request <= `FALSE; 1.41 + refill_address <= {`LM32_WORD_WIDTH{1'bx}}; 1.42 + restart_request <= `FALSE; 1.43 end 1.44 else 1.45 begin 1.46 @@ -479,35 +479,35 @@ 1.47 `LM32_DC_STATE_FLUSH: 1.48 begin 1.49 if (flush_set == {`LM32_DC_TMEM_ADDR_WIDTH{1'b0}}) 1.50 - state <= #1 `LM32_DC_STATE_CHECK; 1.51 - flush_set <= #1 flush_set - 1'b1; 1.52 + state <= `LM32_DC_STATE_CHECK; 1.53 + flush_set <= flush_set - 1'b1; 1.54 end 1.55 1.56 // Check for cache misses 1.57 `LM32_DC_STATE_CHECK: 1.58 begin 1.59 if (stall_a == `FALSE) 1.60 - restart_request <= #1 `FALSE; 1.61 + restart_request <= `FALSE; 1.62 if (miss == `TRUE) 1.63 begin 1.64 - refill_request <= #1 `TRUE; 1.65 - refill_address <= #1 address_m; 1.66 - state <= #1 `LM32_DC_STATE_REFILL; 1.67 + refill_request <= `TRUE; 1.68 + refill_address <= address_m; 1.69 + state <= `LM32_DC_STATE_REFILL; 1.70 end 1.71 else if (dflush == `TRUE) 1.72 - state <= #1 `LM32_DC_STATE_FLUSH; 1.73 + state <= `LM32_DC_STATE_FLUSH; 1.74 end 1.75 1.76 // Refill a cache line 1.77 `LM32_DC_STATE_REFILL: 1.78 begin 1.79 - refill_request <= #1 `FALSE; 1.80 + refill_request <= `FALSE; 1.81 if (refill_ready == `TRUE) 1.82 begin 1.83 if (last_refill == `TRUE) 1.84 begin 1.85 - restart_request <= #1 `TRUE; 1.86 - state <= #1 `LM32_DC_STATE_CHECK; 1.87 + restart_request <= `TRUE; 1.88 + state <= `LM32_DC_STATE_CHECK; 1.89 end 1.90 end 1.91 end 1.92 @@ -523,7 +523,7 @@ 1.93 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.94 begin 1.95 if (rst_i == `TRUE) 1.96 - refill_offset <= #1 {addr_offset_width{1'b0}}; 1.97 + refill_offset <= {addr_offset_width{1'b0}}; 1.98 else 1.99 begin 1.100 case (state) 1.101 @@ -532,14 +532,14 @@ 1.102 `LM32_DC_STATE_CHECK: 1.103 begin 1.104 if (miss == `TRUE) 1.105 - refill_offset <= #1 {addr_offset_width{1'b0}}; 1.106 + refill_offset <= {addr_offset_width{1'b0}}; 1.107 end 1.108 1.109 // Refill a cache line 1.110 `LM32_DC_STATE_REFILL: 1.111 begin 1.112 if (refill_ready == `TRUE) 1.113 - refill_offset <= #1 refill_offset + 1'b1; 1.114 + refill_offset <= refill_offset + 1'b1; 1.115 end 1.116 1.117 endcase