1.1 --- a/lm32_debug.v Sat Aug 06 00:02:46 2011 +0100 1.2 +++ b/lm32_debug.v Sat Aug 06 01:26:56 2011 +0100 1.3 @@ -247,15 +247,15 @@ 1.4 begin 1.5 if (rst_i == `TRUE) 1.6 begin 1.7 - bp_a[i] <= #1 {`LM32_PC_WIDTH{1'bx}}; 1.8 - bp_e[i] <= #1 `FALSE; 1.9 + bp_a[i] <= {`LM32_PC_WIDTH{1'bx}}; 1.10 + bp_e[i] <= `FALSE; 1.11 end 1.12 else 1.13 begin 1.14 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i)) 1.15 begin 1.16 - bp_a[i] <= #1 debug_csr_write_data[`LM32_PC_RNG]; 1.17 - bp_e[i] <= #1 debug_csr_write_data[0]; 1.18 + bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG]; 1.19 + bp_e[i] <= debug_csr_write_data[0]; 1.20 end 1.21 end 1.22 end 1.23 @@ -270,17 +270,17 @@ 1.24 begin 1.25 if (rst_i == `TRUE) 1.26 begin 1.27 - wp[i] <= #1 {`LM32_WORD_WIDTH{1'bx}}; 1.28 - wpc_c[i] <= #1 `LM32_WPC_C_DISABLED; 1.29 + wp[i] <= {`LM32_WORD_WIDTH{1'bx}}; 1.30 + wpc_c[i] <= `LM32_WPC_C_DISABLED; 1.31 end 1.32 else 1.33 begin 1.34 if (debug_csr_write_enable == `TRUE) 1.35 begin 1.36 if (debug_csr == `LM32_CSR_DC) 1.37 - wpc_c[i] <= #1 debug_csr_write_data[3+i*2:2+i*2]; 1.38 + wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2]; 1.39 if (debug_csr == `LM32_CSR_WP0 + i) 1.40 - wp[i] <= #1 debug_csr_write_data; 1.41 + wp[i] <= debug_csr_write_data; 1.42 end 1.43 end 1.44 end 1.45 @@ -291,11 +291,11 @@ 1.46 always @(posedge clk_i `CFG_RESET_SENSITIVITY) 1.47 begin 1.48 if (rst_i == `TRUE) 1.49 - dc_re <= #1 `FALSE; 1.50 + dc_re <= `FALSE; 1.51 else 1.52 begin 1.53 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 1.54 - dc_re <= #1 debug_csr_write_data[1]; 1.55 + dc_re <= debug_csr_write_data[1]; 1.56 end 1.57 end 1.58 1.59 @@ -305,18 +305,18 @@ 1.60 begin 1.61 if (rst_i == `TRUE) 1.62 begin 1.63 - state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 1.64 - dc_ss <= #1 `FALSE; 1.65 + state <= `LM32_DEBUG_SS_STATE_IDLE; 1.66 + dc_ss <= `FALSE; 1.67 end 1.68 else 1.69 begin 1.70 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC)) 1.71 begin 1.72 - dc_ss <= #1 debug_csr_write_data[0]; 1.73 + dc_ss <= debug_csr_write_data[0]; 1.74 if (debug_csr_write_data[0] == `FALSE) 1.75 - state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 1.76 + state <= `LM32_DEBUG_SS_STATE_IDLE; 1.77 else 1.78 - state <= #1 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 1.79 + state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET; 1.80 end 1.81 case (state) 1.82 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET: 1.83 @@ -327,26 +327,26 @@ 1.84 ) 1.85 && (stall_x == `FALSE) 1.86 ) 1.87 - state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.88 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.89 end 1.90 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN: 1.91 begin 1.92 // Wait for an instruction to be executed 1.93 if ((q_x == `TRUE) && (stall_x == `FALSE)) 1.94 - state <= #1 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 1.95 + state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT; 1.96 end 1.97 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT: 1.98 begin 1.99 // Wait for exception to be raised 1.100 `ifdef CFG_DCACHE_ENABLED 1.101 if (dcache_refill_request == `TRUE) 1.102 - state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.103 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.104 else 1.105 `endif 1.106 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE)) 1.107 begin 1.108 - dc_ss <= #1 `FALSE; 1.109 - state <= #1 `LM32_DEBUG_SS_STATE_RESTART; 1.110 + dc_ss <= `FALSE; 1.111 + state <= `LM32_DEBUG_SS_STATE_RESTART; 1.112 end 1.113 end 1.114 `LM32_DEBUG_SS_STATE_RESTART: 1.115 @@ -354,10 +354,10 @@ 1.116 // Watch to see if stepped instruction is restarted due to a cache miss 1.117 `ifdef CFG_DCACHE_ENABLED 1.118 if (dcache_refill_request == `TRUE) 1.119 - state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.120 + state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 1.121 else 1.122 `endif 1.123 - state <= #1 `LM32_DEBUG_SS_STATE_IDLE; 1.124 + state <= `LM32_DEBUG_SS_STATE_IDLE; 1.125 end 1.126 endcase 1.127 end