lm32_icache.v

changeset 27
d6c693415d59
parent 26
73de224304c1
     1.1 --- a/lm32_icache.v	Sat Aug 06 00:02:46 2011 +0100
     1.2 +++ b/lm32_icache.v	Sat Aug 06 01:26:56 2011 +0100
     1.3 @@ -380,11 +380,11 @@
     1.4  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
     1.5  begin
     1.6      if (rst_i == `TRUE)
     1.7 -        refill_way_select <= #1 {{associativity-1{1'b0}}, 1'b1};
     1.8 +        refill_way_select <= {{associativity-1{1'b0}}, 1'b1};
     1.9      else
    1.10      begin        
    1.11          if (miss == `TRUE)
    1.12 -            refill_way_select <= #1 {refill_way_select[0], refill_way_select[1]};
    1.13 +            refill_way_select <= {refill_way_select[0], refill_way_select[1]};
    1.14      end
    1.15  end
    1.16      end
    1.17 @@ -394,9 +394,9 @@
    1.18  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.19  begin
    1.20      if (rst_i == `TRUE)
    1.21 -        refilling <= #1 `FALSE;
    1.22 +        refilling <= `FALSE;
    1.23      else
    1.24 -        refilling <= #1 refill;
    1.25 +        refilling <= refill;
    1.26  end
    1.27  
    1.28  // Instruction cache control FSM
    1.29 @@ -404,10 +404,10 @@
    1.30  begin
    1.31      if (rst_i == `TRUE)
    1.32      begin
    1.33 -        state <= #1 `LM32_IC_STATE_FLUSH_INIT;
    1.34 -        flush_set <= #1 {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
    1.35 -        refill_address <= #1 {`LM32_PC_WIDTH{1'bx}};
    1.36 -        restart_request <= #1 `FALSE;
    1.37 +        state <= `LM32_IC_STATE_FLUSH_INIT;
    1.38 +        flush_set <= {`LM32_IC_TMEM_ADDR_WIDTH{1'b1}};
    1.39 +        refill_address <= {`LM32_PC_WIDTH{1'bx}};
    1.40 +        restart_request <= `FALSE;
    1.41      end
    1.42      else 
    1.43      begin
    1.44 @@ -417,8 +417,8 @@
    1.45          `LM32_IC_STATE_FLUSH_INIT:
    1.46          begin            
    1.47              if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
    1.48 -                state <= #1 `LM32_IC_STATE_CHECK;
    1.49 -            flush_set <= #1 flush_set - 1'b1;
    1.50 +                state <= `LM32_IC_STATE_CHECK;
    1.51 +            flush_set <= flush_set - 1'b1;
    1.52          end
    1.53  
    1.54          // Flush the cache in response to an write to the ICC CSR
    1.55 @@ -427,28 +427,28 @@
    1.56              if (flush_set == {`LM32_IC_TMEM_ADDR_WIDTH{1'b0}})
    1.57  `ifdef CFG_IROM_ENABLED
    1.58  	      if (select_f)
    1.59 -                state <= #1 `LM32_IC_STATE_REFILL;
    1.60 +                state <= `LM32_IC_STATE_REFILL;
    1.61  	      else
    1.62  `endif
    1.63 -		state <= #1 `LM32_IC_STATE_CHECK;
    1.64 +		state <= `LM32_IC_STATE_CHECK;
    1.65  	   
    1.66 -            flush_set <= #1 flush_set - 1'b1;
    1.67 +            flush_set <= flush_set - 1'b1;
    1.68          end
    1.69          
    1.70          // Check for cache misses
    1.71          `LM32_IC_STATE_CHECK:
    1.72          begin            
    1.73              if (stall_a == `FALSE)
    1.74 -                restart_request <= #1 `FALSE;
    1.75 +                restart_request <= `FALSE;
    1.76              if (iflush == `TRUE)
    1.77              begin
    1.78 -                refill_address <= #1 address_f;
    1.79 -                state <= #1 `LM32_IC_STATE_FLUSH;
    1.80 +                refill_address <= address_f;
    1.81 +                state <= `LM32_IC_STATE_FLUSH;
    1.82              end
    1.83              else if (miss == `TRUE)
    1.84              begin
    1.85 -                refill_address <= #1 address_f;
    1.86 -                state <= #1 `LM32_IC_STATE_REFILL;
    1.87 +                refill_address <= address_f;
    1.88 +                state <= `LM32_IC_STATE_REFILL;
    1.89              end
    1.90          end
    1.91  
    1.92 @@ -459,8 +459,8 @@
    1.93              begin
    1.94                  if (last_refill == `TRUE)
    1.95                  begin
    1.96 -                    restart_request <= #1 `TRUE;
    1.97 -                    state <= #1 `LM32_IC_STATE_CHECK;
    1.98 +                    restart_request <= `TRUE;
    1.99 +                    state <= `LM32_IC_STATE_CHECK;
   1.100                  end
   1.101              end
   1.102          end
   1.103 @@ -476,7 +476,7 @@
   1.104  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   1.105  begin
   1.106      if (rst_i == `TRUE)
   1.107 -        refill_offset <= #1 {addr_offset_width{1'b0}};
   1.108 +        refill_offset <= {addr_offset_width{1'b0}};
   1.109      else 
   1.110      begin
   1.111          case (state)
   1.112 @@ -485,16 +485,16 @@
   1.113          `LM32_IC_STATE_CHECK:
   1.114          begin            
   1.115              if (iflush == `TRUE)
   1.116 -                refill_offset <= #1 {addr_offset_width{1'b0}};
   1.117 +                refill_offset <= {addr_offset_width{1'b0}};
   1.118              else if (miss == `TRUE)
   1.119 -                refill_offset <= #1 {addr_offset_width{1'b0}};
   1.120 +                refill_offset <= {addr_offset_width{1'b0}};
   1.121          end
   1.122  
   1.123          // Refill a cache line
   1.124          `LM32_IC_STATE_REFILL:
   1.125          begin            
   1.126              if (refill_ready == `TRUE)
   1.127 -                refill_offset <= #1 refill_offset + 1'b1;
   1.128 +                refill_offset <= refill_offset + 1'b1;
   1.129          end
   1.130  
   1.131          endcase