lm32_instruction_unit.v

changeset 27
d6c693415d59
parent 26
73de224304c1
     1.1 --- a/lm32_instruction_unit.v	Sat Aug 06 00:02:46 2011 +0100
     1.2 +++ b/lm32_instruction_unit.v	Sat Aug 06 01:26:56 2011 +0100
     1.3 @@ -587,31 +587,31 @@
     1.4  `ifdef CFG_DEBUG_ENABLED
     1.5   `ifdef CFG_ALTERNATE_EBA
     1.6  	  if (at_debug == `TRUE)
     1.7 -	    pc_f <= #1 (`CFG_DEBA_RESET-4)/4;
     1.8 +	    pc_f <= (`CFG_DEBA_RESET-4)/4;
     1.9  	  else
    1.10 -	    pc_f <= #1 (`CFG_EBA_RESET-4)/4;
    1.11 +	    pc_f <= (`CFG_EBA_RESET-4)/4;
    1.12   `else
    1.13 -	  pc_f <= #1 (`CFG_EBA_RESET-4)/4;
    1.14 +	  pc_f <= (`CFG_EBA_RESET-4)/4;
    1.15   `endif
    1.16  `else
    1.17 -          pc_f <= #1 (`CFG_EBA_RESET-4)/4;
    1.18 +          pc_f <= (`CFG_EBA_RESET-4)/4;
    1.19  `endif
    1.20 -          pc_d <= #1 {`LM32_PC_WIDTH{1'b0}};
    1.21 -          pc_x <= #1 {`LM32_PC_WIDTH{1'b0}};
    1.22 -          pc_m <= #1 {`LM32_PC_WIDTH{1'b0}};
    1.23 -          pc_w <= #1 {`LM32_PC_WIDTH{1'b0}};
    1.24 +          pc_d <= {`LM32_PC_WIDTH{1'b0}};
    1.25 +          pc_x <= {`LM32_PC_WIDTH{1'b0}};
    1.26 +          pc_m <= {`LM32_PC_WIDTH{1'b0}};
    1.27 +          pc_w <= {`LM32_PC_WIDTH{1'b0}};
    1.28         end
    1.29       else
    1.30         begin
    1.31            if (stall_f == `FALSE)
    1.32 -            pc_f <= #1 pc_a;
    1.33 +            pc_f <= pc_a;
    1.34            if (stall_d == `FALSE)
    1.35 -            pc_d <= #1 pc_f;
    1.36 +            pc_d <= pc_f;
    1.37            if (stall_x == `FALSE)
    1.38 -            pc_x <= #1 pc_d;
    1.39 +            pc_x <= pc_d;
    1.40            if (stall_m == `FALSE)
    1.41 -            pc_m <= #1 pc_x;
    1.42 -          pc_w <= #1 pc_m;
    1.43 +            pc_m <= pc_x;
    1.44 +          pc_w <= pc_m;
    1.45         end
    1.46    end
    1.47  
    1.48 @@ -620,24 +620,24 @@
    1.49  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.50  begin
    1.51      if (rst_i == `TRUE)
    1.52 -        restart_address <= #1 {`LM32_PC_WIDTH{1'b0}};
    1.53 +        restart_address <= {`LM32_PC_WIDTH{1'b0}};
    1.54      else
    1.55      begin
    1.56  `ifdef CFG_DCACHE_ENABLED
    1.57  `ifdef CFG_ICACHE_ENABLED        
    1.58              // D-cache restart address must take priority, otherwise instructions will be lost
    1.59              if (dcache_refill_request == `TRUE)
    1.60 -                restart_address <= #1 pc_w;
    1.61 +                restart_address <= pc_w;
    1.62              else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request))
    1.63 -                restart_address <= #1 icache_refill_address;
    1.64 +                restart_address <= icache_refill_address;
    1.65  `else
    1.66              if (dcache_refill_request == `TRUE)
    1.67 -                restart_address <= #1 pc_w;
    1.68 +                restart_address <= pc_w;
    1.69  `endif
    1.70  `else
    1.71  `ifdef CFG_ICACHE_ENABLED        
    1.72              if (icache_refill_request == `TRUE)
    1.73 -                restart_address <= #1 icache_refill_address;
    1.74 +                restart_address <= icache_refill_address;
    1.75  `endif
    1.76  `endif
    1.77      end
    1.78 @@ -649,11 +649,11 @@
    1.79  always @(posedge clk_i `CFG_RESET_SENSITIVITY)
    1.80  begin
    1.81      if (rst_i == `TRUE)
    1.82 -        irom_select_f <= #1 `FALSE;
    1.83 +        irom_select_f <= `FALSE;
    1.84      else
    1.85      begin
    1.86          if (stall_f == `FALSE)
    1.87 -            irom_select_f <= #1 irom_select_a;
    1.88 +            irom_select_f <= irom_select_a;
    1.89      end
    1.90  end
    1.91  `endif
    1.92 @@ -678,25 +678,25 @@
    1.93  begin
    1.94      if (rst_i == `TRUE)
    1.95      begin
    1.96 -        i_cyc_o <= #1 `FALSE;
    1.97 -        i_stb_o <= #1 `FALSE;
    1.98 -        i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
    1.99 -        i_cti_o <= #1 `LM32_CTYPE_END;
   1.100 -        i_lock_o <= #1 `FALSE;
   1.101 -        icache_refill_data <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}};
   1.102 -        icache_refill_ready <= #1 `FALSE;
   1.103 +        i_cyc_o <= `FALSE;
   1.104 +        i_stb_o <= `FALSE;
   1.105 +        i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
   1.106 +        i_cti_o <= `LM32_CTYPE_END;
   1.107 +        i_lock_o <= `FALSE;
   1.108 +        icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
   1.109 +        icache_refill_ready <= `FALSE;
   1.110  `ifdef CFG_BUS_ERRORS_ENABLED
   1.111 -        bus_error_f <= #1 `FALSE;
   1.112 +        bus_error_f <= `FALSE;
   1.113  `endif
   1.114  `ifdef CFG_HW_DEBUG_ENABLED
   1.115 -        i_we_o <= #1 `FALSE;
   1.116 -        i_sel_o <= #1 4'b1111;
   1.117 -        jtag_access <= #1 `FALSE;
   1.118 +        i_we_o <= `FALSE;
   1.119 +        i_sel_o <= 4'b1111;
   1.120 +        jtag_access <= `FALSE;
   1.121  `endif
   1.122      end
   1.123      else
   1.124      begin   
   1.125 -        icache_refill_ready <= #1 `FALSE;
   1.126 +        icache_refill_ready <= `FALSE;
   1.127          // Is a cycle in progress?
   1.128          if (i_cyc_o == `TRUE)
   1.129          begin
   1.130 @@ -706,10 +706,10 @@
   1.131  `ifdef CFG_HW_DEBUG_ENABLED
   1.132                  if (jtag_access == `TRUE)
   1.133                  begin
   1.134 -                    i_cyc_o <= #1 `FALSE;
   1.135 -                    i_stb_o <= #1 `FALSE;       
   1.136 -                    i_we_o <= #1 `FALSE;  
   1.137 -                    jtag_access <= #1 `FALSE;    
   1.138 +                    i_cyc_o <= `FALSE;
   1.139 +                    i_stb_o <= `FALSE;       
   1.140 +                    i_we_o <= `FALSE;  
   1.141 +                    jtag_access <= `FALSE;    
   1.142                  end
   1.143                  else
   1.144  `endif
   1.145 @@ -717,22 +717,22 @@
   1.146                      if (last_word == `TRUE)
   1.147                      begin
   1.148                          // Cache line fill complete 
   1.149 -                        i_cyc_o <= #1 `FALSE;
   1.150 -                        i_stb_o <= #1 `FALSE;
   1.151 -                        i_lock_o <= #1 `FALSE;
   1.152 +                        i_cyc_o <= `FALSE;
   1.153 +                        i_stb_o <= `FALSE;
   1.154 +                        i_lock_o <= `FALSE;
   1.155                      end
   1.156                      // Fetch next word in cache line
   1.157 -                    i_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
   1.158 -                    i_cti_o <= #1 next_cycle_type;
   1.159 +                    i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
   1.160 +                    i_cti_o <= next_cycle_type;
   1.161                      // Write fetched data into instruction cache
   1.162 -                    icache_refill_ready <= #1 `TRUE;
   1.163 -                    icache_refill_data <= #1 i_dat_i;
   1.164 +                    icache_refill_ready <= `TRUE;
   1.165 +                    icache_refill_data <= i_dat_i;
   1.166                  end
   1.167              end
   1.168  `ifdef CFG_BUS_ERRORS_ENABLED
   1.169              if (i_err_i == `TRUE)
   1.170              begin
   1.171 -                bus_error_f <= #1 `TRUE;
   1.172 +                bus_error_f <= `TRUE;
   1.173                  $display ("Instruction bus error. Address: %x", i_adr_o);
   1.174              end
   1.175  `endif
   1.176 @@ -743,15 +743,15 @@
   1.177              begin
   1.178                  // Read first word of cache line
   1.179  `ifdef CFG_HW_DEBUG_ENABLED     
   1.180 -                i_sel_o <= #1 4'b1111;
   1.181 +                i_sel_o <= 4'b1111;
   1.182  `endif
   1.183 -                i_adr_o <= #1 {first_address, 2'b00};
   1.184 -                i_cyc_o <= #1 `TRUE;
   1.185 -                i_stb_o <= #1 `TRUE;                
   1.186 -                i_cti_o <= #1 first_cycle_type;
   1.187 -                //i_lock_o <= #1 `TRUE;
   1.188 +                i_adr_o <= {first_address, 2'b00};
   1.189 +                i_cyc_o <= `TRUE;
   1.190 +                i_stb_o <= `TRUE;                
   1.191 +                i_cti_o <= first_cycle_type;
   1.192 +                //i_lock_o <= `TRUE;
   1.193  `ifdef CFG_BUS_ERRORS_ENABLED
   1.194 -                bus_error_f <= #1 `FALSE;
   1.195 +                bus_error_f <= `FALSE;
   1.196  `endif
   1.197              end
   1.198  `ifdef CFG_HW_DEBUG_ENABLED
   1.199 @@ -760,18 +760,18 @@
   1.200                  if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
   1.201                  begin
   1.202                      case (jtag_address[1:0])
   1.203 -                    2'b00: i_sel_o <= #1 4'b1000;
   1.204 -                    2'b01: i_sel_o <= #1 4'b0100;
   1.205 -                    2'b10: i_sel_o <= #1 4'b0010;
   1.206 -                    2'b11: i_sel_o <= #1 4'b0001;
   1.207 +                    2'b00: i_sel_o <= 4'b1000;
   1.208 +                    2'b01: i_sel_o <= 4'b0100;
   1.209 +                    2'b10: i_sel_o <= 4'b0010;
   1.210 +                    2'b11: i_sel_o <= 4'b0001;
   1.211                      endcase
   1.212 -                    i_adr_o <= #1 jtag_address;
   1.213 -                    i_dat_o <= #1 {4{jtag_write_data}};
   1.214 -                    i_cyc_o <= #1 `TRUE;
   1.215 -                    i_stb_o <= #1 `TRUE;
   1.216 -                    i_we_o <= #1 jtag_write_enable;
   1.217 -                    i_cti_o <= #1 `LM32_CTYPE_END;
   1.218 -                    jtag_access <= #1 `TRUE;
   1.219 +                    i_adr_o <= jtag_address;
   1.220 +                    i_dat_o <= {4{jtag_write_data}};
   1.221 +                    i_cyc_o <= `TRUE;
   1.222 +                    i_stb_o <= `TRUE;
   1.223 +                    i_we_o <= jtag_write_enable;
   1.224 +                    i_cti_o <= `LM32_CTYPE_END;
   1.225 +                    jtag_access <= `TRUE;
   1.226                  end
   1.227              end 
   1.228  `endif                    
   1.229 @@ -780,10 +780,10 @@
   1.230              // continually generated if exception handler is cached
   1.231  `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   1.232              if (branch_taken_x == `TRUE)
   1.233 -                bus_error_f <= #1 `FALSE;
   1.234 +                bus_error_f <= `FALSE;
   1.235  `endif
   1.236              if (branch_taken_m == `TRUE)
   1.237 -                bus_error_f <= #1 `FALSE;
   1.238 +                bus_error_f <= `FALSE;
   1.239  `endif
   1.240          end
   1.241      end
   1.242 @@ -793,14 +793,14 @@
   1.243  begin
   1.244      if (rst_i == `TRUE)
   1.245      begin
   1.246 -        i_cyc_o <= #1 `FALSE;
   1.247 -        i_stb_o <= #1 `FALSE;
   1.248 -        i_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.249 -        i_cti_o <= #1 `LM32_CTYPE_END;
   1.250 -        i_lock_o <= #1 `FALSE;
   1.251 -        wb_data_f <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}};
   1.252 +        i_cyc_o <= `FALSE;
   1.253 +        i_stb_o <= `FALSE;
   1.254 +        i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
   1.255 +        i_cti_o <= `LM32_CTYPE_END;
   1.256 +        i_lock_o <= `FALSE;
   1.257 +        wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
   1.258  `ifdef CFG_BUS_ERRORS_ENABLED
   1.259 -        bus_error_f <= #1 `FALSE;
   1.260 +        bus_error_f <= `FALSE;
   1.261  `endif
   1.262      end
   1.263      else
   1.264 @@ -812,15 +812,15 @@
   1.265              if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
   1.266              begin
   1.267                  // Cycle complete
   1.268 -                i_cyc_o <= #1 `FALSE;
   1.269 -                i_stb_o <= #1 `FALSE;
   1.270 +                i_cyc_o <= `FALSE;
   1.271 +                i_stb_o <= `FALSE;
   1.272                  // Register fetched instruction
   1.273 -                wb_data_f <= #1 i_dat_i;
   1.274 +                wb_data_f <= i_dat_i;
   1.275              end
   1.276  `ifdef CFG_BUS_ERRORS_ENABLED
   1.277              if (i_err_i == `TRUE)
   1.278              begin
   1.279 -                bus_error_f <= #1 `TRUE;
   1.280 +                bus_error_f <= `TRUE;
   1.281                  $display ("Instruction bus error. Address: %x", i_adr_o);
   1.282              end
   1.283  `endif
   1.284 @@ -836,13 +836,13 @@
   1.285              begin
   1.286                  // Fetch instruction
   1.287  `ifdef CFG_HW_DEBUG_ENABLED     
   1.288 -                i_sel_o <= #1 4'b1111;
   1.289 +                i_sel_o <= 4'b1111;
   1.290  `endif
   1.291 -                i_adr_o <= #1 {pc_a, 2'b00};
   1.292 -                i_cyc_o <= #1 `TRUE;
   1.293 -                i_stb_o <= #1 `TRUE;
   1.294 +                i_adr_o <= {pc_a, 2'b00};
   1.295 +                i_cyc_o <= `TRUE;
   1.296 +                i_stb_o <= `TRUE;
   1.297  `ifdef CFG_BUS_ERRORS_ENABLED
   1.298 -                bus_error_f <= #1 `FALSE;
   1.299 +                bus_error_f <= `FALSE;
   1.300  `endif
   1.301              end
   1.302  	    else
   1.303 @@ -854,7 +854,7 @@
   1.304  	           )
   1.305  		begin
   1.306  `ifdef CFG_BUS_ERRORS_ENABLED
   1.307 -		    bus_error_f <= #1 `FALSE;
   1.308 +		    bus_error_f <= `FALSE;
   1.309  `endif
   1.310  		end
   1.311  	    end
   1.312 @@ -869,18 +869,18 @@
   1.313  begin
   1.314      if (rst_i == `TRUE)
   1.315      begin
   1.316 -        instruction_d <= #1 {`LM32_INSTRUCTION_WIDTH{1'b0}};
   1.317 +        instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
   1.318  `ifdef CFG_BUS_ERRORS_ENABLED
   1.319 -        bus_error_d <= #1 `FALSE;
   1.320 +        bus_error_d <= `FALSE;
   1.321  `endif
   1.322      end
   1.323      else
   1.324      begin
   1.325          if (stall_d == `FALSE)
   1.326          begin
   1.327 -            instruction_d <= #1 instruction_f;
   1.328 +            instruction_d <= instruction_f;
   1.329  `ifdef CFG_BUS_ERRORS_ENABLED
   1.330 -            bus_error_d <= #1 bus_error_f;
   1.331 +            bus_error_d <= bus_error_f;
   1.332  `endif
   1.333          end
   1.334      end