lm32_interrupt.v

changeset 27
d6c693415d59
parent 26
73de224304c1
     1.1 --- a/lm32_interrupt.v	Sat Aug 06 00:02:46 2011 +0100
     1.2 +++ b/lm32_interrupt.v	Sat Aug 06 01:26:56 2011 +0100
     1.3 @@ -220,64 +220,64 @@
     1.4  begin
     1.5      if (rst_i == `TRUE)
     1.6      begin
     1.7 -        ie <= #1 `FALSE;
     1.8 -        eie <= #1 `FALSE;
     1.9 +        ie <= `FALSE;
    1.10 +        eie <= `FALSE;
    1.11  `ifdef CFG_DEBUG_ENABLED
    1.12 -        bie <= #1 `FALSE;
    1.13 +        bie <= `FALSE;
    1.14  `endif
    1.15 -        im <= #1 {interrupts{1'b0}};
    1.16 -        ip <= #1 {interrupts{1'b0}};
    1.17 +        im <= {interrupts{1'b0}};
    1.18 +        ip <= {interrupts{1'b0}};
    1.19      end
    1.20      else
    1.21      begin
    1.22          // Set IP bit when interrupt line is asserted
    1.23 -        ip <= #1 asserted;
    1.24 +        ip <= asserted;
    1.25  `ifdef CFG_DEBUG_ENABLED
    1.26          if (non_debug_exception == `TRUE)
    1.27          begin
    1.28              // Save and then clear interrupt enable
    1.29 -            eie <= #1 ie;
    1.30 -            ie <= #1 `FALSE;
    1.31 +            eie <= ie;
    1.32 +            ie <= `FALSE;
    1.33          end
    1.34          else if (debug_exception == `TRUE)
    1.35          begin
    1.36              // Save and then clear interrupt enable
    1.37 -            bie <= #1 ie;
    1.38 -            ie <= #1 `FALSE;
    1.39 +            bie <= ie;
    1.40 +            ie <= `FALSE;
    1.41          end
    1.42  `else
    1.43          if (exception == `TRUE)
    1.44          begin
    1.45              // Save and then clear interrupt enable
    1.46 -            eie <= #1 ie;
    1.47 -            ie <= #1 `FALSE;
    1.48 +            eie <= ie;
    1.49 +            ie <= `FALSE;
    1.50          end
    1.51  `endif
    1.52          else if (stall_x == `FALSE)
    1.53          begin
    1.54              if (eret_q_x == `TRUE)
    1.55                  // Restore interrupt enable
    1.56 -                ie <= #1 eie;          
    1.57 +                ie <= eie;          
    1.58  `ifdef CFG_DEBUG_ENABLED
    1.59              else if (bret_q_x == `TRUE)
    1.60                  // Restore interrupt enable
    1.61 -                ie <= #1 bie;
    1.62 +                ie <= bie;
    1.63  `endif
    1.64              else if (csr_write_enable == `TRUE)
    1.65              begin
    1.66                  // Handle wcsr write
    1.67                  if (csr == `LM32_CSR_IE)
    1.68                  begin
    1.69 -                    ie <= #1 csr_write_data[0];
    1.70 -                    eie <= #1 csr_write_data[1];
    1.71 +                    ie <= csr_write_data[0];
    1.72 +                    eie <= csr_write_data[1];
    1.73  `ifdef CFG_DEBUG_ENABLED
    1.74 -                    bie <= #1 csr_write_data[2];
    1.75 +                    bie <= csr_write_data[2];
    1.76  `endif
    1.77                  end
    1.78                  if (csr == `LM32_CSR_IM)
    1.79 -                    im <= #1 csr_write_data[interrupts-1:0];
    1.80 +                    im <= csr_write_data[interrupts-1:0];
    1.81                  if (csr == `LM32_CSR_IP)
    1.82 -                    ip <= #1 asserted & ~csr_write_data[interrupts-1:0];
    1.83 +                    ip <= asserted & ~csr_write_data[interrupts-1:0];
    1.84              end
    1.85          end
    1.86      end
    1.87 @@ -290,61 +290,61 @@
    1.88  begin
    1.89      if (rst_i == `TRUE)
    1.90      begin
    1.91 -        ie <= #1 `FALSE;
    1.92 -        eie <= #1 `FALSE;
    1.93 +        ie <= `FALSE;
    1.94 +        eie <= `FALSE;
    1.95  `ifdef CFG_DEBUG_ENABLED
    1.96 -        bie <= #1 `FALSE;
    1.97 +        bie <= `FALSE;
    1.98  `endif
    1.99 -        ip <= #1 {interrupts{1'b0}};
   1.100 +        ip <= {interrupts{1'b0}};
   1.101      end
   1.102      else
   1.103      begin
   1.104          // Set IP bit when interrupt line is asserted
   1.105 -        ip <= #1 asserted;
   1.106 +        ip <= asserted;
   1.107  `ifdef CFG_DEBUG_ENABLED
   1.108          if (non_debug_exception == `TRUE)
   1.109          begin
   1.110              // Save and then clear interrupt enable
   1.111 -            eie <= #1 ie;
   1.112 -            ie <= #1 `FALSE;
   1.113 +            eie <= ie;
   1.114 +            ie <= `FALSE;
   1.115          end
   1.116          else if (debug_exception == `TRUE)
   1.117          begin
   1.118              // Save and then clear interrupt enable
   1.119 -            bie <= #1 ie;
   1.120 -            ie <= #1 `FALSE;
   1.121 +            bie <= ie;
   1.122 +            ie <= `FALSE;
   1.123          end
   1.124  `else
   1.125          if (exception == `TRUE)
   1.126          begin
   1.127              // Save and then clear interrupt enable
   1.128 -            eie <= #1 ie;
   1.129 -            ie <= #1 `FALSE;
   1.130 +            eie <= ie;
   1.131 +            ie <= `FALSE;
   1.132          end
   1.133  `endif
   1.134          else if (stall_x == `FALSE)
   1.135          begin
   1.136              if (eret_q_x == `TRUE)
   1.137                  // Restore interrupt enable
   1.138 -                ie <= #1 eie;          
   1.139 +                ie <= eie;          
   1.140  `ifdef CFG_DEBUG_ENABLED
   1.141              else if (bret_q_x == `TRUE)
   1.142                  // Restore interrupt enable
   1.143 -                ie <= #1 bie;
   1.144 +                ie <= bie;
   1.145  `endif
   1.146              else if (csr_write_enable == `TRUE)
   1.147              begin
   1.148                  // Handle wcsr write
   1.149                  if (csr == `LM32_CSR_IE)
   1.150                  begin
   1.151 -                    ie <= #1 csr_write_data[0];
   1.152 -                    eie <= #1 csr_write_data[1];
   1.153 +                    ie <= csr_write_data[0];
   1.154 +                    eie <= csr_write_data[1];
   1.155  `ifdef CFG_DEBUG_ENABLED
   1.156 -                    bie <= #1 csr_write_data[2];
   1.157 +                    bie <= csr_write_data[2];
   1.158  `endif
   1.159                  end
   1.160                  if (csr == `LM32_CSR_IP)
   1.161 -                    ip <= #1 asserted & ~csr_write_data[interrupts-1:0];
   1.162 +                    ip <= asserted & ~csr_write_data[interrupts-1:0];
   1.163              end
   1.164          end
   1.165      end