lm32_jtag.v

changeset 27
d6c693415d59
parent 26
73de224304c1
     1.1 --- a/lm32_jtag.v	Sat Aug 06 00:02:46 2011 +0100
     1.2 +++ b/lm32_jtag.v	Sat Aug 06 01:26:56 2011 +0100
     1.3 @@ -257,9 +257,9 @@
     1.4  always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
     1.5  begin
     1.6  if (rst_i == `TRUE)
     1.7 -  rx_toggle <= #1 1'b0;
     1.8 +  rx_toggle <= 1'b0;
     1.9  else 
    1.10 -  rx_toggle <= #1 ~rx_toggle;
    1.11 +  rx_toggle <= ~rx_toggle;
    1.12  end
    1.13  
    1.14  always @(*)
    1.15 @@ -273,15 +273,15 @@
    1.16  begin
    1.17      if (rst_i == `TRUE)
    1.18      begin
    1.19 -        rx_toggle_r <= #1 1'b0;
    1.20 -        rx_toggle_r_r <= #1 1'b0;
    1.21 -        rx_toggle_r_r_r <= #1 1'b0;
    1.22 +        rx_toggle_r <= 1'b0;
    1.23 +        rx_toggle_r_r <= 1'b0;
    1.24 +        rx_toggle_r_r_r <= 1'b0;
    1.25      end
    1.26      else
    1.27      begin
    1.28 -        rx_toggle_r <= #1 rx_toggle;
    1.29 -        rx_toggle_r_r <= #1 rx_toggle_r;
    1.30 -        rx_toggle_r_r_r <= #1 rx_toggle_r_r;
    1.31 +        rx_toggle_r <= rx_toggle;
    1.32 +        rx_toggle_r_r <= rx_toggle_r;
    1.33 +        rx_toggle_r_r_r <= rx_toggle_r_r;
    1.34      end
    1.35  end
    1.36  
    1.37 @@ -290,24 +290,24 @@
    1.38  begin
    1.39      if (rst_i == `TRUE)
    1.40      begin
    1.41 -        state <= #1 `LM32_JTAG_STATE_READ_COMMAND;
    1.42 -        command <= #1 4'b0000;
    1.43 -        jtag_reg_d <= #1 8'h00;
    1.44 +        state <= `LM32_JTAG_STATE_READ_COMMAND;
    1.45 +        command <= 4'b0000;
    1.46 +        jtag_reg_d <= 8'h00;
    1.47  `ifdef CFG_HW_DEBUG_ENABLED
    1.48 -        processing <= #1 `FALSE;
    1.49 -        jtag_csr_write_enable <= #1 `FALSE;
    1.50 -        jtag_read_enable <= #1 `FALSE;
    1.51 -        jtag_write_enable <= #1 `FALSE;
    1.52 +        processing <= `FALSE;
    1.53 +        jtag_csr_write_enable <= `FALSE;
    1.54 +        jtag_read_enable <= `FALSE;
    1.55 +        jtag_write_enable <= `FALSE;
    1.56  `endif
    1.57  `ifdef CFG_DEBUG_ENABLED
    1.58 -        jtag_break <= #1 `FALSE;
    1.59 -        jtag_reset <= #1 `FALSE;
    1.60 +        jtag_break <= `FALSE;
    1.61 +        jtag_reset <= `FALSE;
    1.62  `endif
    1.63  `ifdef CFG_JTAG_UART_ENABLED                 
    1.64 -        uart_tx_byte <= #1 8'h00;
    1.65 -        uart_tx_valid <= #1 `FALSE;
    1.66 -        uart_rx_byte <= #1 8'h00;
    1.67 -        uart_rx_valid <= #1 `FALSE;
    1.68 +        uart_tx_byte <= 8'h00;
    1.69 +        uart_tx_valid <= `FALSE;
    1.70 +        uart_rx_byte <= 8'h00;
    1.71 +        uart_rx_valid <= `FALSE;
    1.72  `endif
    1.73      end
    1.74      else
    1.75 @@ -319,13 +319,13 @@
    1.76              `LM32_CSR_JTX:
    1.77              begin
    1.78                  // Set flag indicating data is available
    1.79 -                uart_tx_byte <= #1 csr_write_data[`LM32_BYTE_0_RNG];
    1.80 -                uart_tx_valid <= #1 `TRUE;
    1.81 +                uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
    1.82 +                uart_tx_valid <= `TRUE;
    1.83              end
    1.84              `LM32_CSR_JRX:
    1.85              begin
    1.86                  // Clear flag indidicating data has been received
    1.87 -                uart_rx_valid <= #1 `FALSE;
    1.88 +                uart_rx_valid <= `FALSE;
    1.89              end
    1.90              endcase
    1.91          end
    1.92 @@ -334,8 +334,8 @@
    1.93          // When an exception has occured, clear the requests
    1.94          if (exception_q_w == `TRUE)
    1.95          begin
    1.96 -            jtag_break <= #1 `FALSE;
    1.97 -            jtag_reset <= #1 `FALSE;
    1.98 +            jtag_break <= `FALSE;
    1.99 +            jtag_reset <= `FALSE;
   1.100          end
   1.101  `endif
   1.102          case (state)
   1.103 @@ -344,7 +344,7 @@
   1.104              // Wait for rx register to toggle which indicates new data is available
   1.105              if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.106              begin
   1.107 -                command <= #1 rx_byte[7:4];                
   1.108 +                command <= rx_byte[7:4];                
   1.109                  case (rx_addr)
   1.110  `ifdef CFG_DEBUG_ENABLED
   1.111                  `LM32_DP:
   1.112 @@ -352,37 +352,37 @@
   1.113                      case (rx_byte[7:4])
   1.114  `ifdef CFG_HW_DEBUG_ENABLED
   1.115                      `LM32_DP_READ_MEMORY:
   1.116 -                        state <= #1 `LM32_JTAG_STATE_READ_BYTE_0;
   1.117 +                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
   1.118                      `LM32_DP_READ_SEQUENTIAL:
   1.119                      begin
   1.120 -                        {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1;
   1.121 -                        state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND;
   1.122 +                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
   1.123 +                        state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   1.124                      end
   1.125                      `LM32_DP_WRITE_MEMORY:
   1.126 -                        state <= #1 `LM32_JTAG_STATE_READ_BYTE_0;
   1.127 +                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
   1.128                      `LM32_DP_WRITE_SEQUENTIAL:
   1.129                      begin
   1.130 -                        {jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1;
   1.131 -                        state <= #1 5;
   1.132 +                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
   1.133 +                        state <= 5;
   1.134                      end
   1.135                      `LM32_DP_WRITE_CSR:
   1.136 -                        state <= #1 `LM32_JTAG_STATE_READ_BYTE_0;
   1.137 +                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
   1.138  `endif                    
   1.139                      `LM32_DP_BREAK:
   1.140                      begin
   1.141  `ifdef CFG_JTAG_UART_ENABLED     
   1.142 -                        uart_rx_valid <= #1 `FALSE;    
   1.143 -                        uart_tx_valid <= #1 `FALSE;         
   1.144 +                        uart_rx_valid <= `FALSE;    
   1.145 +                        uart_tx_valid <= `FALSE;         
   1.146  `endif
   1.147 -                        jtag_break <= #1 `TRUE;
   1.148 +                        jtag_break <= `TRUE;
   1.149                      end
   1.150                      `LM32_DP_RESET:
   1.151                      begin
   1.152  `ifdef CFG_JTAG_UART_ENABLED     
   1.153 -                        uart_rx_valid <= #1 `FALSE;    
   1.154 -                        uart_tx_valid <= #1 `FALSE;         
   1.155 +                        uart_rx_valid <= `FALSE;    
   1.156 +                        uart_tx_valid <= `FALSE;         
   1.157  `endif
   1.158 -                        jtag_reset <= #1 `TRUE;
   1.159 +                        jtag_reset <= `TRUE;
   1.160                      end
   1.161                      endcase                               
   1.162                  end
   1.163 @@ -390,13 +390,13 @@
   1.164  `ifdef CFG_JTAG_UART_ENABLED                 
   1.165                  `LM32_TX:
   1.166                  begin
   1.167 -                    uart_rx_byte <= #1 rx_byte;
   1.168 -                    uart_rx_valid <= #1 `TRUE;
   1.169 +                    uart_rx_byte <= rx_byte;
   1.170 +                    uart_rx_valid <= `TRUE;
   1.171                  end                    
   1.172                  `LM32_RX:
   1.173                  begin
   1.174 -                    jtag_reg_d <= #1 uart_tx_byte;
   1.175 -                    uart_tx_valid <= #1 `FALSE;
   1.176 +                    jtag_reg_d <= uart_tx_byte;
   1.177 +                    uart_tx_valid <= `FALSE;
   1.178                  end
   1.179  `endif
   1.180                  default:
   1.181 @@ -409,43 +409,43 @@
   1.182          begin
   1.183              if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.184              begin
   1.185 -                jtag_byte_0 <= #1 rx_byte;
   1.186 -                state <= #1 `LM32_JTAG_STATE_READ_BYTE_1;
   1.187 +                jtag_byte_0 <= rx_byte;
   1.188 +                state <= `LM32_JTAG_STATE_READ_BYTE_1;
   1.189              end
   1.190          end
   1.191          `LM32_JTAG_STATE_READ_BYTE_1:
   1.192          begin
   1.193              if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.194              begin
   1.195 -                jtag_byte_1 <= #1 rx_byte;
   1.196 -                state <= #1 `LM32_JTAG_STATE_READ_BYTE_2;
   1.197 +                jtag_byte_1 <= rx_byte;
   1.198 +                state <= `LM32_JTAG_STATE_READ_BYTE_2;
   1.199              end
   1.200          end
   1.201          `LM32_JTAG_STATE_READ_BYTE_2:
   1.202          begin
   1.203              if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.204              begin
   1.205 -                jtag_byte_2 <= #1 rx_byte;
   1.206 -                state <= #1 `LM32_JTAG_STATE_READ_BYTE_3;
   1.207 +                jtag_byte_2 <= rx_byte;
   1.208 +                state <= `LM32_JTAG_STATE_READ_BYTE_3;
   1.209              end
   1.210          end
   1.211          `LM32_JTAG_STATE_READ_BYTE_3:
   1.212          begin
   1.213              if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.214              begin
   1.215 -                jtag_byte_3 <= #1 rx_byte;
   1.216 +                jtag_byte_3 <= rx_byte;
   1.217                  if (command == `LM32_DP_READ_MEMORY)
   1.218 -                    state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND;
   1.219 +                    state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   1.220                  else 
   1.221 -                    state <= #1 `LM32_JTAG_STATE_READ_BYTE_4;
   1.222 +                    state <= `LM32_JTAG_STATE_READ_BYTE_4;
   1.223              end
   1.224          end
   1.225          `LM32_JTAG_STATE_READ_BYTE_4:
   1.226          begin
   1.227              if (rx_toggle_r_r != rx_toggle_r_r_r)
   1.228              begin
   1.229 -                jtag_byte_4 <= #1 rx_byte;
   1.230 -                state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND;
   1.231 +                jtag_byte_4 <= rx_byte;
   1.232 +                state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   1.233              end
   1.234          end
   1.235          `LM32_JTAG_STATE_PROCESS_COMMAND:
   1.236 @@ -454,22 +454,22 @@
   1.237              `LM32_DP_READ_MEMORY,
   1.238              `LM32_DP_READ_SEQUENTIAL:
   1.239              begin
   1.240 -                jtag_read_enable <= #1 `TRUE;
   1.241 -                processing <= #1 `TRUE;
   1.242 -                state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   1.243 +                jtag_read_enable <= `TRUE;
   1.244 +                processing <= `TRUE;
   1.245 +                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   1.246              end
   1.247              `LM32_DP_WRITE_MEMORY,
   1.248              `LM32_DP_WRITE_SEQUENTIAL:
   1.249              begin
   1.250 -                jtag_write_enable <= #1 `TRUE;
   1.251 -                processing <= #1 `TRUE;
   1.252 -                state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   1.253 +                jtag_write_enable <= `TRUE;
   1.254 +                processing <= `TRUE;
   1.255 +                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   1.256              end
   1.257              `LM32_DP_WRITE_CSR:
   1.258              begin
   1.259 -                jtag_csr_write_enable <= #1 `TRUE;
   1.260 -                processing <= #1 `TRUE;
   1.261 -                state <= #1 `LM32_JTAG_STATE_WAIT_FOR_CSR;
   1.262 +                jtag_csr_write_enable <= `TRUE;
   1.263 +                processing <= `TRUE;
   1.264 +                state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
   1.265              end
   1.266              endcase
   1.267          end
   1.268 @@ -477,18 +477,18 @@
   1.269          begin
   1.270              if (jtag_access_complete == `TRUE)
   1.271              begin          
   1.272 -                jtag_read_enable <= #1 `FALSE;
   1.273 -                jtag_reg_d <= #1 jtag_read_data;
   1.274 -                jtag_write_enable <= #1 `FALSE;  
   1.275 -                processing <= #1 `FALSE;
   1.276 -                state <= #1 `LM32_JTAG_STATE_READ_COMMAND;
   1.277 +                jtag_read_enable <= `FALSE;
   1.278 +                jtag_reg_d <= jtag_read_data;
   1.279 +                jtag_write_enable <= `FALSE;  
   1.280 +                processing <= `FALSE;
   1.281 +                state <= `LM32_JTAG_STATE_READ_COMMAND;
   1.282              end
   1.283          end    
   1.284          `LM32_JTAG_STATE_WAIT_FOR_CSR:
   1.285          begin
   1.286 -            jtag_csr_write_enable <= #1 `FALSE;
   1.287 -            processing <= #1 `FALSE;
   1.288 -            state <= #1 `LM32_JTAG_STATE_READ_COMMAND;
   1.289 +            jtag_csr_write_enable <= `FALSE;
   1.290 +            processing <= `FALSE;
   1.291 +            state <= `LM32_JTAG_STATE_READ_COMMAND;
   1.292          end    
   1.293  `endif
   1.294          endcase