lm32_load_store_unit.v

changeset 27
d6c693415d59
parent 26
73de224304c1
     1.1 --- a/lm32_load_store_unit.v	Sat Aug 06 00:02:46 2011 +0100
     1.2 +++ b/lm32_load_store_unit.v	Sat Aug 06 01:26:56 2011 +0100
     1.3 @@ -343,13 +343,13 @@
     1.4     always @(posedge clk_i `CFG_RESET_SENSITIVITY)
     1.5       if (rst_i == `TRUE)
     1.6         begin
     1.7 -	  dram_bypass_en <= #1 `FALSE;
     1.8 -	  dram_bypass_data <= #1 0;
     1.9 +	  dram_bypass_en <= `FALSE;
    1.10 +	  dram_bypass_data <= 0;
    1.11         end
    1.12       else
    1.13         begin
    1.14  	  if (stall_x == `FALSE)
    1.15 -	    dram_bypass_data <= #1 dram_store_data_m;
    1.16 +	    dram_bypass_data <= dram_store_data_m;
    1.17  	  
    1.18  	  if (   (stall_m == `FALSE) 
    1.19                && (stall_x == `FALSE)
    1.20 @@ -359,12 +359,12 @@
    1.21  		 )
    1.22  	      && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
    1.23  	     )
    1.24 -	    dram_bypass_en <= #1 `TRUE;
    1.25 +	    dram_bypass_en <= `TRUE;
    1.26  	  else
    1.27  	    if (   (dram_bypass_en == `TRUE)
    1.28  		&& (stall_x == `FALSE)
    1.29  	       )
    1.30 -	      dram_bypass_en <= #1 `FALSE;
    1.31 +	      dram_bypass_en <= `FALSE;
    1.32         end
    1.33     
    1.34     assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
    1.35 @@ -624,26 +624,26 @@
    1.36  begin
    1.37      if (rst_i == `TRUE)
    1.38      begin
    1.39 -        d_cyc_o <= #1 `FALSE;
    1.40 -        d_stb_o <= #1 `FALSE;
    1.41 -        d_dat_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
    1.42 -        d_adr_o <= #1 {`LM32_WORD_WIDTH{1'b0}};
    1.43 -        d_sel_o <= #1 {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
    1.44 -        d_we_o <= #1 `FALSE;
    1.45 -        d_cti_o <= #1 `LM32_CTYPE_END;
    1.46 -        d_lock_o <= #1 `FALSE;
    1.47 -        wb_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
    1.48 -        wb_load_complete <= #1 `FALSE;
    1.49 -        stall_wb_load <= #1 `FALSE;
    1.50 +        d_cyc_o <= `FALSE;
    1.51 +        d_stb_o <= `FALSE;
    1.52 +        d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
    1.53 +        d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
    1.54 +        d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
    1.55 +        d_we_o <= `FALSE;
    1.56 +        d_cti_o <= `LM32_CTYPE_END;
    1.57 +        d_lock_o <= `FALSE;
    1.58 +        wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
    1.59 +        wb_load_complete <= `FALSE;
    1.60 +        stall_wb_load <= `FALSE;
    1.61  `ifdef CFG_DCACHE_ENABLED                
    1.62 -        dcache_refill_ready <= #1 `FALSE;
    1.63 +        dcache_refill_ready <= `FALSE;
    1.64  `endif                
    1.65      end
    1.66      else
    1.67      begin
    1.68  `ifdef CFG_DCACHE_ENABLED 
    1.69          // Refill ready should only be asserted for a single cycle               
    1.70 -        dcache_refill_ready <= #1 `FALSE;
    1.71 +        dcache_refill_ready <= `FALSE;
    1.72  `endif                
    1.73          // Is a Wishbone cycle already in progress?
    1.74          if (d_cyc_o == `TRUE)
    1.75 @@ -655,25 +655,25 @@
    1.76                  if ((dcache_refilling == `TRUE) && (!last_word))
    1.77                  begin
    1.78                      // Fetch next word of cache line    
    1.79 -                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= #1 d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
    1.80 +                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
    1.81                  end
    1.82                  else
    1.83  `endif                
    1.84                  begin
    1.85                      // Refill/access complete
    1.86 -                    d_cyc_o <= #1 `FALSE;
    1.87 -                    d_stb_o <= #1 `FALSE;
    1.88 -                    d_lock_o <= #1 `FALSE;
    1.89 +                    d_cyc_o <= `FALSE;
    1.90 +                    d_stb_o <= `FALSE;
    1.91 +                    d_lock_o <= `FALSE;
    1.92                  end
    1.93  `ifdef CFG_DCACHE_ENABLED    
    1.94 -                d_cti_o <= #1 next_cycle_type;
    1.95 +                d_cti_o <= next_cycle_type;
    1.96                  // If we are performing a refill, indicate to cache next word of data is ready            
    1.97 -                dcache_refill_ready <= #1 dcache_refilling;
    1.98 +                dcache_refill_ready <= dcache_refilling;
    1.99  `endif
   1.100                  // Register data read from Wishbone interface
   1.101 -                wb_data_m <= #1 d_dat_i;
   1.102 +                wb_data_m <= d_dat_i;
   1.103                  // Don't set when stores complete - otherwise we'll deadlock if load in m stage
   1.104 -                wb_load_complete <= #1 !d_we_o;
   1.105 +                wb_load_complete <= !d_we_o;
   1.106              end
   1.107              // synthesis translate_off            
   1.108              if (d_err_i == `TRUE)
   1.109 @@ -686,13 +686,13 @@
   1.110              if (dcache_refill_request == `TRUE)
   1.111              begin
   1.112                  // Start cache refill
   1.113 -                d_adr_o <= #1 first_address;
   1.114 -                d_cyc_o <= #1 `TRUE;
   1.115 -                d_sel_o <= #1 {`LM32_WORD_WIDTH/8{`TRUE}};
   1.116 -                d_stb_o <= #1 `TRUE;                
   1.117 -                d_we_o <= #1 `FALSE;
   1.118 -                d_cti_o <= #1 first_cycle_type;
   1.119 -                //d_lock_o <= #1 `TRUE;
   1.120 +                d_adr_o <= first_address;
   1.121 +                d_cyc_o <= `TRUE;
   1.122 +                d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
   1.123 +                d_stb_o <= `TRUE;                
   1.124 +                d_we_o <= `FALSE;
   1.125 +                d_cti_o <= first_cycle_type;
   1.126 +                //d_lock_o <= `TRUE;
   1.127              end
   1.128              else 
   1.129  `endif            
   1.130 @@ -707,13 +707,13 @@
   1.131                      )
   1.132              begin
   1.133                  // Data cache is write through, so all stores go to memory
   1.134 -                d_dat_o <= #1 store_data_m;
   1.135 -                d_adr_o <= #1 load_store_address_m;
   1.136 -                d_cyc_o <= #1 `TRUE;
   1.137 -                d_sel_o <= #1 byte_enable_m;
   1.138 -                d_stb_o <= #1 `TRUE;
   1.139 -                d_we_o <= #1 `TRUE;
   1.140 -                d_cti_o <= #1 `LM32_CTYPE_END;
   1.141 +                d_dat_o <= store_data_m;
   1.142 +                d_adr_o <= load_store_address_m;
   1.143 +                d_cyc_o <= `TRUE;
   1.144 +                d_sel_o <= byte_enable_m;
   1.145 +                d_stb_o <= `TRUE;
   1.146 +                d_we_o <= `TRUE;
   1.147 +                d_cti_o <= `LM32_CTYPE_END;
   1.148              end        
   1.149              else if (   (load_q_m == `TRUE) 
   1.150                       && (wb_select_m == `TRUE) 
   1.151 @@ -722,24 +722,24 @@
   1.152                      )
   1.153              begin
   1.154                  // Read requested address
   1.155 -                stall_wb_load <= #1 `FALSE;
   1.156 -                d_adr_o <= #1 load_store_address_m;
   1.157 -                d_cyc_o <= #1 `TRUE;
   1.158 -                d_sel_o <= #1 byte_enable_m;
   1.159 -                d_stb_o <= #1 `TRUE;
   1.160 -                d_we_o <= #1 `FALSE;
   1.161 -                d_cti_o <= #1 `LM32_CTYPE_END;
   1.162 +                stall_wb_load <= `FALSE;
   1.163 +                d_adr_o <= load_store_address_m;
   1.164 +                d_cyc_o <= `TRUE;
   1.165 +                d_sel_o <= byte_enable_m;
   1.166 +                d_stb_o <= `TRUE;
   1.167 +                d_we_o <= `FALSE;
   1.168 +                d_cti_o <= `LM32_CTYPE_END;
   1.169              end
   1.170          end
   1.171          // Clear load/store complete flag when instruction leaves M stage
   1.172          if (stall_m == `FALSE)
   1.173 -            wb_load_complete <= #1 `FALSE;
   1.174 +            wb_load_complete <= `FALSE;
   1.175          // When a Wishbone load first enters the M stage, we need to stall it
   1.176          if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
   1.177 -            stall_wb_load <= #1 `TRUE;
   1.178 +            stall_wb_load <= `TRUE;
   1.179          // Clear stall request if load instruction is killed
   1.180          if ((kill_m == `TRUE) || (exception_m == `TRUE))
   1.181 -            stall_wb_load <= #1 `FALSE;
   1.182 +            stall_wb_load <= `FALSE;
   1.183      end
   1.184  end
   1.185  
   1.186 @@ -750,39 +750,39 @@
   1.187  begin
   1.188      if (rst_i == `TRUE)
   1.189      begin
   1.190 -        sign_extend_m <= #1 `FALSE;
   1.191 -        size_m <= #1 2'b00;
   1.192 -        byte_enable_m <= #1 `FALSE;
   1.193 -        store_data_m <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.194 +        sign_extend_m <= `FALSE;
   1.195 +        size_m <= 2'b00;
   1.196 +        byte_enable_m <= `FALSE;
   1.197 +        store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
   1.198  `ifdef CFG_DCACHE_ENABLED
   1.199 -        dcache_select_m <= #1 `FALSE;
   1.200 +        dcache_select_m <= `FALSE;
   1.201  `endif
   1.202  `ifdef CFG_DRAM_ENABLED
   1.203 -        dram_select_m <= #1 `FALSE;
   1.204 +        dram_select_m <= `FALSE;
   1.205  `endif
   1.206  `ifdef CFG_IROM_ENABLED
   1.207 -        irom_select_m <= #1 `FALSE;
   1.208 +        irom_select_m <= `FALSE;
   1.209  `endif
   1.210 -        wb_select_m <= #1 `FALSE;        
   1.211 +        wb_select_m <= `FALSE;        
   1.212      end
   1.213      else
   1.214      begin
   1.215          if (stall_m == `FALSE)
   1.216          begin
   1.217 -            sign_extend_m <= #1 sign_extend_x;
   1.218 -            size_m <= #1 size_x;
   1.219 -            byte_enable_m <= #1 byte_enable_x;    
   1.220 -            store_data_m <= #1 store_data_x;
   1.221 +            sign_extend_m <= sign_extend_x;
   1.222 +            size_m <= size_x;
   1.223 +            byte_enable_m <= byte_enable_x;    
   1.224 +            store_data_m <= store_data_x;
   1.225  `ifdef CFG_DCACHE_ENABLED
   1.226 -            dcache_select_m <= #1 dcache_select_x;
   1.227 +            dcache_select_m <= dcache_select_x;
   1.228  `endif
   1.229  `ifdef CFG_DRAM_ENABLED
   1.230 -            dram_select_m <= #1 dram_select_x;
   1.231 +            dram_select_m <= dram_select_x;
   1.232  `endif
   1.233  `ifdef CFG_IROM_ENABLED
   1.234 -            irom_select_m <= #1 irom_select_x;
   1.235 +            irom_select_m <= irom_select_x;
   1.236  `endif
   1.237 -            wb_select_m <= #1 wb_select_x;
   1.238 +            wb_select_m <= wb_select_x;
   1.239          end
   1.240      end
   1.241  end
   1.242 @@ -792,15 +792,15 @@
   1.243  begin
   1.244      if (rst_i == `TRUE)
   1.245      begin
   1.246 -        size_w <= #1 2'b00;
   1.247 -        data_w <= #1 {`LM32_WORD_WIDTH{1'b0}};
   1.248 -        sign_extend_w <= #1 `FALSE;
   1.249 +        size_w <= 2'b00;
   1.250 +        data_w <= {`LM32_WORD_WIDTH{1'b0}};
   1.251 +        sign_extend_w <= `FALSE;
   1.252      end
   1.253      else
   1.254      begin
   1.255 -        size_w <= #1 size_m;
   1.256 -        data_w <= #1 data_m;
   1.257 -        sign_extend_w <= #1 sign_extend_m;
   1.258 +        size_w <= size_m;
   1.259 +        data_w <= data_m;
   1.260 +        sign_extend_w <= sign_extend_m;
   1.261      end
   1.262  end
   1.263