lm32_monitor.v

changeset 27
d6c693415d59
parent 26
73de224304c1
     1.1 --- a/lm32_monitor.v	Sat Aug 06 00:02:46 2011 +0100
     1.2 +++ b/lm32_monitor.v	Sat Aug 06 01:26:56 2011 +0100
     1.3 @@ -144,10 +144,10 @@
     1.4  begin
     1.5      if (rst_i == `TRUE)
     1.6      begin
     1.7 -        write_enable <= #1 `FALSE;
     1.8 -        MON_ACK_O <= #1 `FALSE;
     1.9 -        MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}};
    1.10 -        state <= #1 2'b00;
    1.11 +        write_enable <= `FALSE;
    1.12 +        MON_ACK_O <= `FALSE;
    1.13 +        MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
    1.14 +        state <= 2'b00;
    1.15      end
    1.16      else
    1.17      begin
    1.18 @@ -155,33 +155,33 @@
    1.19          2'b01:
    1.20          begin
    1.21              // Output read data to Wishbone
    1.22 -            MON_ACK_O <= #1 `TRUE;
    1.23 -            MON_DAT_O <= #1 data;
    1.24 +            MON_ACK_O <= `TRUE;
    1.25 +            MON_DAT_O <= data;
    1.26              // Sub-word writes are performed using read-modify-write  
    1.27              // as the Lattice EBRs don't support byte enables
    1.28              if (MON_WE_I == `TRUE)
    1.29 -                write_enable <= #1 `TRUE;
    1.30 -            write_data[7:0] <= #1 MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
    1.31 -            write_data[15:8] <= #1 MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
    1.32 -            write_data[23:16] <= #1 MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
    1.33 -            write_data[31:24] <= #1 MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
    1.34 -            state <= #1 2'b10;
    1.35 +                write_enable <= `TRUE;
    1.36 +            write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
    1.37 +            write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
    1.38 +            write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
    1.39 +            write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
    1.40 +            state <= 2'b10;
    1.41          end
    1.42          2'b10:
    1.43          begin
    1.44              // Wishbone access occurs in this cycle
    1.45 -            write_enable <= #1 `FALSE;
    1.46 -            MON_ACK_O <= #1 `FALSE;
    1.47 -            MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}};
    1.48 -            state <= #1 2'b00;
    1.49 +            write_enable <= `FALSE;
    1.50 +            MON_ACK_O <= `FALSE;
    1.51 +            MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
    1.52 +            state <= 2'b00;
    1.53          end
    1.54          default:
    1.55          begin
    1.56 -           write_enable <= #1 `FALSE;
    1.57 -           MON_ACK_O <= #1 `FALSE;
    1.58 +           write_enable <= `FALSE;
    1.59 +           MON_ACK_O <= `FALSE;
    1.60              // Wait for a Wishbone access
    1.61              if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
    1.62 -                state <= #1 2'b01;
    1.63 +                state <= 2'b01;
    1.64          end
    1.65          endcase        
    1.66      end