1.1 --- a/lm32_ram.v Sat Aug 06 00:02:46 2011 +0100 1.2 +++ b/lm32_ram.v Sat Aug 06 01:26:56 2011 +0100 1.3 @@ -191,13 +191,13 @@ 1.4 always @(posedge read_clk) 1.5 if (reset) 1.6 begin 1.7 - raw_data <= #1 0; 1.8 - raw <= #1 1'b0; 1.9 + raw_data <= 0; 1.10 + raw <= 1'b0; 1.11 end 1.12 else 1.13 begin 1.14 - raw_data <= #1 raw_data_nxt; 1.15 - raw <= #1 raw_nxt; 1.16 + raw_data <= raw_data_nxt; 1.17 + raw <= raw_nxt; 1.18 end 1.19 1.20 pmi_ram_dp_true 1.21 @@ -273,7 +273,7 @@ 1.22 1.23 always @(posedge read_clk) 1.24 if (enable_read) 1.25 - ra <= #1 read_address; 1.26 + ra <= read_address; 1.27 end 1.28 1.29 else 1.30 @@ -296,12 +296,12 @@ 1.31 // Write port 1.32 always @(posedge write_clk) 1.33 if ((write_enable == `TRUE) && (enable_write == `TRUE)) 1.34 - mem[write_address] <= #1 write_data; 1.35 + mem[write_address] <= write_data; 1.36 1.37 // Register read address for use on next cycle 1.38 always @(posedge read_clk) 1.39 if (enable_read) 1.40 - ra <= #1 read_address; 1.41 + ra <= read_address; 1.42 1.43 end 1.44