lm32_cpu.v

Fri, 13 Aug 2010 01:13:04 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Fri, 13 Aug 2010 01:13:04 +0100
changeset 8
07be9df9fee8
parent 0
cd0b58aa6f83
child 12
e8125a6a3bd8
child 22
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permissions
-rwxr-xr-x

[UPSTREAM PULL] update baseline to LatticeMico32 v3.5 and add documentation

Update baseline head to LatticeMico32 v3.5, from "LatticeMico32 System for
ispLEVER on Linux" v8.1 (Jun 2010). Downloaded from:
http://www.latticesemi.com/dynamic/index.cfm?fuseaction=view_documents&document_type=65&sloc=01-01-08-11-48&source=sidebar

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : lm32_cpu.v
    19 // Title            : Top-level of CPU.
    20 // Dependencies     : lm32_include.v
    21 //
    22 // Version 3.4
    23 // 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 
    24 //    never serviced.
    25 //    
    26 // Version 3.3
    27 // 1. Feature: Support for memory that is tightly coupled to processor core, and 
    28 //    has a single-cycle access latency (same as caches). Instruction port has
    29 //    access to a dedicated physically-mapped memory. Data port has access to
    30 //    a dedicated physically-mapped memory. In order to be able to manipulate
    31 //    values in both these memories via the debugger, these memories also
    32 //    interface with the data port of LM32.
    33 // 2. Feature: Extended Configuration Register
    34 // 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
    35 //    Verilog.
    36 //
    37 // Version 3.2
    38 // 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
    39 //    hang. At the same time CPU fails to register data bus error exception. Bug
    40 //    is caused because (a) data bus error exception occurs after load/store has
    41 //    passed X stage and next sequential instruction (e.g., brk) is already in X
    42 //    stage, and (b) data bus error exception had lower priority than, say, brk
    43 //    exception.
    44 // 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
    45 //    invalid location, CPU will fail to register data bus error exception. The
    46 //    solution is to stall scall/eret/bret/brk instructions in D pipeline stage
    47 //    until load/store has completed.
    48 // 3. Feature: Enable precise identification of load/store that causes seg fault.
    49 // 4. SYNC resets used for register file when implemented in EBRs.
    50 //
    51 // Version 3.1
    52 // 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
    53 //    instead of distributed memory by enabling the option in LM32 GUI. 
    54 // 2. Feature: LM32 also adds a static branch predictor to improve branch 
    55 //    performance. All immediate-based forward-pointing branches are predicted 
    56 //    not-taken. All immediate-based backward-pointing branches are predicted taken.
    57 // 
    58 // Version 7.0SP2, 3.0
    59 // No Change
    60 //
    61 // Version 6.1.17
    62 // Initial Release
    63 // =============================================================================
    65 `include "lm32_include.v"
    67 /////////////////////////////////////////////////////
    68 // Module interface
    69 /////////////////////////////////////////////////////
    71 module lm32_cpu (
    72     // ----- Inputs -------
    73     clk_i,
    74 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
    75     clk_n_i,
    76 `endif    
    77     rst_i,
    78     // From external devices
    79 `ifdef CFG_INTERRUPTS_ENABLED
    80     interrupt_n,
    81 `endif
    82     // From user logic
    83 `ifdef CFG_USER_ENABLED
    84     user_result,
    85     user_complete,
    86 `endif     
    87 `ifdef CFG_JTAG_ENABLED
    88     // From JTAG
    89     jtag_clk,
    90     jtag_update, 
    91     jtag_reg_q,
    92     jtag_reg_addr_q,
    93 `endif
    94 `ifdef CFG_IWB_ENABLED
    95     // Instruction Wishbone master
    96     I_DAT_I,
    97     I_ACK_I,
    98     I_ERR_I,
    99     I_RTY_I,
   100 `endif
   101     // Data Wishbone master
   102     D_DAT_I,
   103     D_ACK_I,
   104     D_ERR_I,
   105     D_RTY_I,
   106     // ----- Outputs -------
   107 `ifdef CFG_TRACE_ENABLED
   108     trace_pc,
   109     trace_pc_valid,
   110     trace_exception,
   111     trace_eid,
   112     trace_eret,
   113 `ifdef CFG_DEBUG_ENABLED
   114     trace_bret,
   115 `endif
   116 `endif
   117 `ifdef CFG_JTAG_ENABLED
   118     jtag_reg_d,
   119     jtag_reg_addr_d,
   120 `endif
   121 `ifdef CFG_USER_ENABLED    
   122     user_valid,
   123     user_opcode,
   124     user_operand_0,
   125     user_operand_1,
   126 `endif    
   127 `ifdef CFG_IWB_ENABLED
   128     // Instruction Wishbone master
   129     I_DAT_O,
   130     I_ADR_O,
   131     I_CYC_O,
   132     I_SEL_O,
   133     I_STB_O,
   134     I_WE_O,
   135     I_CTI_O,
   136     I_LOCK_O,
   137     I_BTE_O,
   138 `endif
   139     // Data Wishbone master
   140     D_DAT_O,
   141     D_ADR_O,
   142     D_CYC_O,
   143     D_SEL_O,
   144     D_STB_O,
   145     D_WE_O,
   146     D_CTI_O,
   147     D_LOCK_O,
   148     D_BTE_O
   149     );
   151 /////////////////////////////////////////////////////
   152 // Parameters
   153 /////////////////////////////////////////////////////
   155 parameter eba_reset = `CFG_EBA_RESET;                           // Reset value for EBA CSR
   156 `ifdef CFG_DEBUG_ENABLED
   157 parameter deba_reset = `CFG_DEBA_RESET;                         // Reset value for DEBA CSR
   158 `endif
   160 `ifdef CFG_ICACHE_ENABLED
   161 parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
   162 parameter icache_sets = `CFG_ICACHE_SETS;                       // Number of sets
   163 parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE;   // Number of bytes per cache line
   164 parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS;       // Base address of cachable memory
   165 parameter icache_limit = `CFG_ICACHE_LIMIT;                     // Limit (highest address) of cachable memory
   166 `else
   167 parameter icache_associativity = 1;    
   168 parameter icache_sets = 512;                      
   169 parameter icache_bytes_per_line = 16;  
   170 parameter icache_base_address = 0;      
   171 parameter icache_limit = 0;                    
   172 `endif
   174 `ifdef CFG_DCACHE_ENABLED
   175 parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
   176 parameter dcache_sets = `CFG_DCACHE_SETS;                       // Number of sets
   177 parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE;   // Number of bytes per cache line
   178 parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS;       // Base address of cachable memory
   179 parameter dcache_limit = `CFG_DCACHE_LIMIT;                     // Limit (highest address) of cachable memory
   180 `else
   181 parameter dcache_associativity = 1;    
   182 parameter dcache_sets = 512;                      
   183 parameter dcache_bytes_per_line = 16;  
   184 parameter dcache_base_address = 0;      
   185 parameter dcache_limit = 0;                    
   186 `endif
   188 `ifdef CFG_DEBUG_ENABLED
   189 parameter watchpoints = `CFG_WATCHPOINTS;                       // Number of h/w watchpoint CSRs
   190 `else
   191 parameter watchpoints = 0;
   192 `endif
   193 `ifdef CFG_ROM_DEBUG_ENABLED
   194 parameter breakpoints = `CFG_BREAKPOINTS;                       // Number of h/w breakpoint CSRs
   195 `else
   196 parameter breakpoints = 0;
   197 `endif
   199 `ifdef CFG_INTERRUPTS_ENABLED
   200 parameter interrupts = `CFG_INTERRUPTS;                         // Number of interrupts
   201 `else
   202 parameter interrupts = 0;
   203 `endif
   205 /////////////////////////////////////////////////////
   206 // Inputs
   207 /////////////////////////////////////////////////////
   209 input clk_i;                                    // Clock
   210 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
   211 input clk_n_i;                                  // Inverted clock
   212 `endif    
   213 input rst_i;                                    // Reset
   215 `ifdef CFG_INTERRUPTS_ENABLED
   216 input [`LM32_INTERRUPT_RNG] interrupt_n;        // Interrupt pins, active-low
   217 `endif
   219 `ifdef CFG_USER_ENABLED
   220 input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
   221 input user_complete;                            // User-defined instruction execution is complete
   222 `endif    
   224 `ifdef CFG_JTAG_ENABLED
   225 input jtag_clk;                                 // JTAG clock
   226 input jtag_update;                              // JTAG state machine is in data register update state
   227 input [`LM32_BYTE_RNG] jtag_reg_q;              
   228 input [2:0] jtag_reg_addr_q;
   229 `endif
   231 `ifdef CFG_IWB_ENABLED
   232 input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
   233 input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
   234 input I_ERR_I;                                  // Instruction Wishbone interface error
   235 input I_RTY_I;                                  // Instruction Wishbone interface retry
   236 `endif
   238 input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
   239 input D_ACK_I;                                  // Data Wishbone interface acknowledgement
   240 input D_ERR_I;                                  // Data Wishbone interface error
   241 input D_RTY_I;                                  // Data Wishbone interface retry
   243 /////////////////////////////////////////////////////
   244 // Outputs
   245 /////////////////////////////////////////////////////
   247 `ifdef CFG_TRACE_ENABLED
   248 output [`LM32_PC_RNG] trace_pc;                 // PC to trace
   249 reg    [`LM32_PC_RNG] trace_pc;
   250 output trace_pc_valid;                          // Indicates that a new trace PC is valid
   251 reg    trace_pc_valid;
   252 output trace_exception;                         // Indicates an exception has occured
   253 reg    trace_exception;
   254 output [`LM32_EID_RNG] trace_eid;               // Indicates what type of exception has occured
   255 reg    [`LM32_EID_RNG] trace_eid;
   256 output trace_eret;                              // Indicates an eret instruction has been executed
   257 reg    trace_eret;
   258 `ifdef CFG_DEBUG_ENABLED
   259 output trace_bret;                              // Indicates a bret instruction has been executed
   260 reg    trace_bret;
   261 `endif
   262 `endif
   264 `ifdef CFG_JTAG_ENABLED
   265 output [`LM32_BYTE_RNG] jtag_reg_d;
   266 wire   [`LM32_BYTE_RNG] jtag_reg_d;
   267 output [2:0] jtag_reg_addr_d;
   268 wire   [2:0] jtag_reg_addr_d;
   269 `endif
   271 `ifdef CFG_USER_ENABLED
   272 output user_valid;                              // Indicates if user_opcode is valid
   273 wire   user_valid;
   274 output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
   275 reg    [`LM32_USER_OPCODE_RNG] user_opcode;
   276 output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
   277 wire   [`LM32_WORD_RNG] user_operand_0;
   278 output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
   279 wire   [`LM32_WORD_RNG] user_operand_1;
   280 `endif
   282 `ifdef CFG_IWB_ENABLED
   283 output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
   284 wire   [`LM32_WORD_RNG] I_DAT_O;
   285 output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
   286 wire   [`LM32_WORD_RNG] I_ADR_O;
   287 output I_CYC_O;                                 // Instruction Wishbone interface cycle
   288 wire   I_CYC_O;
   289 output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
   290 wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
   291 output I_STB_O;                                 // Instruction Wishbone interface strobe
   292 wire   I_STB_O;
   293 output I_WE_O;                                  // Instruction Wishbone interface write enable
   294 wire   I_WE_O;
   295 output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type 
   296 wire   [`LM32_CTYPE_RNG] I_CTI_O;
   297 output I_LOCK_O;                                // Instruction Wishbone interface lock bus
   298 wire   I_LOCK_O;
   299 output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type 
   300 wire   [`LM32_BTYPE_RNG] I_BTE_O;
   301 `endif
   303 output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
   304 wire   [`LM32_WORD_RNG] D_DAT_O;
   305 output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
   306 wire   [`LM32_WORD_RNG] D_ADR_O;
   307 output D_CYC_O;                                 // Data Wishbone interface cycle
   308 wire   D_CYC_O;
   309 output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
   310 wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
   311 output D_STB_O;                                 // Data Wishbone interface strobe
   312 wire   D_STB_O;
   313 output D_WE_O;                                  // Data Wishbone interface write enable
   314 wire   D_WE_O;
   315 output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type 
   316 wire   [`LM32_CTYPE_RNG] D_CTI_O;
   317 output D_LOCK_O;                                // Date Wishbone interface lock bus
   318 wire   D_LOCK_O;
   319 output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
   320 wire   [`LM32_BTYPE_RNG] D_BTE_O;
   322 /////////////////////////////////////////////////////
   323 // Internal nets and registers 
   324 /////////////////////////////////////////////////////
   326 // Pipeline registers
   328 `ifdef LM32_CACHE_ENABLED
   329 reg valid_a;                                    // Instruction in A stage is valid
   330 `endif
   331 reg valid_f;                                    // Instruction in F stage is valid
   332 reg valid_d;                                    // Instruction in D stage is valid
   333 reg valid_x;                                    // Instruction in X stage is valid
   334 reg valid_m;                                    // Instruction in M stage is valid
   335 reg valid_w;                                    // Instruction in W stage is valid
   337 wire q_x;
   338 wire [`LM32_WORD_RNG] immediate_d;              // Immediate operand
   339 wire load_d;                                    // Indicates a load instruction
   340 reg load_x;                                     
   341 reg load_m;
   342 wire load_q_x;
   343 wire store_q_x;
   344 wire store_d;                                   // Indicates a store instruction
   345 reg store_x;
   346 reg store_m;
   347 wire [`LM32_SIZE_RNG] size_d;                   // Size of load/store (byte, hword, word)
   348 reg [`LM32_SIZE_RNG] size_x;
   349 wire branch_d;                                  // Indicates a branch instruction
   350 wire branch_predict_d;                          // Indicates a branch is predicted
   351 wire branch_predict_taken_d;                    // Indicates a branch is predicted taken
   352 wire [`LM32_PC_RNG] branch_predict_address_d;   // Address to which predicted branch jumps
   353 wire [`LM32_PC_RNG] branch_target_d;
   354 wire bi_unconditional;
   355 wire bi_conditional;
   356 reg branch_x;                                   
   357 reg branch_predict_x;
   358 reg branch_predict_taken_x;
   359 reg branch_m;
   360 reg branch_predict_m;
   361 reg branch_predict_taken_m;
   362 wire branch_mispredict_taken_m;                 // Indicates a branch was mispredicted as taken
   363 wire branch_flushX_m;                           // Indicates that instruction in X stage must be squashed
   364 wire branch_reg_d;                              // Branch to register or immediate
   365 wire [`LM32_PC_RNG] branch_offset_d;            // Branch offset for immediate branches
   366 reg [`LM32_PC_RNG] branch_target_x;             // Address to branch to
   367 reg [`LM32_PC_RNG] branch_target_m;
   368 wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
   369 wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
   371 wire x_result_sel_csr_d;                        // Select X stage result from CSRs
   372 reg x_result_sel_csr_x;
   373 `ifdef LM32_MC_ARITHMETIC_ENABLED
   374 wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
   375 reg x_result_sel_mc_arith_x;
   376 `endif
   377 `ifdef LM32_NO_BARREL_SHIFT    
   378 wire x_result_sel_shift_d;                      // Select X stage result from shifter
   379 reg x_result_sel_shift_x;
   380 `endif
   381 `ifdef CFG_SIGN_EXTEND_ENABLED
   382 wire x_result_sel_sext_d;                       // Select X stage result from sign-extend logic
   383 reg x_result_sel_sext_x;
   384 `endif
   385 wire x_result_sel_logic_d;                      // Select X stage result from logic op unit
   386 reg x_result_sel_logic_x;
   387 `ifdef CFG_USER_ENABLED
   388 wire x_result_sel_user_d;                       // Select X stage result from user-defined logic
   389 reg x_result_sel_user_x;
   390 `endif
   391 wire x_result_sel_add_d;                        // Select X stage result from adder
   392 reg x_result_sel_add_x;
   393 wire m_result_sel_compare_d;                    // Select M stage result from comparison logic
   394 reg m_result_sel_compare_x;
   395 reg m_result_sel_compare_m;
   396 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   397 wire m_result_sel_shift_d;                      // Select M stage result from shifter
   398 reg m_result_sel_shift_x;
   399 reg m_result_sel_shift_m;
   400 `endif
   401 wire w_result_sel_load_d;                       // Select W stage result from load/store unit
   402 reg w_result_sel_load_x;
   403 reg w_result_sel_load_m;
   404 reg w_result_sel_load_w;
   405 `ifdef CFG_PL_MULTIPLY_ENABLED
   406 wire w_result_sel_mul_d;                        // Select W stage result from multiplier
   407 reg w_result_sel_mul_x;
   408 reg w_result_sel_mul_m;
   409 reg w_result_sel_mul_w;
   410 `endif
   411 wire x_bypass_enable_d;                         // Whether result is bypassable in X stage
   412 reg x_bypass_enable_x;                          
   413 wire m_bypass_enable_d;                         // Whether result is bypassable in M stage
   414 reg m_bypass_enable_x;                          
   415 reg m_bypass_enable_m;
   416 wire sign_extend_d;                             // Whether to sign-extend or zero-extend
   417 reg sign_extend_x;
   418 wire write_enable_d;                            // Register file write enable
   419 reg write_enable_x;
   420 wire write_enable_q_x;
   421 reg write_enable_m;
   422 wire write_enable_q_m;
   423 reg write_enable_w;
   424 wire write_enable_q_w;
   425 wire read_enable_0_d;                           // Register file read enable 0
   426 wire [`LM32_REG_IDX_RNG] read_idx_0_d;          // Register file read index 0
   427 wire read_enable_1_d;                           // Register file read enable 1
   428 wire [`LM32_REG_IDX_RNG] read_idx_1_d;          // Register file read index 1
   429 wire [`LM32_REG_IDX_RNG] write_idx_d;           // Register file write index
   430 reg [`LM32_REG_IDX_RNG] write_idx_x;            
   431 reg [`LM32_REG_IDX_RNG] write_idx_m;
   432 reg [`LM32_REG_IDX_RNG] write_idx_w;
   433 wire [`LM32_CSR_RNG] csr_d;                     // CSR read/write index
   434 reg  [`LM32_CSR_RNG] csr_x;                  
   435 wire [`LM32_CONDITION_RNG] condition_d;         // Branch condition
   436 reg [`LM32_CONDITION_RNG] condition_x;          
   437 `ifdef CFG_DEBUG_ENABLED
   438 wire break_d;                                   // Indicates a break instruction
   439 reg break_x;                                    
   440 `endif
   441 wire scall_d;                                   // Indicates a scall instruction
   442 reg scall_x;    
   443 wire eret_d;                                    // Indicates an eret instruction
   444 reg eret_x;
   445 wire eret_q_x;
   446 reg eret_m;
   447 `ifdef CFG_TRACE_ENABLED
   448 reg eret_w;
   449 `endif
   450 `ifdef CFG_DEBUG_ENABLED
   451 wire bret_d;                                    // Indicates a bret instruction
   452 reg bret_x;
   453 wire bret_q_x;
   454 reg bret_m;
   455 `ifdef CFG_TRACE_ENABLED
   456 reg bret_w;
   457 `endif
   458 `endif
   459 wire csr_write_enable_d;                        // CSR write enable
   460 reg csr_write_enable_x;
   461 wire csr_write_enable_q_x;
   462 `ifdef CFG_USER_ENABLED
   463 wire [`LM32_USER_OPCODE_RNG] user_opcode_d;     // User-defined instruction opcode
   464 `endif
   466 `ifdef CFG_BUS_ERRORS_ENABLED
   467 wire bus_error_d;                               // Indicates an bus error occured while fetching the instruction in this pipeline stage
   468 reg bus_error_x;
   469 reg data_bus_error_exception_m;
   470 reg [`LM32_PC_RNG] memop_pc_w;
   471 `endif
   473 reg [`LM32_WORD_RNG] d_result_0;                // Result of instruction in D stage (operand 0)
   474 reg [`LM32_WORD_RNG] d_result_1;                // Result of instruction in D stage (operand 1)
   475 reg [`LM32_WORD_RNG] x_result;                  // Result of instruction in X stage
   476 reg [`LM32_WORD_RNG] m_result;                  // Result of instruction in M stage
   477 reg [`LM32_WORD_RNG] w_result;                  // Result of instruction in W stage
   479 reg [`LM32_WORD_RNG] operand_0_x;               // Operand 0 for X stage instruction
   480 reg [`LM32_WORD_RNG] operand_1_x;               // Operand 1 for X stage instruction
   481 reg [`LM32_WORD_RNG] store_operand_x;           // Data read from register to store
   482 reg [`LM32_WORD_RNG] operand_m;                 // Operand for M stage instruction
   483 reg [`LM32_WORD_RNG] operand_w;                 // Operand for W stage instruction
   485 // To/from register file
   486 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   487 reg [`LM32_WORD_RNG] reg_data_live_0;          
   488 reg [`LM32_WORD_RNG] reg_data_live_1;  
   489 reg use_buf;                                    // Whether to use reg_data_live or reg_data_buf
   490 reg [`LM32_WORD_RNG] reg_data_buf_0;
   491 reg [`LM32_WORD_RNG] reg_data_buf_1;
   492 `endif
   493 `ifdef LM32_EBR_REGISTER_FILE
   494 `else
   495 reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1];   // Register file
   496 `endif
   497 wire [`LM32_WORD_RNG] reg_data_0;               // Register file read port 0 data         
   498 wire [`LM32_WORD_RNG] reg_data_1;               // Register file read port 1 data
   499 reg [`LM32_WORD_RNG] bypass_data_0;             // Register value 0 after bypassing
   500 reg [`LM32_WORD_RNG] bypass_data_1;             // Register value 1 after bypassing
   501 wire reg_write_enable_q_w;
   503 reg interlock;                                  // Indicates pipeline should be stalled because of a read-after-write hazzard
   505 wire stall_a;                                   // Stall instruction in A pipeline stage
   506 wire stall_f;                                   // Stall instruction in F pipeline stage
   507 wire stall_d;                                   // Stall instruction in D pipeline stage
   508 wire stall_x;                                   // Stall instruction in X pipeline stage
   509 wire stall_m;                                   // Stall instruction in M pipeline stage
   511 // To/from adder
   512 wire adder_op_d;                                // Whether to add or subtract
   513 reg adder_op_x;                                 
   514 reg adder_op_x_n;                               // Inverted version of adder_op_x
   515 wire [`LM32_WORD_RNG] adder_result_x;           // Result from adder
   516 wire adder_overflow_x;                          // Whether a signed overflow occured
   517 wire adder_carry_n_x;                           // Whether a carry was generated
   519 // To/from logical operations unit
   520 wire [`LM32_LOGIC_OP_RNG] logic_op_d;           // Which operation to perform
   521 reg [`LM32_LOGIC_OP_RNG] logic_op_x;            
   522 wire [`LM32_WORD_RNG] logic_result_x;           // Result of logical operation
   524 `ifdef CFG_SIGN_EXTEND_ENABLED
   525 // From sign-extension unit
   526 wire [`LM32_WORD_RNG] sextb_result_x;           // Result of byte sign-extension
   527 wire [`LM32_WORD_RNG] sexth_result_x;           // Result of half-word sign-extenstion
   528 wire [`LM32_WORD_RNG] sext_result_x;            // Result of sign-extension specified by instruction
   529 `endif
   531 // To/from shifter
   532 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   533 `ifdef CFG_ROTATE_ENABLED
   534 wire rotate_d;                                  // Whether we should rotate or shift
   535 reg rotate_x;                                    
   536 `endif
   537 wire direction_d;                               // Which direction to shift in
   538 reg direction_x;                                        
   539 wire [`LM32_WORD_RNG] shifter_result_m;         // Result of shifter
   540 `endif
   541 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   542 wire shift_left_d;                              // Indicates whether to perform a left shift or not
   543 wire shift_left_q_d;
   544 wire shift_right_d;                             // Indicates whether to perform a right shift or not
   545 wire shift_right_q_d;
   546 `endif
   547 `ifdef LM32_NO_BARREL_SHIFT
   548 wire [`LM32_WORD_RNG] shifter_result_x;         // Result of single-bit right shifter
   549 `endif
   551 // To/from multiplier
   552 `ifdef LM32_MULTIPLY_ENABLED
   553 wire [`LM32_WORD_RNG] multiplier_result_w;      // Result from multiplier
   554 `endif
   555 `ifdef CFG_MC_MULTIPLY_ENABLED
   556 wire multiply_d;                                // Indicates whether to perform a multiply or not
   557 wire multiply_q_d;
   558 `endif
   560 // To/from divider
   561 `ifdef CFG_MC_DIVIDE_ENABLED
   562 wire divide_d;                                  // Indicates whether to perform a divider or not
   563 wire divide_q_d;
   564 wire modulus_d;
   565 wire modulus_q_d;
   566 wire divide_by_zero_x;                          // Indicates an attempt was made to divide by zero
   567 `endif
   569 // To from multi-cycle arithmetic unit
   570 `ifdef LM32_MC_ARITHMETIC_ENABLED
   571 wire mc_stall_request_x;                        // Multi-cycle arithmetic unit stall request
   572 wire [`LM32_WORD_RNG] mc_result_x;
   573 `endif
   575 // From CSRs
   576 `ifdef CFG_INTERRUPTS_ENABLED
   577 wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
   578 `endif
   579 wire [`LM32_WORD_RNG] cfg;                      // Configuration CSR
   580 wire [`LM32_WORD_RNG] cfg2;                     // Extended Configuration CSR
   581 `ifdef CFG_CYCLE_COUNTER_ENABLED
   582 reg [`LM32_WORD_RNG] cc;                        // Cycle counter CSR
   583 `endif
   584 reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
   586 // To/from instruction unit
   587 wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
   588 wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
   589 wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
   590 wire [`LM32_PC_RNG] pc_m;                       // PC of instruction in M stage
   591 wire [`LM32_PC_RNG] pc_w;                       // PC of instruction in W stage
   592 `ifdef CFG_TRACE_ENABLED
   593 reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
   594 `endif
   595 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   596 wire [`LM32_INSTRUCTION_RNG] instruction_f;     // Instruction in F stage
   597 `endif
   598 //pragma attribute instruction_d preserve_signal true
   599 //pragma attribute instruction_d preserve_driver true
   600 wire [`LM32_INSTRUCTION_RNG] instruction_d;     // Instruction in D stage
   601 `ifdef CFG_ICACHE_ENABLED
   602 wire iflush;                                    // Flush instruction cache
   603 wire icache_stall_request;                      // Stall pipeline because instruction cache is busy
   604 wire icache_restart_request;                    // Restart instruction that caused an instruction cache miss
   605 wire icache_refill_request;                     // Request to refill instruction cache
   606 wire icache_refilling;                          // Indicates the instruction cache is being refilled
   607 `endif
   608 `ifdef CFG_IROM_ENABLED
   609 wire [`LM32_WORD_RNG] irom_store_data_m;        // Store data to instruction ROM
   610 wire [`LM32_WORD_RNG] irom_address_xm;          // Address to instruction ROM from load-store unit
   611 wire [`LM32_WORD_RNG] irom_data_m;              // Load data from instruction ROM
   612 wire irom_we_xm;                                // Indicates data needs to be written to instruction ROM
   613 wire irom_stall_request_x;                      // Indicates D stage needs to be stalled on a store to instruction ROM
   614 `endif
   616 // To/from load/store unit
   617 `ifdef CFG_DCACHE_ENABLED
   618 wire dflush_x;                                  // Flush data cache    
   619 reg dflush_m;                                    
   620 wire dcache_stall_request;                      // Stall pipeline because data cache is busy
   621 wire dcache_restart_request;                    // Restart instruction that caused a data cache miss
   622 wire dcache_refill_request;                     // Request to refill data cache
   623 wire dcache_refilling;                          // Indicates the data cache is being refilled
   624 `endif
   625 wire [`LM32_WORD_RNG] load_data_w;              // Result of a load instruction
   626 wire stall_wb_load;                             // Stall pipeline because of a load via the data Wishbone interface
   628 // To/from JTAG interface
   629 `ifdef CFG_JTAG_ENABLED
   630 `ifdef CFG_JTAG_UART_ENABLED
   631 wire [`LM32_WORD_RNG] jtx_csr_read_data;        // Read data for JTX CSR
   632 wire [`LM32_WORD_RNG] jrx_csr_read_data;        // Read data for JRX CSR
   633 `endif
   634 `ifdef CFG_HW_DEBUG_ENABLED
   635 wire jtag_csr_write_enable;                     // Debugger CSR write enable
   636 wire [`LM32_WORD_RNG] jtag_csr_write_data;      // Data to write to specified CSR
   637 wire [`LM32_CSR_RNG] jtag_csr;                  // Which CSR to write
   638 wire jtag_read_enable;                          
   639 wire [`LM32_BYTE_RNG] jtag_read_data;
   640 wire jtag_write_enable;
   641 wire [`LM32_BYTE_RNG] jtag_write_data;
   642 wire [`LM32_WORD_RNG] jtag_address;
   643 wire jtag_access_complete;
   644 `endif
   645 `ifdef CFG_DEBUG_ENABLED
   646 wire jtag_break;                                // Request from debugger to raise a breakpoint
   647 `endif
   648 `endif
   650 // Hazzard detection
   651 wire raw_x_0;                                   // RAW hazzard between instruction in X stage and read port 0
   652 wire raw_x_1;                                   // RAW hazzard between instruction in X stage and read port 1
   653 wire raw_m_0;                                   // RAW hazzard between instruction in M stage and read port 0
   654 wire raw_m_1;                                   // RAW hazzard between instruction in M stage and read port 1
   655 wire raw_w_0;                                   // RAW hazzard between instruction in W stage and read port 0
   656 wire raw_w_1;                                   // RAW hazzard between instruction in W stage and read port 1
   658 // Control flow
   659 wire cmp_zero;                                  // Result of comparison is zero
   660 wire cmp_negative;                              // Result of comparison is negative
   661 wire cmp_overflow;                              // Comparison produced an overflow
   662 wire cmp_carry_n;                               // Comparison produced a carry, inverted
   663 reg condition_met_x;                            // Condition of branch instruction is met
   664 reg condition_met_m;
   665 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   666 wire branch_taken_x;                            // Branch is taken in X stage
   667 `endif
   668 wire branch_taken_m;                            // Branch is taken in M stage
   670 wire kill_f;                                    // Kill instruction in F stage
   671 wire kill_d;                                    // Kill instruction in D stage
   672 wire kill_x;                                    // Kill instruction in X stage
   673 wire kill_m;                                    // Kill instruction in M stage
   674 wire kill_w;                                    // Kill instruction in W stage
   676 reg [`LM32_PC_WIDTH+2-1:8] eba;                 // Exception Base Address (EBA) CSR
   677 `ifdef CFG_DEBUG_ENABLED
   678 reg [`LM32_PC_WIDTH+2-1:8] deba;                // Debug Exception Base Address (DEBA) CSR
   679 `endif
   680 reg [`LM32_EID_RNG] eid_x;                      // Exception ID in X stage
   681 `ifdef CFG_TRACE_ENABLED
   682 reg [`LM32_EID_RNG] eid_m;                      // Exception ID in M stage
   683 reg [`LM32_EID_RNG] eid_w;                      // Exception ID in W stage
   684 `endif
   686 `ifdef CFG_DEBUG_ENABLED
   687 `ifdef LM32_SINGLE_STEP_ENABLED
   688 wire dc_ss;                                     // Is single-step enabled
   689 `endif
   690 wire dc_re;                                     // Remap all exceptions
   691 wire exception_x;                               // An exception occured in the X stage
   692 reg exception_m;                                // An instruction that caused an exception is in the M stage
   693 wire debug_exception_x;                         // Indicates if a debug exception has occured
   694 reg debug_exception_m;
   695 reg debug_exception_w;
   696 wire debug_exception_q_w;
   697 wire non_debug_exception_x;                     // Indicates if a non debug exception has occured
   698 reg non_debug_exception_m;
   699 reg non_debug_exception_w;
   700 wire non_debug_exception_q_w;
   701 `else
   702 wire exception_x;                               // Indicates if a debug exception has occured
   703 reg exception_m;
   704 reg exception_w;
   705 wire exception_q_w;
   706 `endif
   708 `ifdef CFG_DEBUG_ENABLED
   709 `ifdef CFG_JTAG_ENABLED
   710 wire reset_exception;                           // Indicates if a reset exception has occured
   711 `endif
   712 `endif
   713 `ifdef CFG_INTERRUPTS_ENABLED
   714 wire interrupt_exception;                       // Indicates if an interrupt exception has occured
   715 `endif
   716 `ifdef CFG_DEBUG_ENABLED
   717 wire breakpoint_exception;                      // Indicates if a breakpoint exception has occured
   718 wire watchpoint_exception;                      // Indicates if a watchpoint exception has occured
   719 `endif
   720 `ifdef CFG_BUS_ERRORS_ENABLED
   721 wire instruction_bus_error_exception;           // Indicates if an instruction bus error exception has occured
   722 wire data_bus_error_exception;                  // Indicates if a data bus error exception has occured
   723 `endif
   724 `ifdef CFG_MC_DIVIDE_ENABLED
   725 wire divide_by_zero_exception;                  // Indicates if a divide by zero exception has occured
   726 `endif
   727 wire system_call_exception;                     // Indicates if a system call exception has occured
   729 `ifdef CFG_BUS_ERRORS_ENABLED
   730 reg data_bus_error_seen;                        // Indicates if a data bus error was seen
   731 `endif
   733 /////////////////////////////////////////////////////
   734 // Functions
   735 /////////////////////////////////////////////////////
   737 `include "lm32_functions.v"
   739 /////////////////////////////////////////////////////
   740 // Instantiations
   741 ///////////////////////////////////////////////////// 
   743 // Instruction unit
   744 lm32_instruction_unit #(
   745     .associativity          (icache_associativity),
   746     .sets                   (icache_sets),
   747     .bytes_per_line         (icache_bytes_per_line),
   748     .base_address           (icache_base_address),
   749     .limit                  (icache_limit)
   750   ) instruction_unit (
   751     // ----- Inputs -------
   752     .clk_i                  (clk_i),
   753     .rst_i                  (rst_i),
   754     // From pipeline
   755     .stall_a                (stall_a),
   756     .stall_f                (stall_f),
   757     .stall_d                (stall_d),
   758     .stall_x                (stall_x),
   759     .stall_m                (stall_m),
   760     .valid_f                (valid_f),
   761     .valid_d                (valid_d),
   762     .kill_f                 (kill_f),
   763     .branch_predict_taken_d (branch_predict_taken_d),
   764     .branch_predict_address_d (branch_predict_address_d),
   765 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   766     .branch_taken_x         (branch_taken_x),
   767     .branch_target_x        (branch_target_x),
   768 `endif
   769     .exception_m            (exception_m),
   770     .branch_taken_m         (branch_taken_m),
   771     .branch_mispredict_taken_m (branch_mispredict_taken_m),
   772     .branch_target_m        (branch_target_m),
   773 `ifdef CFG_ICACHE_ENABLED
   774     .iflush                 (iflush),
   775 `endif
   776 `ifdef CFG_IROM_ENABLED
   777     .irom_store_data_m      (irom_store_data_m),
   778     .irom_address_xm        (irom_address_xm),
   779     .irom_we_xm             (irom_we_xm),
   780 `endif
   781 `ifdef CFG_DCACHE_ENABLED
   782     .dcache_restart_request (dcache_restart_request),
   783     .dcache_refill_request  (dcache_refill_request),
   784     .dcache_refilling       (dcache_refilling),
   785 `endif        
   786 `ifdef CFG_IWB_ENABLED
   787     // From Wishbone
   788     .i_dat_i                (I_DAT_I),
   789     .i_ack_i                (I_ACK_I),
   790     .i_err_i                (I_ERR_I),
   791 `endif
   792 `ifdef CFG_HW_DEBUG_ENABLED
   793     .jtag_read_enable       (jtag_read_enable),
   794     .jtag_write_enable      (jtag_write_enable),
   795     .jtag_write_data        (jtag_write_data),
   796     .jtag_address           (jtag_address),
   797 `endif
   798     // ----- Outputs -------
   799     // To pipeline
   800     .pc_f                   (pc_f),
   801     .pc_d                   (pc_d),
   802     .pc_x                   (pc_x),
   803     .pc_m                   (pc_m),
   804     .pc_w                   (pc_w),
   805 `ifdef CFG_ICACHE_ENABLED
   806     .icache_stall_request   (icache_stall_request),
   807     .icache_restart_request (icache_restart_request),
   808     .icache_refill_request  (icache_refill_request),
   809     .icache_refilling       (icache_refilling),
   810 `endif
   811 `ifdef CFG_IROM_ENABLED
   812     .irom_data_m            (irom_data_m),
   813 `endif
   814 `ifdef CFG_IWB_ENABLED
   815     // To Wishbone
   816     .i_dat_o                (I_DAT_O),
   817     .i_adr_o                (I_ADR_O),
   818     .i_cyc_o                (I_CYC_O),
   819     .i_sel_o                (I_SEL_O),
   820     .i_stb_o                (I_STB_O),
   821     .i_we_o                 (I_WE_O),
   822     .i_cti_o                (I_CTI_O),
   823     .i_lock_o               (I_LOCK_O),
   824     .i_bte_o                (I_BTE_O),
   825 `endif
   826 `ifdef CFG_HW_DEBUG_ENABLED
   827     .jtag_read_data         (jtag_read_data),
   828     .jtag_access_complete   (jtag_access_complete),
   829 `endif
   830 `ifdef CFG_BUS_ERRORS_ENABLED
   831     .bus_error_d            (bus_error_d),
   832 `endif
   833 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   834     .instruction_f          (instruction_f),
   835 `endif
   836     .instruction_d          (instruction_d)
   837     );
   839 // Instruction decoder
   840 lm32_decoder decoder (
   841     // ----- Inputs -------
   842     .instruction            (instruction_d),
   843     // ----- Outputs -------
   844     .d_result_sel_0         (d_result_sel_0_d),
   845     .d_result_sel_1         (d_result_sel_1_d),
   846     .x_result_sel_csr       (x_result_sel_csr_d),
   847 `ifdef LM32_MC_ARITHMETIC_ENABLED
   848     .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
   849 `endif
   850 `ifdef LM32_NO_BARREL_SHIFT    
   851     .x_result_sel_shift     (x_result_sel_shift_d),
   852 `endif
   853 `ifdef CFG_SIGN_EXTEND_ENABLED
   854     .x_result_sel_sext      (x_result_sel_sext_d),
   855 `endif    
   856     .x_result_sel_logic     (x_result_sel_logic_d),
   857 `ifdef CFG_USER_ENABLED
   858     .x_result_sel_user      (x_result_sel_user_d),
   859 `endif
   860     .x_result_sel_add       (x_result_sel_add_d),
   861     .m_result_sel_compare   (m_result_sel_compare_d),
   862 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   863     .m_result_sel_shift     (m_result_sel_shift_d),  
   864 `endif    
   865     .w_result_sel_load      (w_result_sel_load_d),
   866 `ifdef CFG_PL_MULTIPLY_ENABLED
   867     .w_result_sel_mul       (w_result_sel_mul_d),
   868 `endif
   869     .x_bypass_enable        (x_bypass_enable_d),
   870     .m_bypass_enable        (m_bypass_enable_d),
   871     .read_enable_0          (read_enable_0_d),
   872     .read_idx_0             (read_idx_0_d),
   873     .read_enable_1          (read_enable_1_d),
   874     .read_idx_1             (read_idx_1_d),
   875     .write_enable           (write_enable_d),
   876     .write_idx              (write_idx_d),
   877     .immediate              (immediate_d),
   878     .branch_offset          (branch_offset_d),
   879     .load                   (load_d),
   880     .store                  (store_d),
   881     .size                   (size_d),
   882     .sign_extend            (sign_extend_d),
   883     .adder_op               (adder_op_d),
   884     .logic_op               (logic_op_d),
   885 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   886     .direction              (direction_d),
   887 `endif
   888 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   889     .shift_left             (shift_left_d),
   890     .shift_right            (shift_right_d),
   891 `endif
   892 `ifdef CFG_MC_MULTIPLY_ENABLED
   893     .multiply               (multiply_d),
   894 `endif
   895 `ifdef CFG_MC_DIVIDE_ENABLED
   896     .divide                 (divide_d),
   897     .modulus                (modulus_d),
   898 `endif
   899     .branch                 (branch_d),
   900     .bi_unconditional       (bi_unconditional),
   901     .bi_conditional         (bi_conditional),
   902     .branch_reg             (branch_reg_d),
   903     .condition              (condition_d),
   904 `ifdef CFG_DEBUG_ENABLED
   905     .break_opcode           (break_d),
   906 `endif
   907     .scall                  (scall_d),
   908     .eret                   (eret_d),
   909 `ifdef CFG_DEBUG_ENABLED
   910     .bret                   (bret_d),
   911 `endif
   912 `ifdef CFG_USER_ENABLED
   913     .user_opcode            (user_opcode_d),
   914 `endif
   915     .csr_write_enable       (csr_write_enable_d)
   916     ); 
   918 // Load/store unit       
   919 lm32_load_store_unit #(
   920     .associativity          (dcache_associativity),
   921     .sets                   (dcache_sets),
   922     .bytes_per_line         (dcache_bytes_per_line),
   923     .base_address           (dcache_base_address),
   924     .limit                  (dcache_limit)
   925   ) load_store_unit (
   926     // ----- Inputs -------
   927     .clk_i                  (clk_i),
   928     .rst_i                  (rst_i),
   929     // From pipeline
   930     .stall_a                (stall_a),
   931     .stall_x                (stall_x),
   932     .stall_m                (stall_m),
   933     .kill_m                 (kill_m),
   934     .exception_m            (exception_m),
   935     .store_operand_x        (store_operand_x),
   936     .load_store_address_x   (adder_result_x),
   937     .load_store_address_m   (operand_m),
   938     .load_store_address_w   (operand_w[1:0]),
   939     .load_x                 (load_x),
   940     .store_x                (store_x),
   941     .load_q_x               (load_q_x),
   942     .store_q_x              (store_q_x),
   943     .load_q_m               (load_q_m),
   944     .store_q_m              (store_q_m),
   945     .sign_extend_x          (sign_extend_x),
   946     .size_x                 (size_x),
   947 `ifdef CFG_DCACHE_ENABLED
   948     .dflush                 (dflush_m),
   949 `endif
   950 `ifdef CFG_IROM_ENABLED
   951     .irom_data_m            (irom_data_m),
   952 `endif
   953     // From Wishbone
   954     .d_dat_i                (D_DAT_I),
   955     .d_ack_i                (D_ACK_I),
   956     .d_err_i                (D_ERR_I),
   957     // ----- Outputs -------
   958     // To pipeline
   959 `ifdef CFG_DCACHE_ENABLED
   960     .dcache_refill_request  (dcache_refill_request),
   961     .dcache_restart_request (dcache_restart_request),
   962     .dcache_stall_request   (dcache_stall_request),
   963     .dcache_refilling       (dcache_refilling),
   964 `endif    
   965 `ifdef CFG_IROM_ENABLED
   966     .irom_store_data_m      (irom_store_data_m),
   967     .irom_address_xm        (irom_address_xm),
   968     .irom_we_xm             (irom_we_xm),
   969     .irom_stall_request_x   (irom_stall_request_x),
   970 `endif
   971     .load_data_w            (load_data_w),
   972     .stall_wb_load          (stall_wb_load),
   973     // To Wishbone
   974     .d_dat_o                (D_DAT_O),
   975     .d_adr_o                (D_ADR_O),
   976     .d_cyc_o                (D_CYC_O),
   977     .d_sel_o                (D_SEL_O),
   978     .d_stb_o                (D_STB_O),
   979     .d_we_o                 (D_WE_O),
   980     .d_cti_o                (D_CTI_O),
   981     .d_lock_o               (D_LOCK_O),
   982     .d_bte_o                (D_BTE_O)
   983     );      
   985 // Adder       
   986 lm32_adder adder (
   987     // ----- Inputs -------
   988     .adder_op_x             (adder_op_x),
   989     .adder_op_x_n           (adder_op_x_n),
   990     .operand_0_x            (operand_0_x),
   991     .operand_1_x            (operand_1_x),
   992     // ----- Outputs -------
   993     .adder_result_x         (adder_result_x),
   994     .adder_carry_n_x        (adder_carry_n_x),
   995     .adder_overflow_x       (adder_overflow_x)
   996     );
   998 // Logic operations
   999 lm32_logic_op logic_op (
  1000     // ----- Inputs -------
  1001     .logic_op_x             (logic_op_x),
  1002     .operand_0_x            (operand_0_x),
  1004     .operand_1_x            (operand_1_x),
  1005     // ----- Outputs -------
  1006     .logic_result_x         (logic_result_x)
  1007     );
  1009 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1010 // Pipelined barrel-shifter
  1011 lm32_shifter shifter (
  1012     // ----- Inputs -------
  1013     .clk_i                  (clk_i),
  1014     .rst_i                  (rst_i),
  1015     .stall_x                (stall_x),
  1016     .direction_x            (direction_x),
  1017     .sign_extend_x          (sign_extend_x),
  1018     .operand_0_x            (operand_0_x),
  1019     .operand_1_x            (operand_1_x),
  1020     // ----- Outputs -------
  1021     .shifter_result_m       (shifter_result_m)
  1022     );
  1023 `endif
  1025 `ifdef CFG_PL_MULTIPLY_ENABLED
  1026 // Pipeline fixed-point multiplier
  1027 lm32_multiplier multiplier (
  1028     // ----- Inputs -------
  1029     .clk_i                  (clk_i),
  1030     .rst_i                  (rst_i),
  1031     .stall_x                (stall_x),
  1032     .stall_m                (stall_m),
  1033     .operand_0              (d_result_0),
  1034     .operand_1              (d_result_1),
  1035     // ----- Outputs -------
  1036     .result                 (multiplier_result_w)    
  1037     );
  1038 `endif
  1040 `ifdef LM32_MC_ARITHMETIC_ENABLED
  1041 // Multi-cycle arithmetic
  1042 lm32_mc_arithmetic mc_arithmetic (
  1043     // ----- Inputs -------
  1044     .clk_i                  (clk_i),
  1045     .rst_i                  (rst_i),
  1046     .stall_d                (stall_d),
  1047     .kill_x                 (kill_x),
  1048 `ifdef CFG_MC_DIVIDE_ENABLED                  
  1049     .divide_d               (divide_q_d),
  1050     .modulus_d              (modulus_q_d),
  1051 `endif
  1052 `ifdef CFG_MC_MULTIPLY_ENABLED        
  1053     .multiply_d             (multiply_q_d),
  1054 `endif
  1055 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
  1056     .shift_left_d           (shift_left_q_d),
  1057     .shift_right_d          (shift_right_q_d),
  1058     .sign_extend_d          (sign_extend_d),
  1059 `endif    
  1060     .operand_0_d            (d_result_0),
  1061     .operand_1_d            (d_result_1),
  1062     // ----- Outputs -------
  1063     .result_x               (mc_result_x),
  1064 `ifdef CFG_MC_DIVIDE_ENABLED                  
  1065     .divide_by_zero_x       (divide_by_zero_x),
  1066 `endif
  1067     .stall_request_x        (mc_stall_request_x)
  1068     );
  1069 `endif
  1071 `ifdef CFG_INTERRUPTS_ENABLED
  1072 // Interrupt unit
  1073 lm32_interrupt interrupt (
  1074     // ----- Inputs -------
  1075     .clk_i                  (clk_i), 
  1076     .rst_i                  (rst_i),
  1077     // From external devices
  1078     .interrupt_n            (interrupt_n),
  1079     // From pipeline
  1080     .stall_x                (stall_x),
  1081 `ifdef CFG_DEBUG_ENABLED
  1082     .non_debug_exception    (non_debug_exception_q_w), 
  1083     .debug_exception        (debug_exception_q_w),
  1084 `else
  1085     .exception              (exception_q_w), 
  1086 `endif
  1087     .eret_q_x               (eret_q_x),
  1088 `ifdef CFG_DEBUG_ENABLED
  1089     .bret_q_x               (bret_q_x),
  1090 `endif
  1091     .csr                    (csr_x),
  1092     .csr_write_data         (operand_1_x),
  1093     .csr_write_enable       (csr_write_enable_q_x),
  1094     // ----- Outputs -------
  1095     .interrupt_exception    (interrupt_exception),
  1096     // To pipeline
  1097     .csr_read_data          (interrupt_csr_read_data_x)
  1098     );
  1099 `endif
  1101 `ifdef CFG_JTAG_ENABLED
  1102 // JTAG interface
  1103 lm32_jtag jtag (
  1104     // ----- Inputs -------
  1105     .clk_i                  (clk_i),
  1106     .rst_i                  (rst_i),
  1107     // From JTAG
  1108     .jtag_clk               (jtag_clk),
  1109     .jtag_update            (jtag_update),
  1110     .jtag_reg_q             (jtag_reg_q),
  1111     .jtag_reg_addr_q        (jtag_reg_addr_q),
  1112     // From pipeline
  1113 `ifdef CFG_JTAG_UART_ENABLED
  1114     .csr                    (csr_x),
  1115     .csr_write_data         (operand_1_x),
  1116     .csr_write_enable       (csr_write_enable_q_x),
  1117     .stall_x                (stall_x),
  1118 `endif
  1119 `ifdef CFG_HW_DEBUG_ENABLED
  1120     .jtag_read_data         (jtag_read_data),
  1121     .jtag_access_complete   (jtag_access_complete),
  1122 `endif
  1123 `ifdef CFG_DEBUG_ENABLED
  1124     .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
  1125 `endif    
  1126     // ----- Outputs -------
  1127     // To pipeline
  1128 `ifdef CFG_JTAG_UART_ENABLED
  1129     .jtx_csr_read_data      (jtx_csr_read_data),
  1130     .jrx_csr_read_data      (jrx_csr_read_data),
  1131 `endif
  1132 `ifdef CFG_HW_DEBUG_ENABLED
  1133     .jtag_csr_write_enable  (jtag_csr_write_enable),
  1134     .jtag_csr_write_data    (jtag_csr_write_data),
  1135     .jtag_csr               (jtag_csr),
  1136     .jtag_read_enable       (jtag_read_enable),
  1137     .jtag_write_enable      (jtag_write_enable),
  1138     .jtag_write_data        (jtag_write_data),
  1139     .jtag_address           (jtag_address),
  1140 `endif
  1141 `ifdef CFG_DEBUG_ENABLED
  1142     .jtag_break             (jtag_break),
  1143     .jtag_reset             (reset_exception),
  1144 `endif
  1145     // To JTAG 
  1146     .jtag_reg_d             (jtag_reg_d),
  1147     .jtag_reg_addr_d        (jtag_reg_addr_d)
  1148     );
  1149 `endif
  1151 `ifdef CFG_DEBUG_ENABLED
  1152 // Debug unit
  1153 lm32_debug #(
  1154     .breakpoints            (breakpoints),
  1155     .watchpoints            (watchpoints)
  1156   ) hw_debug (
  1157     // ----- Inputs -------
  1158     .clk_i                  (clk_i), 
  1159     .rst_i                  (rst_i),
  1160     .pc_x                   (pc_x),
  1161     .load_x                 (load_x),
  1162     .store_x                (store_x),
  1163     .load_store_address_x   (adder_result_x),
  1164     .csr_write_enable_x     (csr_write_enable_q_x),
  1165     .csr_write_data         (operand_1_x),
  1166     .csr_x                  (csr_x),
  1167 `ifdef CFG_HW_DEBUG_ENABLED
  1168     .jtag_csr_write_enable  (jtag_csr_write_enable),
  1169     .jtag_csr_write_data    (jtag_csr_write_data),
  1170     .jtag_csr               (jtag_csr),
  1171 `endif
  1172 `ifdef LM32_SINGLE_STEP_ENABLED
  1173     .eret_q_x               (eret_q_x),
  1174     .bret_q_x               (bret_q_x),
  1175     .stall_x                (stall_x),
  1176     .exception_x            (exception_x),
  1177     .q_x                    (q_x),
  1178 `ifdef CFG_DCACHE_ENABLED
  1179     .dcache_refill_request  (dcache_refill_request),
  1180 `endif
  1181 `endif
  1182     // ----- Outputs -------
  1183 `ifdef LM32_SINGLE_STEP_ENABLED
  1184     .dc_ss                  (dc_ss),
  1185 `endif
  1186     .dc_re                  (dc_re),
  1187     .bp_match               (bp_match),
  1188     .wp_match               (wp_match)
  1189     );
  1190 `endif
  1192 // Register file
  1194 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  1195    /*----------------------------------------------------------------------
  1196     Register File is implemented using EBRs. There can be three accesses to
  1197     the register file in each cycle: two reads and one write. On-chip block
  1198     RAM has two read/write ports. To accomodate three accesses, two on-chip
  1199     block RAMs are used (each register file "write" is made to both block
  1200     RAMs).
  1202     One limitation of the on-chip block RAMs is that one cannot perform a 
  1203     read and write to same location in a cycle (if this is done, then the
  1204     data read out is indeterminate).
  1205     ----------------------------------------------------------------------*/
  1206    wire [31:0] regfile_data_0, regfile_data_1;
  1207    reg [31:0]  w_result_d;
  1208    reg 	       regfile_raw_0, regfile_raw_0_nxt;
  1209    reg 	       regfile_raw_1, regfile_raw_1_nxt;
  1211    /*----------------------------------------------------------------------
  1212     Check if read and write is being performed to same register in current 
  1213     cycle? This is done by comparing the read and write IDXs.
  1214     ----------------------------------------------------------------------*/
  1215    always @(reg_write_enable_q_w or write_idx_w or instruction_f)
  1216      begin
  1217 	if (reg_write_enable_q_w
  1218 	    && (write_idx_w == instruction_f[25:21]))
  1219 	  regfile_raw_0_nxt = 1'b1;
  1220 	else
  1221 	  regfile_raw_0_nxt = 1'b0;
  1223 	if (reg_write_enable_q_w
  1224 	    && (write_idx_w == instruction_f[20:16]))
  1225 	  regfile_raw_1_nxt = 1'b1;
  1226 	else
  1227 	  regfile_raw_1_nxt = 1'b0;
  1228      end
  1230    /*----------------------------------------------------------------------
  1231     Select latched (delayed) write value or data from register file. If 
  1232     read in previous cycle was performed to register written to in same
  1233     cycle, then latched (delayed) write value is selected.
  1234     ----------------------------------------------------------------------*/
  1235    always @(regfile_raw_0 or w_result_d or regfile_data_0)
  1236      if (regfile_raw_0)
  1237        reg_data_live_0 = w_result_d;
  1238      else
  1239        reg_data_live_0 = regfile_data_0;
  1241    /*----------------------------------------------------------------------
  1242     Select latched (delayed) write value or data from register file. If 
  1243     read in previous cycle was performed to register written to in same
  1244     cycle, then latched (delayed) write value is selected.
  1245     ----------------------------------------------------------------------*/
  1246    always @(regfile_raw_1 or w_result_d or regfile_data_1)
  1247      if (regfile_raw_1)
  1248        reg_data_live_1 = w_result_d;
  1249      else
  1250        reg_data_live_1 = regfile_data_1;
  1252    /*----------------------------------------------------------------------
  1253     Latch value written to register file
  1254     ----------------------------------------------------------------------*/
  1255    always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  1256      if (rst_i == `TRUE)
  1257        begin
  1258 	  regfile_raw_0 <= 1'b0;
  1259 	  regfile_raw_1 <= 1'b0;
  1260 	  w_result_d <= 32'b0;
  1261        end
  1262      else
  1263        begin
  1264 	  regfile_raw_0 <= regfile_raw_0_nxt;
  1265 	  regfile_raw_1 <= regfile_raw_1_nxt;
  1266 	  w_result_d <= w_result;
  1267        end
  1269    /*----------------------------------------------------------------------
  1270     Register file instantiation as Pseudo-Dual Port EBRs.
  1271     ----------------------------------------------------------------------*/
  1272    pmi_ram_dp
  1273      #(
  1274        // ----- Parameters -----
  1275        .pmi_wr_addr_depth(1<<5),
  1276        .pmi_wr_addr_width(5),
  1277        .pmi_wr_data_width(32),
  1278        .pmi_rd_addr_depth(1<<5),
  1279        .pmi_rd_addr_width(5),
  1280        .pmi_rd_data_width(32),
  1281        .pmi_regmode("noreg"),
  1282        .pmi_gsr("enable"),
  1283        .pmi_resetmode("sync"),
  1284        .pmi_init_file("none"),
  1285        .pmi_init_file_format("binary"),
  1286        .pmi_family(`LATTICE_FAMILY),
  1287        .module_type("pmi_ram_dp")
  1289    reg_0
  1291       // ----- Inputs -----
  1292       .Data(w_result),
  1293       .WrAddress(write_idx_w),
  1294       .RdAddress(instruction_f[25:21]),
  1295       .WrClock(clk_i),
  1296       .RdClock(clk_i),
  1297       .WrClockEn(`TRUE),
  1298       .RdClockEn(`TRUE),
  1299       .WE(reg_write_enable_q_w),
  1300       .Reset(rst_i), 
  1301       // ----- Outputs -----
  1302       .Q(regfile_data_0)
  1303       );
  1305    pmi_ram_dp
  1306      #(
  1307        // ----- Parameters -----
  1308        .pmi_wr_addr_depth(1<<5),
  1309        .pmi_wr_addr_width(5),
  1310        .pmi_wr_data_width(32),
  1311        .pmi_rd_addr_depth(1<<5),
  1312        .pmi_rd_addr_width(5),
  1313        .pmi_rd_data_width(32),
  1314        .pmi_regmode("noreg"),
  1315        .pmi_gsr("enable"),
  1316        .pmi_resetmode("sync"),
  1317        .pmi_init_file("none"),
  1318        .pmi_init_file_format("binary"),
  1319        .pmi_family(`LATTICE_FAMILY),
  1320        .module_type("pmi_ram_dp")
  1322    reg_1
  1324       // ----- Inputs -----
  1325       .Data(w_result),
  1326       .WrAddress(write_idx_w),
  1327       .RdAddress(instruction_f[20:16]),
  1328       .WrClock(clk_i),
  1329       .RdClock(clk_i),
  1330       .WrClockEn(`TRUE),
  1331       .RdClockEn(`TRUE),
  1332       .WE(reg_write_enable_q_w),
  1333       .Reset(rst_i), 
  1334       // ----- Outputs -----
  1335       .Q(regfile_data_1)
  1336       );
  1337 `endif
  1339 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  1340    pmi_ram_dp
  1341      #(
  1342        // ----- Parameters -----
  1343        .pmi_wr_addr_depth(1<<5),
  1344        .pmi_wr_addr_width(5),
  1345        .pmi_wr_data_width(32),
  1346        .pmi_rd_addr_depth(1<<5),
  1347        .pmi_rd_addr_width(5),
  1348        .pmi_rd_data_width(32),
  1349        .pmi_regmode("noreg"),
  1350        .pmi_gsr("enable"),
  1351        .pmi_resetmode("sync"),
  1352        .pmi_init_file("none"),
  1353        .pmi_init_file_format("binary"),
  1354        .pmi_family(`LATTICE_FAMILY),
  1355        .module_type("pmi_ram_dp")
  1357    reg_0
  1359       // ----- Inputs -----
  1360       .Data(w_result),
  1361       .WrAddress(write_idx_w),
  1362       .RdAddress(read_idx_0_d),
  1363       .WrClock(clk_i),
  1364       .RdClock(clk_n_i),
  1365       .WrClockEn(`TRUE),
  1366       .RdClockEn(stall_f == `FALSE),
  1367       .WE(reg_write_enable_q_w),
  1368       .Reset(rst_i), 
  1369       // ----- Outputs -----
  1370       .Q(reg_data_0)
  1371       );
  1373    pmi_ram_dp
  1374      #(
  1375        // ----- Parameters -----
  1376        .pmi_wr_addr_depth(1<<5),
  1377        .pmi_wr_addr_width(5),
  1378        .pmi_wr_data_width(32),
  1379        .pmi_rd_addr_depth(1<<5),
  1380        .pmi_rd_addr_width(5),
  1381        .pmi_rd_data_width(32),
  1382        .pmi_regmode("noreg"),
  1383        .pmi_gsr("enable"),
  1384        .pmi_resetmode("sync"),
  1385        .pmi_init_file("none"),
  1386        .pmi_init_file_format("binary"),
  1387        .pmi_family(`LATTICE_FAMILY),
  1388        .module_type("pmi_ram_dp")
  1390    reg_1
  1392       // ----- Inputs -----
  1393       .Data(w_result),
  1394       .WrAddress(write_idx_w),
  1395       .RdAddress(read_idx_1_d),
  1396       .WrClock(clk_i),
  1397       .RdClock(clk_n_i),
  1398       .WrClockEn(`TRUE),
  1399       .RdClockEn(stall_f == `FALSE),
  1400       .WE(reg_write_enable_q_w),
  1401       .Reset(rst_i), 
  1402       // ----- Outputs -----
  1403       .Q(reg_data_1)
  1404       );
  1405 `endif
  1408 /////////////////////////////////////////////////////
  1409 // Combinational Logic
  1410 /////////////////////////////////////////////////////
  1412 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  1413 // Select between buffered and live data from register file
  1414 assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
  1415 assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
  1416 `endif
  1417 `ifdef LM32_EBR_REGISTER_FILE
  1418 `else
  1419 // Register file read ports
  1420 assign reg_data_0 = registers[read_idx_0_d];
  1421 assign reg_data_1 = registers[read_idx_1_d];
  1422 `endif
  1424 // Detect read-after-write hazzards
  1425 assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
  1426 assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
  1427 assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
  1428 assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
  1429 assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
  1430 assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
  1432 // Interlock detection - Raise an interlock for RAW hazzards 
  1433 always @(*)
  1434 begin
  1435     if (   (   (x_bypass_enable_x == `FALSE)
  1436             && (   ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
  1437                 || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
  1440         || (   (m_bypass_enable_m == `FALSE)
  1441             && (   ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
  1442                 || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
  1446         interlock = `TRUE;
  1447     else
  1448         interlock = `FALSE;
  1449 end
  1451 // Bypass for reg port 0
  1452 always @(*)
  1453 begin
  1454     if (raw_x_0 == `TRUE)        
  1455         bypass_data_0 = x_result;
  1456     else if (raw_m_0 == `TRUE)
  1457         bypass_data_0 = m_result;
  1458     else if (raw_w_0 == `TRUE)
  1459         bypass_data_0 = w_result;
  1460     else
  1461         bypass_data_0 = reg_data_0;
  1462 end
  1464 // Bypass for reg port 1
  1465 always @(*)
  1466 begin
  1467     if (raw_x_1 == `TRUE)
  1468         bypass_data_1 = x_result;
  1469     else if (raw_m_1 == `TRUE)
  1470         bypass_data_1 = m_result;
  1471     else if (raw_w_1 == `TRUE)
  1472         bypass_data_1 = w_result;
  1473     else
  1474         bypass_data_1 = reg_data_1;
  1475 end
  1477    /*----------------------------------------------------------------------
  1478     Branch prediction is performed in D stage of pipeline. Only PC-relative
  1479     branches are predicted: forward-pointing conditional branches are not-
  1480     taken, while backward-pointing conditional branches are taken. 
  1481     Unconditional branches are always predicted taken!
  1482     ----------------------------------------------------------------------*/
  1483    assign branch_predict_d = bi_unconditional | bi_conditional;
  1484    assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
  1486    // Compute branch target address: Branch PC PLUS Offset
  1487    assign branch_target_d = pc_d + branch_offset_d;
  1489    // Compute fetch address. Address of instruction sequentially after the
  1490    // branch if branch is not taken. Target address of branch is branch is
  1491    // taken
  1492    assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
  1494 // D stage result selection
  1495 always @(*)
  1496 begin
  1497     d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
  1498     case (d_result_sel_1_d)
  1499     `LM32_D_RESULT_SEL_1_ZERO:      d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
  1500     `LM32_D_RESULT_SEL_1_REG_1:     d_result_1 = bypass_data_1;
  1501     `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
  1502     default:                        d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
  1503     endcase
  1504 end
  1506 `ifdef CFG_USER_ENABLED    
  1507 // Operands for user-defined instructions
  1508 assign user_operand_0 = operand_0_x;
  1509 assign user_operand_1 = operand_1_x;
  1510 `endif
  1512 `ifdef CFG_SIGN_EXTEND_ENABLED
  1513 // Sign-extension
  1514 assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
  1515 assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
  1516 assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
  1517 `endif
  1519 `ifdef LM32_NO_BARREL_SHIFT
  1520 // Only single bit shift operations are supported when barrel-shifter isn't implemented
  1521 assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
  1522 `endif
  1524 // Condition evaluation
  1525 assign cmp_zero = operand_0_x == operand_1_x;
  1526 assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
  1527 assign cmp_overflow = adder_overflow_x;
  1528 assign cmp_carry_n = adder_carry_n_x;
  1529 always @(*)
  1530 begin
  1531     case (condition_x)
  1532     `LM32_CONDITION_U1:   condition_met_x = `TRUE;
  1533     `LM32_CONDITION_U2:   condition_met_x = `TRUE;
  1534     `LM32_CONDITION_E:    condition_met_x = cmp_zero;
  1535     `LM32_CONDITION_NE:   condition_met_x = !cmp_zero;
  1536     `LM32_CONDITION_G:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
  1537     `LM32_CONDITION_GU:   condition_met_x = cmp_carry_n && !cmp_zero;
  1538     `LM32_CONDITION_GE:   condition_met_x = cmp_negative == cmp_overflow;
  1539     `LM32_CONDITION_GEU:  condition_met_x = cmp_carry_n;
  1540     default:              condition_met_x = 1'bx;
  1541     endcase 
  1542 end
  1544 // X stage result selection
  1545 always @(*)
  1546 begin
  1547     x_result =   x_result_sel_add_x ? adder_result_x 
  1548                : x_result_sel_csr_x ? csr_read_data_x
  1549 `ifdef CFG_SIGN_EXTEND_ENABLED
  1550                : x_result_sel_sext_x ? sext_result_x
  1551 `endif
  1552 `ifdef CFG_USER_ENABLED
  1553                : x_result_sel_user_x ? user_result
  1554 `endif
  1555 `ifdef LM32_NO_BARREL_SHIFT
  1556                : x_result_sel_shift_x ? shifter_result_x
  1557 `endif
  1558 `ifdef LM32_MC_ARITHMETIC_ENABLED
  1559                : x_result_sel_mc_arith_x ? mc_result_x
  1560 `endif
  1561                : logic_result_x;
  1562 end
  1564 // M stage result selection
  1565 always @(*)
  1566 begin
  1567     m_result =   m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
  1568 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1569                : m_result_sel_shift_m ? shifter_result_m
  1570 `endif
  1571                : operand_m; 
  1572 end
  1574 // W stage result selection
  1575 always @(*)
  1576 begin
  1577     w_result =    w_result_sel_load_w ? load_data_w
  1578 `ifdef CFG_PL_MULTIPLY_ENABLED
  1579                 : w_result_sel_mul_w ? multiplier_result_w
  1580 `endif
  1581                 : operand_w;
  1582 end
  1584 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  1585 // Indicate when a branch should be taken in X stage
  1586 assign branch_taken_x =      (stall_x == `FALSE)
  1587                           && (   (branch_x == `TRUE)
  1588                               && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
  1589                               && (valid_x == `TRUE)
  1590                               && (branch_predict_x == `FALSE)
  1591                              ); 
  1592 `endif
  1594 // Indicate when a branch should be taken in M stage (exceptions are a type of branch)
  1595 assign branch_taken_m =      (stall_m == `FALSE) 
  1596                           && (   (   (branch_m == `TRUE) 
  1597                                   && (valid_m == `TRUE)
  1598                                   && (   (   (condition_met_m == `TRUE)
  1599 					  && (branch_predict_taken_m == `FALSE)
  1601 				      || (   (condition_met_m == `FALSE)
  1602 					  && (branch_predict_m == `TRUE)
  1603 					  && (branch_predict_taken_m == `TRUE)
  1607                               || (exception_m == `TRUE)
  1608                              );
  1610 // Indicate when a branch in M stage is mispredicted as being taken
  1611 assign branch_mispredict_taken_m =    (condition_met_m == `FALSE)
  1612                                    && (branch_predict_m == `TRUE)
  1613 	   			   && (branch_predict_taken_m == `TRUE);
  1615 // Indicate when a branch in M stage will cause flush in X stage
  1616 assign branch_flushX_m =    (stall_m == `FALSE)
  1617                          && (   (   (branch_m == `TRUE) 
  1618                                  && (valid_m == `TRUE)
  1619 			         && (   (condition_met_m == `TRUE)
  1620 				     || (   (condition_met_m == `FALSE)
  1621 					 && (branch_predict_m == `TRUE)
  1622 					 && (branch_predict_taken_m == `TRUE)
  1626 			     || (exception_m == `TRUE)
  1627 			    );
  1629 // Generate signal that will kill instructions in each pipeline stage when necessary
  1630 assign kill_f =    (   (valid_d == `TRUE)
  1631                     && (branch_predict_taken_d == `TRUE)
  1633                 || (branch_taken_m == `TRUE) 
  1634 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  1635                 || (branch_taken_x == `TRUE)
  1636 `endif
  1637 `ifdef CFG_ICACHE_ENABLED
  1638                 || (icache_refill_request == `TRUE) 
  1639 `endif
  1640 `ifdef CFG_DCACHE_ENABLED                
  1641                 || (dcache_refill_request == `TRUE)
  1642 `endif
  1644 assign kill_d =    (branch_taken_m == `TRUE) 
  1645 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  1646                 || (branch_taken_x == `TRUE)
  1647 `endif
  1648 `ifdef CFG_ICACHE_ENABLED
  1649                 || (icache_refill_request == `TRUE)     
  1650 `endif                
  1651 `ifdef CFG_DCACHE_ENABLED                
  1652                 || (dcache_refill_request == `TRUE)
  1653 `endif
  1655 assign kill_x =    (branch_flushX_m == `TRUE) 
  1656 `ifdef CFG_DCACHE_ENABLED                
  1657                 || (dcache_refill_request == `TRUE)
  1658 `endif
  1660 assign kill_m =    `FALSE
  1661 `ifdef CFG_DCACHE_ENABLED                
  1662                 || (dcache_refill_request == `TRUE)
  1663 `endif
  1665 assign kill_w =    `FALSE
  1666 `ifdef CFG_DCACHE_ENABLED                
  1667                 || (dcache_refill_request == `TRUE)
  1668 `endif                
  1671 // Exceptions
  1673 `ifdef CFG_DEBUG_ENABLED
  1674 assign breakpoint_exception =    (   (   (break_x == `TRUE)
  1675 				      || (bp_match == `TRUE)
  1677 				  && (valid_x == `TRUE)
  1679 `ifdef CFG_JTAG_ENABLED
  1680                               || (jtag_break == `TRUE)
  1681 `endif
  1683 `endif
  1685 `ifdef CFG_DEBUG_ENABLED
  1686 assign watchpoint_exception = wp_match == `TRUE;
  1687 `endif
  1689 `ifdef CFG_BUS_ERRORS_ENABLED
  1690 assign instruction_bus_error_exception = (   (bus_error_x == `TRUE)
  1691                                           && (valid_x == `TRUE)
  1692                                          );
  1693 assign data_bus_error_exception = data_bus_error_seen == `TRUE;
  1694 `endif
  1696 `ifdef CFG_MC_DIVIDE_ENABLED
  1697 assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
  1698 `endif
  1700 assign system_call_exception = (   (scall_x == `TRUE)
  1701 `ifdef CFG_BUS_ERRORS_ENABLED
  1702                                 && (valid_x == `TRUE)
  1703 `endif
  1704 			       );
  1706 `ifdef CFG_DEBUG_ENABLED
  1707 assign debug_exception_x =  (breakpoint_exception == `TRUE)
  1708                          || (watchpoint_exception == `TRUE)
  1711 assign non_debug_exception_x = (system_call_exception == `TRUE)
  1712 `ifdef CFG_JTAG_ENABLED
  1713                             || (reset_exception == `TRUE)
  1714 `endif
  1715 `ifdef CFG_BUS_ERRORS_ENABLED
  1716                             || (instruction_bus_error_exception == `TRUE)
  1717                             || (data_bus_error_exception == `TRUE)
  1718 `endif
  1719 `ifdef CFG_MC_DIVIDE_ENABLED
  1720                             || (divide_by_zero_exception == `TRUE)
  1721 `endif
  1722 `ifdef CFG_INTERRUPTS_ENABLED
  1723                             || (   (interrupt_exception == `TRUE)
  1724 `ifdef LM32_SINGLE_STEP_ENABLED
  1725                                 && (dc_ss == `FALSE)
  1726 `endif                            
  1727 `ifdef CFG_BUS_ERRORS_ENABLED
  1728  				&& (store_q_m == `FALSE)
  1729 				&& (D_CYC_O == `FALSE)
  1730 `endif
  1732 `endif
  1735 assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
  1736 `else
  1737 assign exception_x =           (system_call_exception == `TRUE)
  1738 `ifdef CFG_BUS_ERRORS_ENABLED
  1739                             || (instruction_bus_error_exception == `TRUE)
  1740                             || (data_bus_error_exception == `TRUE)
  1741 `endif
  1742 `ifdef CFG_MC_DIVIDE_ENABLED
  1743                             || (divide_by_zero_exception == `TRUE)
  1744 `endif
  1745 `ifdef CFG_INTERRUPTS_ENABLED
  1746                             || (   (interrupt_exception == `TRUE)
  1747 `ifdef LM32_SINGLE_STEP_ENABLED
  1748                                 && (dc_ss == `FALSE)
  1749 `endif                            
  1750 `ifdef CFG_BUS_ERRORS_ENABLED
  1751  				&& (store_q_m == `FALSE)
  1752 				&& (D_CYC_O == `FALSE)
  1753 `endif
  1755 `endif
  1757 `endif
  1759 // Exception ID
  1760 always @(*)
  1761 begin
  1762 `ifdef CFG_DEBUG_ENABLED
  1763 `ifdef CFG_JTAG_ENABLED
  1764     if (reset_exception == `TRUE)
  1765         eid_x = `LM32_EID_RESET;
  1766     else
  1767 `endif     
  1768 `ifdef CFG_BUS_ERRORS_ENABLED
  1769          if (data_bus_error_exception == `TRUE)
  1770         eid_x = `LM32_EID_DATA_BUS_ERROR;
  1771     else
  1772 `endif
  1773          if (breakpoint_exception == `TRUE)
  1774         eid_x = `LM32_EID_BREAKPOINT;
  1775     else
  1776 `endif
  1777 `ifdef CFG_BUS_ERRORS_ENABLED
  1778          if (data_bus_error_exception == `TRUE)
  1779         eid_x = `LM32_EID_DATA_BUS_ERROR;
  1780     else
  1781          if (instruction_bus_error_exception == `TRUE)
  1782         eid_x = `LM32_EID_INST_BUS_ERROR;
  1783     else
  1784 `endif
  1785 `ifdef CFG_DEBUG_ENABLED
  1786          if (watchpoint_exception == `TRUE)
  1787         eid_x = `LM32_EID_WATCHPOINT;
  1788     else 
  1789 `endif
  1790 `ifdef CFG_MC_DIVIDE_ENABLED
  1791          if (divide_by_zero_exception == `TRUE)
  1792         eid_x = `LM32_EID_DIVIDE_BY_ZERO;
  1793     else
  1794 `endif
  1795 `ifdef CFG_INTERRUPTS_ENABLED
  1796          if (   (interrupt_exception == `TRUE)
  1797 `ifdef LM32_SINGLE_STEP_ENABLED
  1798              && (dc_ss == `FALSE)
  1799 `endif                            
  1801         eid_x = `LM32_EID_INTERRUPT;
  1802     else
  1803 `endif
  1804         eid_x = `LM32_EID_SCALL;
  1805 end
  1807 // Stall generation
  1809 assign stall_a = (stall_f == `TRUE);
  1811 assign stall_f = (stall_d == `TRUE);
  1813 assign stall_d =   (stall_x == `TRUE) 
  1814                 || (   (interlock == `TRUE)
  1815                     && (kill_d == `FALSE)
  1817 		|| (   (   (eret_d == `TRUE)
  1818 			|| (scall_d == `TRUE)
  1819 			|| (bus_error_d == `TRUE)
  1821 		    && (   (load_q_x == `TRUE)
  1822 			|| (load_q_m == `TRUE)
  1823 			|| (store_q_x == `TRUE)
  1824 			|| (store_q_m == `TRUE)
  1825 			|| (D_CYC_O == `TRUE)
  1827                     && (kill_d == `FALSE)
  1829 `ifdef CFG_DEBUG_ENABLED
  1830 		|| (   (   (break_d == `TRUE)
  1831 			|| (bret_d == `TRUE)
  1833 		    && (   (load_q_x == `TRUE)
  1834 			|| (store_q_x == `TRUE)
  1835 			|| (load_q_m == `TRUE)
  1836 			|| (store_q_m == `TRUE)
  1837 			|| (D_CYC_O == `TRUE)
  1839                     && (kill_d == `FALSE)
  1841 `endif                   
  1842                 || (   (csr_write_enable_d == `TRUE)
  1843                     && (load_q_x == `TRUE)
  1847 assign stall_x =    (stall_m == `TRUE)
  1848 `ifdef LM32_MC_ARITHMETIC_ENABLED
  1849                  || (   (mc_stall_request_x == `TRUE)
  1850                      && (kill_x == `FALSE)
  1852 `endif
  1853 `ifdef CFG_IROM_ENABLED
  1854                  // Stall load/store instruction in D stage if there is an ongoing store
  1855                  // operation to instruction ROM in M stage
  1856                  || (   (irom_stall_request_x == `TRUE)
  1857 		     && (   (load_d == `TRUE)
  1858 			 || (store_d == `TRUE)
  1861 `endif
  1864 assign stall_m =    (stall_wb_load == `TRUE)
  1865 `ifdef CFG_SIZE_OVER_SPEED
  1866                  || (D_CYC_O == `TRUE)
  1867 `else
  1868                  || (   (D_CYC_O == `TRUE)
  1869                      && (   (store_m == `TRUE)
  1870 		         /*
  1871 			  Bug: Following loop does not allow interrupts to be services since
  1872 			  either D_CYC_O or store_m is always high during entire duration of
  1873 			  loop.
  1874 		          L1:	addi	r1, r1, 1
  1875 			  	sw	(r2,0), r1
  1876 			  	bi	L1
  1878 			  Introduce a single-cycle stall when a wishbone cycle is in progress
  1879 			  and a new store instruction is in Execute stage and a interrupt
  1880 			  exception has occured. This stall will ensure that D_CYC_O and 
  1881 			  store_m will both be low for one cycle.
  1882 			  */
  1883 		         || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
  1884                          || (load_m == `TRUE)
  1885                          || (load_x == `TRUE)
  1888 `endif                 
  1889 `ifdef CFG_DCACHE_ENABLED
  1890                  || (dcache_stall_request == `TRUE)     // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
  1891 `endif                                    
  1892 `ifdef CFG_ICACHE_ENABLED
  1893                  || (icache_stall_request == `TRUE)     // Pipeline needs to be stalled otherwise branches may be lost
  1894                  || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) 
  1895 `else
  1896 `ifdef CFG_IWB_ENABLED
  1897                  || (I_CYC_O == `TRUE)            
  1898 `endif
  1899 `endif                               
  1900 `ifdef CFG_USER_ENABLED
  1901                  || (   (user_valid == `TRUE)           // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
  1902                      && (user_complete == `FALSE)
  1904 `endif
  1907 // Qualify state changing control signals
  1908 `ifdef LM32_MC_ARITHMETIC_ENABLED
  1909 assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
  1910 `endif
  1911 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
  1912 assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
  1913 assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
  1914 `endif
  1915 `ifdef CFG_MC_MULTIPLY_ENABLED
  1916 assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
  1917 `endif
  1918 `ifdef CFG_MC_DIVIDE_ENABLED
  1919 assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
  1920 assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
  1921 `endif
  1922 assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
  1923 assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
  1924 assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
  1925 `ifdef CFG_DEBUG_ENABLED
  1926 assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
  1927 `endif
  1928 assign load_q_x = (load_x == `TRUE) 
  1929                && (q_x == `TRUE)
  1930 `ifdef CFG_DEBUG_ENABLED
  1931                && (bp_match == `FALSE)
  1932 `endif
  1934 assign store_q_x = (store_x == `TRUE) 
  1935                && (q_x == `TRUE)
  1936 `ifdef CFG_DEBUG_ENABLED
  1937                && (bp_match == `FALSE)
  1938 `endif
  1940 `ifdef CFG_USER_ENABLED
  1941 assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
  1942 `endif                              
  1943 assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
  1944 assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
  1945 assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
  1946 `ifdef CFG_DEBUG_ENABLED
  1947 assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
  1948 assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));        
  1949 `else
  1950 assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));        
  1951 `endif
  1952 // Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
  1953 assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
  1954 assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
  1955 assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
  1956 // The enable that actually does write the registers needs to be qualified with kill
  1957 assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
  1959 // Configuration (CFG) CSR
  1960 assign cfg = {
  1961               `LM32_REVISION,
  1962               watchpoints[3:0],
  1963               breakpoints[3:0],
  1964               interrupts[5:0],
  1965 `ifdef CFG_JTAG_UART_ENABLED
  1966               `TRUE,
  1967 `else
  1968               `FALSE,
  1969 `endif
  1970 `ifdef CFG_ROM_DEBUG_ENABLED
  1971               `TRUE,
  1972 `else
  1973               `FALSE,
  1974 `endif
  1975 `ifdef CFG_HW_DEBUG_ENABLED
  1976               `TRUE,
  1977 `else
  1978               `FALSE,
  1979 `endif
  1980 `ifdef CFG_DEBUG_ENABLED
  1981               `TRUE,
  1982 `else
  1983               `FALSE,
  1984 `endif
  1985 `ifdef CFG_ICACHE_ENABLED
  1986               `TRUE,
  1987 `else
  1988               `FALSE,
  1989 `endif
  1990 `ifdef CFG_DCACHE_ENABLED
  1991               `TRUE,
  1992 `else
  1993               `FALSE,
  1994 `endif
  1995 `ifdef CFG_CYCLE_COUNTER_ENABLED
  1996               `TRUE,
  1997 `else
  1998               `FALSE,
  1999 `endif
  2000 `ifdef CFG_USER_ENABLED
  2001               `TRUE,
  2002 `else
  2003               `FALSE,
  2004 `endif
  2005 `ifdef CFG_SIGN_EXTEND_ENABLED
  2006               `TRUE,
  2007 `else
  2008               `FALSE,
  2009 `endif
  2010 `ifdef LM32_BARREL_SHIFT_ENABLED
  2011               `TRUE,
  2012 `else
  2013               `FALSE,
  2014 `endif
  2015 `ifdef CFG_MC_DIVIDE_ENABLED
  2016               `TRUE,
  2017 `else
  2018               `FALSE,
  2019 `endif
  2020 `ifdef LM32_MULTIPLY_ENABLED 
  2021               `TRUE
  2022 `else
  2023               `FALSE
  2024 `endif
  2025               };
  2027 assign cfg2 = {
  2028 		     30'b0,
  2029 `ifdef CFG_IROM_ENABLED
  2030 		     `TRUE,
  2031 `else
  2032 		     `FALSE,
  2033 `endif
  2034 `ifdef CFG_DRAM_ENABLED
  2035 		     `TRUE
  2036 `else
  2037 		     `FALSE
  2038 `endif
  2039 		     };
  2041 // Cache flush
  2042 `ifdef CFG_ICACHE_ENABLED
  2043 assign iflush =    (csr_write_enable_d == `TRUE) 
  2044                 && (csr_d == `LM32_CSR_ICC)
  2045                 && (stall_d == `FALSE)
  2046                 && (kill_d == `FALSE)
  2047                 && (valid_d == `TRUE);
  2048 `endif 
  2049 `ifdef CFG_DCACHE_ENABLED
  2050 assign dflush_x =  (csr_write_enable_q_x == `TRUE) 
  2051                 && (csr_x == `LM32_CSR_DCC);
  2052 `endif 
  2054 // Extract CSR index
  2055 assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
  2057 // CSR reads
  2058 always @(*)
  2059 begin
  2060     case (csr_x)
  2061 `ifdef CFG_INTERRUPTS_ENABLED
  2062     `LM32_CSR_IE,
  2063     `LM32_CSR_IM,
  2064     `LM32_CSR_IP:   csr_read_data_x = interrupt_csr_read_data_x;  
  2065 `endif
  2066 `ifdef CFG_CYCLE_COUNTER_ENABLED
  2067     `LM32_CSR_CC:   csr_read_data_x = cc;
  2068 `endif
  2069     `LM32_CSR_CFG:  csr_read_data_x = cfg;
  2070     `LM32_CSR_EBA:  csr_read_data_x = {eba, 8'h00};
  2071 `ifdef CFG_DEBUG_ENABLED
  2072     `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
  2073 `endif
  2074 `ifdef CFG_JTAG_UART_ENABLED
  2075     `LM32_CSR_JTX:  csr_read_data_x = jtx_csr_read_data;  
  2076     `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
  2077 `endif
  2078     `LM32_CSR_CFG2: csr_read_data_x = cfg2;
  2080     default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
  2081     endcase
  2082 end
  2084 /////////////////////////////////////////////////////
  2085 // Sequential Logic
  2086 /////////////////////////////////////////////////////
  2088 // Exception Base Address (EBA) CSR
  2089 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2090 begin
  2091     if (rst_i == `TRUE)
  2092         eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
  2093     else
  2094     begin
  2095         if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
  2096             eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
  2097 `ifdef CFG_HW_DEBUG_ENABLED
  2098         if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
  2099             eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
  2100 `endif
  2101     end
  2102 end
  2104 `ifdef CFG_DEBUG_ENABLED
  2105 // Debug Exception Base Address (DEBA) CSR
  2106 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2107 begin
  2108     if (rst_i == `TRUE)
  2109         deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
  2110     else
  2111     begin
  2112         if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
  2113             deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
  2114 `ifdef CFG_HW_DEBUG_ENABLED
  2115         if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
  2116             deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
  2117 `endif
  2118     end
  2119 end
  2120 `endif
  2122 // Cycle Counter (CC) CSR
  2123 `ifdef CFG_CYCLE_COUNTER_ENABLED
  2124 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2125 begin
  2126     if (rst_i == `TRUE)
  2127         cc <= {`LM32_WORD_WIDTH{1'b0}};
  2128     else
  2129         cc <= cc + 1'b1;
  2130 end
  2131 `endif
  2133 `ifdef CFG_BUS_ERRORS_ENABLED
  2134 // Watch for data bus errors
  2135 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2136 begin
  2137     if (rst_i == `TRUE)
  2138         data_bus_error_seen <= `FALSE;
  2139     else
  2140     begin
  2141         // Set flag when bus error is detected
  2142         if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
  2143             data_bus_error_seen <= `TRUE;
  2144         // Clear flag when exception is taken
  2145         if ((exception_m == `TRUE) && (kill_m == `FALSE))
  2146             data_bus_error_seen <= `FALSE;
  2147     end
  2148 end
  2149 `endif
  2151 // Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not  
  2153 `ifdef CFG_ICACHE_ENABLED
  2154 `ifdef CFG_DCACHE_ENABLED
  2155 always @(*)
  2156 begin
  2157     if (   (icache_refill_request == `TRUE) 
  2158         || (dcache_refill_request == `TRUE)
  2160         valid_a = `FALSE;
  2161     else if (   (icache_restart_request == `TRUE) 
  2162              || (dcache_restart_request == `TRUE) 
  2164         valid_a = `TRUE;
  2165     else 
  2166         valid_a = !icache_refilling && !dcache_refilling;
  2167 end 
  2168 `else
  2169 always @(*)
  2170 begin
  2171     if (icache_refill_request == `TRUE) 
  2172         valid_a = `FALSE;
  2173     else if (icache_restart_request == `TRUE) 
  2174         valid_a = `TRUE;
  2175     else 
  2176         valid_a = !icache_refilling;
  2177 end 
  2178 `endif
  2179 `else
  2180 `ifdef CFG_DCACHE_ENABLED
  2181 always @(*)
  2182 begin
  2183     if (dcache_refill_request == `TRUE) 
  2184         valid_a = `FALSE;
  2185     else if (dcache_restart_request == `TRUE) 
  2186         valid_a = `TRUE;
  2187     else 
  2188         valid_a = !dcache_refilling;
  2189 end 
  2190 `endif
  2191 `endif
  2193 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2194 begin
  2195     if (rst_i == `TRUE)
  2196     begin
  2197         valid_f <= `FALSE;
  2198         valid_d <= `FALSE;
  2199         valid_x <= `FALSE;
  2200         valid_m <= `FALSE;
  2201         valid_w <= `FALSE;
  2202     end
  2203     else
  2204     begin    
  2205         if ((kill_f == `TRUE) || (stall_a == `FALSE))
  2206 `ifdef LM32_CACHE_ENABLED
  2207             valid_f <= valid_a;    
  2208 `else
  2209             valid_f <= `TRUE;
  2210 `endif            
  2211         else if (stall_f == `FALSE)
  2212             valid_f <= `FALSE;            
  2214         if (kill_d == `TRUE)
  2215             valid_d <= `FALSE;
  2216         else if (stall_f == `FALSE)
  2217             valid_d <= valid_f & !kill_f;
  2218         else if (stall_d == `FALSE)
  2219             valid_d <= `FALSE;
  2221         if (stall_d == `FALSE)
  2222             valid_x <= valid_d & !kill_d;
  2223         else if (kill_x == `TRUE)
  2224             valid_x <= `FALSE;
  2225         else if (stall_x == `FALSE)
  2226             valid_x <= `FALSE;
  2228         if (kill_m == `TRUE)
  2229             valid_m <= `FALSE;
  2230         else if (stall_x == `FALSE)
  2231             valid_m <= valid_x & !kill_x;
  2232         else if (stall_m == `FALSE)
  2233             valid_m <= `FALSE;
  2235         if (stall_m == `FALSE)
  2236             valid_w <= valid_m & !kill_m;
  2237         else 
  2238             valid_w <= `FALSE;        
  2239     end
  2240 end
  2242 // Microcode pipeline registers
  2243 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2244 begin
  2245     if (rst_i == `TRUE)
  2246     begin
  2247 `ifdef CFG_USER_ENABLED
  2248         user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};       
  2249 `endif        
  2250         operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
  2251         operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
  2252         store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
  2253         branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};        
  2254         x_result_sel_csr_x <= `FALSE;
  2255 `ifdef LM32_MC_ARITHMETIC_ENABLED
  2256         x_result_sel_mc_arith_x <= `FALSE;
  2257 `endif
  2258 `ifdef LM32_NO_BARREL_SHIFT    
  2259         x_result_sel_shift_x <= `FALSE;
  2260 `endif
  2261 `ifdef CFG_SIGN_EXTEND_ENABLED
  2262         x_result_sel_sext_x <= `FALSE;
  2263 `endif  
  2264 	x_result_sel_logic_x <= `FALSE;
  2265 `ifdef CFG_USER_ENABLED
  2266         x_result_sel_user_x <= `FALSE;
  2267 `endif
  2268         x_result_sel_add_x <= `FALSE;
  2269         m_result_sel_compare_x <= `FALSE;
  2270 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2271         m_result_sel_shift_x <= `FALSE;
  2272 `endif    
  2273         w_result_sel_load_x <= `FALSE;
  2274 `ifdef CFG_PL_MULTIPLY_ENABLED
  2275         w_result_sel_mul_x <= `FALSE;
  2276 `endif
  2277         x_bypass_enable_x <= `FALSE;
  2278         m_bypass_enable_x <= `FALSE;
  2279         write_enable_x <= `FALSE;
  2280         write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
  2281         csr_x <= {`LM32_CSR_WIDTH{1'b0}};
  2282         load_x <= `FALSE;
  2283         store_x <= `FALSE;
  2284         size_x <= {`LM32_SIZE_WIDTH{1'b0}};
  2285         sign_extend_x <= `FALSE;
  2286         adder_op_x <= `FALSE;
  2287         adder_op_x_n <= `FALSE;
  2288         logic_op_x <= 4'h0;
  2289 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2290         direction_x <= `FALSE;
  2291 `endif
  2292 `ifdef CFG_ROTATE_ENABLED
  2293         rotate_x <= `FALSE;
  2295 `endif
  2296         branch_x <= `FALSE;
  2297         branch_predict_x <= `FALSE;
  2298         branch_predict_taken_x <= `FALSE;
  2299         condition_x <= `LM32_CONDITION_U1;
  2300 `ifdef CFG_DEBUG_ENABLED
  2301         break_x <= `FALSE;
  2302 `endif
  2303         scall_x <= `FALSE;
  2304         eret_x <= `FALSE;
  2305 `ifdef CFG_DEBUG_ENABLED
  2306         bret_x <= `FALSE;
  2307 `endif
  2308 `ifdef CFG_BUS_ERRORS_ENABLED
  2309         bus_error_x <= `FALSE;
  2310         data_bus_error_exception_m <= `FALSE;
  2311 `endif
  2312         csr_write_enable_x <= `FALSE;
  2313         operand_m <= {`LM32_WORD_WIDTH{1'b0}};
  2314         branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
  2315         m_result_sel_compare_m <= `FALSE;
  2316 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2317         m_result_sel_shift_m <= `FALSE;
  2318 `endif    
  2319         w_result_sel_load_m <= `FALSE;
  2320 `ifdef CFG_PL_MULTIPLY_ENABLED
  2321         w_result_sel_mul_m <= `FALSE;
  2322 `endif
  2323         m_bypass_enable_m <= `FALSE;
  2324         branch_m <= `FALSE;
  2325         branch_predict_m <= `FALSE;
  2326 	branch_predict_taken_m <= `FALSE;
  2327         exception_m <= `FALSE;
  2328         load_m <= `FALSE;
  2329         store_m <= `FALSE;
  2330         write_enable_m <= `FALSE;            
  2331         write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
  2332         condition_met_m <= `FALSE;
  2333 `ifdef CFG_DCACHE_ENABLED
  2334         dflush_m <= `FALSE;
  2335 `endif
  2336 `ifdef CFG_DEBUG_ENABLED
  2337         debug_exception_m <= `FALSE;
  2338         non_debug_exception_m <= `FALSE;        
  2339 `endif
  2340         operand_w <= {`LM32_WORD_WIDTH{1'b0}};        
  2341         w_result_sel_load_w <= `FALSE;
  2342 `ifdef CFG_PL_MULTIPLY_ENABLED
  2343         w_result_sel_mul_w <= `FALSE;
  2344 `endif
  2345         write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};        
  2346         write_enable_w <= `FALSE;
  2347 `ifdef CFG_DEBUG_ENABLED
  2348         debug_exception_w <= `FALSE;
  2349         non_debug_exception_w <= `FALSE;        
  2350 `else
  2351         exception_w <= `FALSE;
  2352 `endif
  2353 `ifdef CFG_BUS_ERRORS_ENABLED
  2354         memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
  2355 `endif
  2356     end
  2357     else
  2358     begin
  2359         // D/X stage registers
  2361         if (stall_x == `FALSE)
  2362         begin
  2363 `ifdef CFG_USER_ENABLED
  2364             user_opcode <= user_opcode_d;       
  2365 `endif        
  2366             operand_0_x <= d_result_0;
  2367             operand_1_x <= d_result_1;
  2368             store_operand_x <= bypass_data_1;
  2369             branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;            
  2370             x_result_sel_csr_x <= x_result_sel_csr_d;
  2371 `ifdef LM32_MC_ARITHMETIC_ENABLED
  2372             x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
  2373 `endif
  2374 `ifdef LM32_NO_BARREL_SHIFT    
  2375             x_result_sel_shift_x <= x_result_sel_shift_d;
  2376 `endif
  2377 `ifdef CFG_SIGN_EXTEND_ENABLED
  2378             x_result_sel_sext_x <= x_result_sel_sext_d;
  2379 `endif    
  2380 	    x_result_sel_logic_x <= x_result_sel_logic_d;
  2381 `ifdef CFG_USER_ENABLED
  2382             x_result_sel_user_x <= x_result_sel_user_d;
  2383 `endif
  2384             x_result_sel_add_x <= x_result_sel_add_d;
  2385             m_result_sel_compare_x <= m_result_sel_compare_d;
  2386 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2387             m_result_sel_shift_x <= m_result_sel_shift_d;
  2388 `endif    
  2389             w_result_sel_load_x <= w_result_sel_load_d;
  2390 `ifdef CFG_PL_MULTIPLY_ENABLED
  2391             w_result_sel_mul_x <= w_result_sel_mul_d;
  2392 `endif
  2393             x_bypass_enable_x <= x_bypass_enable_d;
  2394             m_bypass_enable_x <= m_bypass_enable_d;
  2395             load_x <= load_d;
  2396             store_x <= store_d;
  2397             branch_x <= branch_d;
  2398 	    branch_predict_x <= branch_predict_d;
  2399 	    branch_predict_taken_x <= branch_predict_taken_d;
  2400 	    write_idx_x <= write_idx_d;
  2401             csr_x <= csr_d;
  2402             size_x <= size_d;
  2403             sign_extend_x <= sign_extend_d;
  2404             adder_op_x <= adder_op_d;
  2405             adder_op_x_n <= ~adder_op_d;
  2406             logic_op_x <= logic_op_d;
  2407 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2408             direction_x <= direction_d;
  2409 `endif
  2410 `ifdef CFG_ROTATE_ENABLED
  2411             rotate_x <= rotate_d;
  2412 `endif
  2413             condition_x <= condition_d;
  2414             csr_write_enable_x <= csr_write_enable_d;
  2415 `ifdef CFG_DEBUG_ENABLED
  2416             break_x <= break_d;
  2417 `endif
  2418             scall_x <= scall_d;
  2419 `ifdef CFG_BUS_ERRORS_ENABLED
  2420             bus_error_x <= bus_error_d;
  2421 `endif
  2422             eret_x <= eret_d;
  2423 `ifdef CFG_DEBUG_ENABLED
  2424             bret_x <= bret_d; 
  2425 `endif
  2426             write_enable_x <= write_enable_d;
  2427         end
  2429         // X/M stage registers
  2431         if (stall_m == `FALSE)
  2432         begin
  2433             operand_m <= x_result;
  2434             m_result_sel_compare_m <= m_result_sel_compare_x;
  2435 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2436             m_result_sel_shift_m <= m_result_sel_shift_x;
  2437 `endif    
  2438             if (exception_x == `TRUE)
  2439             begin
  2440                 w_result_sel_load_m <= `FALSE;
  2441 `ifdef CFG_PL_MULTIPLY_ENABLED
  2442                 w_result_sel_mul_m <= `FALSE;
  2443 `endif
  2444             end
  2445             else
  2446             begin
  2447                 w_result_sel_load_m <= w_result_sel_load_x;
  2448 `ifdef CFG_PL_MULTIPLY_ENABLED
  2449                 w_result_sel_mul_m <= w_result_sel_mul_x;
  2450 `endif
  2451             end
  2452             m_bypass_enable_m <= m_bypass_enable_x;
  2453 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2454 `endif
  2455             load_m <= load_x;
  2456             store_m <= store_x;
  2457 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  2458             branch_m <= branch_x && !branch_taken_x;
  2459 `else
  2460             branch_m <= branch_x;
  2461 	    branch_predict_m <= branch_predict_x;
  2462 	    branch_predict_taken_m <= branch_predict_taken_x;
  2463 `endif
  2464 `ifdef CFG_DEBUG_ENABLED
  2465 	   // Data bus errors are generated by the wishbone and are
  2466 	   // made known to the processor only in next cycle (as a
  2467 	   // non-debug exception). A break instruction can be seen
  2468 	   // in same cycle (causing a debug exception). Handle non
  2469 	   // -debug exception first!
  2470             if (non_debug_exception_x == `TRUE) 
  2471                 write_idx_m <= `LM32_EA_REG;
  2472             else if (debug_exception_x == `TRUE)
  2473                 write_idx_m <= `LM32_BA_REG;
  2474             else 
  2475                 write_idx_m <= write_idx_x;
  2476 `else
  2477             if (exception_x == `TRUE)
  2478                 write_idx_m <= `LM32_EA_REG;
  2479             else 
  2480                 write_idx_m <= write_idx_x;
  2481 `endif
  2482             condition_met_m <= condition_met_x;
  2483 `ifdef CFG_DEBUG_ENABLED
  2484 	   if (exception_x == `TRUE)
  2485 	     if ((dc_re == `TRUE)
  2486 		 || ((debug_exception_x == `TRUE) 
  2487 		     && (non_debug_exception_x == `FALSE)))
  2488 	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
  2489 	     else
  2490 	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
  2491 	   else
  2492 	     branch_target_m <= branch_target_x;
  2493 `else
  2494             branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
  2495 `endif
  2496 `ifdef CFG_TRACE_ENABLED
  2497             eid_m <= eid_x;
  2498 `endif
  2499 `ifdef CFG_DCACHE_ENABLED
  2500             dflush_m <= dflush_x;
  2501 `endif
  2502             eret_m <= eret_q_x;
  2503 `ifdef CFG_DEBUG_ENABLED
  2504             bret_m <= bret_q_x; 
  2505 `endif
  2506             write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;            
  2507 `ifdef CFG_DEBUG_ENABLED
  2508             debug_exception_m <= debug_exception_x;
  2509             non_debug_exception_m <= non_debug_exception_x;        
  2510 `endif
  2511         end
  2513         // State changing regs
  2514         if (stall_m == `FALSE)
  2515         begin
  2516             if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
  2517                 exception_m <= `TRUE;
  2518             else 
  2519                 exception_m <= `FALSE;
  2520 `ifdef CFG_BUS_ERRORS_ENABLED
  2521 	   data_bus_error_exception_m <=    (data_bus_error_exception == `TRUE) 
  2522 `ifdef CFG_DEBUG_ENABLED
  2523 					 && (reset_exception == `FALSE)
  2524 `endif
  2526 `endif
  2527 	end
  2529         // M/W stage registers
  2530 `ifdef CFG_BUS_ERRORS_ENABLED
  2531         operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
  2532 `else
  2533         operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
  2534 `endif
  2535         w_result_sel_load_w <= w_result_sel_load_m;
  2536 `ifdef CFG_PL_MULTIPLY_ENABLED
  2537         w_result_sel_mul_w <= w_result_sel_mul_m;
  2538 `endif
  2539         write_idx_w <= write_idx_m;
  2540 `ifdef CFG_TRACE_ENABLED
  2541         eid_w <= eid_m;
  2542         eret_w <= eret_m;
  2543 `ifdef CFG_DEBUG_ENABLED
  2544         bret_w <= bret_m; 
  2545 `endif
  2546 `endif
  2547         write_enable_w <= write_enable_m;
  2548 `ifdef CFG_DEBUG_ENABLED
  2549         debug_exception_w <= debug_exception_m;
  2550         non_debug_exception_w <= non_debug_exception_m;
  2551 `else
  2552         exception_w <= exception_m;
  2553 `endif
  2554 `ifdef CFG_BUS_ERRORS_ENABLED
  2555         if (   (stall_m == `FALSE)
  2556             && (   (load_q_m == `TRUE) 
  2557                 || (store_q_m == `TRUE)
  2560           memop_pc_w <= pc_m;
  2561 `endif
  2562     end
  2563 end
  2565 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  2566 // Buffer data read from register file, in case a stall occurs, and watch for
  2567 // any writes to the modified registers
  2568 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2569 begin
  2570     if (rst_i == `TRUE)
  2571     begin
  2572         use_buf <= `FALSE;
  2573         reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
  2574         reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
  2575     end
  2576     else
  2577     begin
  2578         if (stall_d == `FALSE)
  2579             use_buf <= `FALSE;
  2580         else if (use_buf == `FALSE)
  2581         begin        
  2582             reg_data_buf_0 <= reg_data_live_0;
  2583             reg_data_buf_1 <= reg_data_live_1;
  2584             use_buf <= `TRUE;
  2585         end        
  2586         if (reg_write_enable_q_w == `TRUE)
  2587         begin
  2588             if (write_idx_w == read_idx_0_d)
  2589                 reg_data_buf_0 <= w_result;
  2590             if (write_idx_w == read_idx_1_d)
  2591                 reg_data_buf_1 <= w_result;
  2592         end
  2593     end
  2594 end
  2595 `endif
  2597 `ifdef LM32_EBR_REGISTER_FILE
  2598 `else
  2599 // Register file write port
  2600 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2601 begin
  2602     if (rst_i == `TRUE) begin
  2603         registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
  2604         registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
  2605         registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
  2606         registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
  2607         registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
  2608         registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
  2609         registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
  2610         registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
  2611         registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
  2612         registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
  2613         registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
  2614         registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
  2615         registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
  2616         registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
  2617         registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
  2618         registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
  2619         registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
  2620         registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
  2621         registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
  2622         registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
  2623         registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
  2624         registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
  2625         registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
  2626         registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
  2627         registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
  2628         registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
  2629         registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
  2630         registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
  2631         registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
  2632         registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
  2633         registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
  2634         registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 
  2635         end
  2636     else begin
  2637         if (reg_write_enable_q_w == `TRUE)
  2638           registers[write_idx_w] <= w_result;
  2639         end
  2640 end
  2641 `endif
  2643 `ifdef CFG_TRACE_ENABLED
  2644 // PC tracing logic
  2645 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2646 begin
  2647     if (rst_i == `TRUE)
  2648     begin
  2649         trace_pc_valid <= `FALSE;
  2650         trace_pc <= {`LM32_PC_WIDTH{1'b0}};
  2651         trace_exception <= `FALSE;
  2652         trace_eid <= `LM32_EID_RESET;
  2653         trace_eret <= `FALSE;
  2654 `ifdef CFG_DEBUG_ENABLED
  2655         trace_bret <= `FALSE;
  2656 `endif
  2657         pc_c <= `CFG_EBA_RESET/4;
  2658     end
  2659     else
  2660     begin
  2661         trace_pc_valid <= `FALSE;
  2662         // Has an exception occured
  2663 `ifdef CFG_DEBUG_ENABLED
  2664         if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
  2665 `else
  2666         if (exception_q_w == `TRUE)
  2667 `endif
  2668         begin        
  2669             trace_exception <= `TRUE;
  2670             trace_pc_valid <= `TRUE;
  2671             trace_pc <= pc_w;
  2672             trace_eid <= eid_w;
  2673         end
  2674         else
  2675             trace_exception <= `FALSE;
  2677         if ((valid_w == `TRUE) && (!kill_w))
  2678         begin
  2679             // An instruction is commiting. Determine if it is non-sequential
  2680             if (pc_c + 1'b1 != pc_w)
  2681             begin
  2682                 // Non-sequential instruction
  2683                 trace_pc_valid <= `TRUE;
  2684                 trace_pc <= pc_w;
  2685             end
  2686             // Record PC so we can determine if next instruction is sequential or not
  2687             pc_c <= pc_w;
  2688             // Indicate if it was an eret/bret instruction
  2689             trace_eret <= eret_w;
  2690 `ifdef CFG_DEBUG_ENABLED
  2691             trace_bret <= bret_w;
  2692 `endif
  2693         end
  2694         else
  2695         begin
  2696             trace_eret <= `FALSE;
  2697 `ifdef CFG_DEBUG_ENABLED
  2698             trace_bret <= `FALSE;
  2699 `endif
  2700         end
  2701     end
  2702 end
  2703 `endif
  2705 /////////////////////////////////////////////////////
  2706 // Behavioural Logic
  2707 /////////////////////////////////////////////////////
  2709 // synthesis translate_off            
  2711 // Reset register 0. Only needed for simulation. 
  2712 initial
  2713 begin
  2714 `ifdef LM32_EBR_REGISTER_FILE
  2715     reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
  2716     reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
  2717 `else
  2718     registers[0] = {`LM32_WORD_WIDTH{1'b0}};
  2719 `endif
  2720 end
  2722 // synthesis translate_on
  2724 endmodule