Fri, 13 Aug 2010 01:13:04 +0100
[UPSTREAM PULL] update baseline to LatticeMico32 v3.5 and add documentation
Update baseline head to LatticeMico32 v3.5, from "LatticeMico32 System for
ispLEVER on Linux" v8.1 (Jun 2010). Downloaded from:
http://www.latticesemi.com/dynamic/index.cfm?fuseaction=view_documents&document_type=65&sloc=01-01-08-11-48&source=sidebar
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_instruction_unit.v
19 // Title : Instruction unit
20 // Dependencies : lm32_include.v
21 // Version : 6.1.17
22 // : Initial Release
23 // Version : 7.0SP2, 3.0
24 // : No Change
25 // Version : 3.1
26 // : Support for static branch prediction is added. Fetching of
27 // : instructions can also be altered by branches predicted in D
28 // : stage of pipeline, and mispredicted branches in the X and M
29 // : stages of the pipeline.
30 // Version : 3.2
31 // : EBRs use SYNC resets instead of ASYNC resets.
32 // Version : 3.3
33 // : Support for a non-cacheable Instruction Memory that has a
34 // : single-cycle access latency. This memory can be accessed by
35 // : data port of LM32 (so that debugger has access to it).
36 // Version : 3.4
37 // : No change
38 // Version : 3.5
39 // : Bug fix: Inline memory is correctly generated if it is not a
40 // : power-of-two.
41 // : Bug fix: Fixed a bug that caused LM32 (configured without
42 // : instruction cache) to lock up in to an infinite loop due to a
43 // : instruction bus error when EBA was set to instruction inline
44 // : memory.
45 // =============================================================================
47 `include "lm32_include.v"
49 /////////////////////////////////////////////////////
50 // Module interface
51 /////////////////////////////////////////////////////
53 module lm32_instruction_unit (
54 // ----- Inputs -------
55 clk_i,
56 rst_i,
57 // From pipeline
58 stall_a,
59 stall_f,
60 stall_d,
61 stall_x,
62 stall_m,
63 valid_f,
64 valid_d,
65 kill_f,
66 branch_predict_taken_d,
67 branch_predict_address_d,
68 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
69 branch_taken_x,
70 branch_target_x,
71 `endif
72 exception_m,
73 branch_taken_m,
74 branch_mispredict_taken_m,
75 branch_target_m,
76 `ifdef CFG_ICACHE_ENABLED
77 iflush,
78 `endif
79 `ifdef CFG_DCACHE_ENABLED
80 dcache_restart_request,
81 dcache_refill_request,
82 dcache_refilling,
83 `endif
84 `ifdef CFG_IROM_ENABLED
85 irom_store_data_m,
86 irom_address_xm,
87 irom_we_xm,
88 `endif
89 `ifdef CFG_IWB_ENABLED
90 // From Wishbone
91 i_dat_i,
92 i_ack_i,
93 i_err_i,
94 `endif
95 `ifdef CFG_HW_DEBUG_ENABLED
96 jtag_read_enable,
97 jtag_write_enable,
98 jtag_write_data,
99 jtag_address,
100 `endif
101 // ----- Outputs -------
102 // To pipeline
103 pc_f,
104 pc_d,
105 pc_x,
106 pc_m,
107 pc_w,
108 `ifdef CFG_ICACHE_ENABLED
109 icache_stall_request,
110 icache_restart_request,
111 icache_refill_request,
112 icache_refilling,
113 `endif
114 `ifdef CFG_IROM_ENABLED
115 irom_data_m,
116 `endif
117 `ifdef CFG_IWB_ENABLED
118 // To Wishbone
119 i_dat_o,
120 i_adr_o,
121 i_cyc_o,
122 i_sel_o,
123 i_stb_o,
124 i_we_o,
125 i_cti_o,
126 i_lock_o,
127 i_bte_o,
128 `endif
129 `ifdef CFG_HW_DEBUG_ENABLED
130 jtag_read_data,
131 jtag_access_complete,
132 `endif
133 `ifdef CFG_BUS_ERRORS_ENABLED
134 bus_error_d,
135 `endif
136 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
137 instruction_f,
138 `endif
139 instruction_d
140 );
142 /////////////////////////////////////////////////////
143 // Parameters
144 /////////////////////////////////////////////////////
146 parameter associativity = 1; // Associativity of the cache (Number of ways)
147 parameter sets = 512; // Number of sets
148 parameter bytes_per_line = 16; // Number of bytes per cache line
149 parameter base_address = 0; // Base address of cachable memory
150 parameter limit = 0; // Limit (highest address) of cachable memory
152 // For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
153 localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
154 localparam addr_offset_lsb = 2;
155 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
157 /////////////////////////////////////////////////////
158 // Inputs
159 /////////////////////////////////////////////////////
161 input clk_i; // Clock
162 input rst_i; // Reset
164 input stall_a; // Stall A stage instruction
165 input stall_f; // Stall F stage instruction
166 input stall_d; // Stall D stage instruction
167 input stall_x; // Stall X stage instruction
168 input stall_m; // Stall M stage instruction
169 input valid_f; // Instruction in F stage is valid
170 input valid_d; // Instruction in D stage is valid
171 input kill_f; // Kill instruction in F stage
173 input branch_predict_taken_d; // Branch is predicted taken in D stage
174 input [`LM32_PC_RNG] branch_predict_address_d; // Branch target address
176 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
177 input branch_taken_x; // Branch instruction in X stage is taken
178 input [`LM32_PC_RNG] branch_target_x; // Target PC of X stage branch instruction
179 `endif
180 input exception_m;
181 input branch_taken_m; // Branch instruction in M stage is taken
182 input branch_mispredict_taken_m; // Branch instruction in M stage is mispredicted as taken
183 input [`LM32_PC_RNG] branch_target_m; // Target PC of M stage branch instruction
185 `ifdef CFG_ICACHE_ENABLED
186 input iflush; // Flush instruction cache
187 `endif
188 `ifdef CFG_DCACHE_ENABLED
189 input dcache_restart_request; // Restart instruction that caused a data cache miss
190 input dcache_refill_request; // Request to refill data cache
191 input dcache_refilling;
192 `endif
194 `ifdef CFG_IROM_ENABLED
195 input [`LM32_WORD_RNG] irom_store_data_m; // Data from load-store unit
196 input [`LM32_WORD_RNG] irom_address_xm; // Address from load-store unit
197 input irom_we_xm; // Indicates if memory operation is load or store
198 `endif
200 `ifdef CFG_IWB_ENABLED
201 input [`LM32_WORD_RNG] i_dat_i; // Instruction Wishbone interface read data
202 input i_ack_i; // Instruction Wishbone interface acknowledgement
203 input i_err_i; // Instruction Wishbone interface error
204 `endif
206 `ifdef CFG_HW_DEBUG_ENABLED
207 input jtag_read_enable; // JTAG read memory request
208 input jtag_write_enable; // JTAG write memory request
209 input [`LM32_BYTE_RNG] jtag_write_data; // JTAG wrirte data
210 input [`LM32_WORD_RNG] jtag_address; // JTAG read/write address
211 `endif
213 /////////////////////////////////////////////////////
214 // Outputs
215 /////////////////////////////////////////////////////
217 output [`LM32_PC_RNG] pc_f; // F stage PC
218 reg [`LM32_PC_RNG] pc_f;
219 output [`LM32_PC_RNG] pc_d; // D stage PC
220 reg [`LM32_PC_RNG] pc_d;
221 output [`LM32_PC_RNG] pc_x; // X stage PC
222 reg [`LM32_PC_RNG] pc_x;
223 output [`LM32_PC_RNG] pc_m; // M stage PC
224 reg [`LM32_PC_RNG] pc_m;
225 output [`LM32_PC_RNG] pc_w; // W stage PC
226 reg [`LM32_PC_RNG] pc_w;
228 `ifdef CFG_ICACHE_ENABLED
229 output icache_stall_request; // Instruction cache stall request
230 wire icache_stall_request;
231 output icache_restart_request; // Request to restart instruction that cached instruction cache miss
232 wire icache_restart_request;
233 output icache_refill_request; // Instruction cache refill request
234 wire icache_refill_request;
235 output icache_refilling; // Indicates the icache is refilling
236 wire icache_refilling;
237 `endif
239 `ifdef CFG_IROM_ENABLED
240 output [`LM32_WORD_RNG] irom_data_m; // Data to load-store unit on load
241 wire [`LM32_WORD_RNG] irom_data_m;
242 `endif
244 `ifdef CFG_IWB_ENABLED
245 output [`LM32_WORD_RNG] i_dat_o; // Instruction Wishbone interface write data
246 `ifdef CFG_HW_DEBUG_ENABLED
247 reg [`LM32_WORD_RNG] i_dat_o;
248 `else
249 wire [`LM32_WORD_RNG] i_dat_o;
250 `endif
251 output [`LM32_WORD_RNG] i_adr_o; // Instruction Wishbone interface address
252 reg [`LM32_WORD_RNG] i_adr_o;
253 output i_cyc_o; // Instruction Wishbone interface cycle
254 reg i_cyc_o;
255 output [`LM32_BYTE_SELECT_RNG] i_sel_o; // Instruction Wishbone interface byte select
256 `ifdef CFG_HW_DEBUG_ENABLED
257 reg [`LM32_BYTE_SELECT_RNG] i_sel_o;
258 `else
259 wire [`LM32_BYTE_SELECT_RNG] i_sel_o;
260 `endif
261 output i_stb_o; // Instruction Wishbone interface strobe
262 reg i_stb_o;
263 output i_we_o; // Instruction Wishbone interface write enable
264 `ifdef CFG_HW_DEBUG_ENABLED
265 reg i_we_o;
266 `else
267 wire i_we_o;
268 `endif
269 output [`LM32_CTYPE_RNG] i_cti_o; // Instruction Wishbone interface cycle type
270 reg [`LM32_CTYPE_RNG] i_cti_o;
271 output i_lock_o; // Instruction Wishbone interface lock bus
272 reg i_lock_o;
273 output [`LM32_BTYPE_RNG] i_bte_o; // Instruction Wishbone interface burst type
274 wire [`LM32_BTYPE_RNG] i_bte_o;
275 `endif
277 `ifdef CFG_HW_DEBUG_ENABLED
278 output [`LM32_BYTE_RNG] jtag_read_data; // Data read for JTAG interface
279 reg [`LM32_BYTE_RNG] jtag_read_data;
280 output jtag_access_complete; // Requested memory access by JTAG interface is complete
281 wire jtag_access_complete;
282 `endif
284 `ifdef CFG_BUS_ERRORS_ENABLED
285 output bus_error_d; // Indicates a bus error occured while fetching the instruction
286 reg bus_error_d;
287 `endif
288 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
289 output [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction (only to have register indices extracted from)
290 wire [`LM32_INSTRUCTION_RNG] instruction_f;
291 `endif
292 output [`LM32_INSTRUCTION_RNG] instruction_d; // D stage instruction to be decoded
293 reg [`LM32_INSTRUCTION_RNG] instruction_d;
295 /////////////////////////////////////////////////////
296 // Internal nets and registers
297 /////////////////////////////////////////////////////
299 reg [`LM32_PC_RNG] pc_a; // A stage PC
301 `ifdef LM32_CACHE_ENABLED
302 reg [`LM32_PC_RNG] restart_address; // Address to restart from after a cache miss
303 `endif
305 `ifdef CFG_ICACHE_ENABLED
306 wire icache_read_enable_f; // Indicates if instruction cache miss is valid
307 wire [`LM32_PC_RNG] icache_refill_address; // Address that caused cache miss
308 reg icache_refill_ready; // Indicates when next word of refill data is ready to be written to cache
309 reg [`LM32_INSTRUCTION_RNG] icache_refill_data; // Next word of refill data, fetched from Wishbone
310 wire [`LM32_INSTRUCTION_RNG] icache_data_f; // Instruction fetched from instruction cache
311 wire [`LM32_CTYPE_RNG] first_cycle_type; // First Wishbone cycle type
312 wire [`LM32_CTYPE_RNG] next_cycle_type; // Next Wishbone cycle type
313 wire last_word; // Indicates if this is the last word in the cache line
314 wire [`LM32_PC_RNG] first_address; // First cache refill address
315 `else
316 `ifdef CFG_IWB_ENABLED
317 reg [`LM32_INSTRUCTION_RNG] wb_data_f; // Instruction fetched from Wishbone
318 `endif
319 `endif
320 `ifdef CFG_IROM_ENABLED
321 wire irom_select_a; // Indicates if A stage PC maps to a ROM address
322 reg irom_select_f; // Indicates if F stage PC maps to a ROM address
323 wire [`LM32_INSTRUCTION_RNG] irom_data_f; // Instruction fetched from ROM
324 `endif
325 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
326 `else
327 wire [`LM32_INSTRUCTION_RNG] instruction_f; // F stage instruction
328 `endif
329 `ifdef CFG_BUS_ERRORS_ENABLED
330 reg bus_error_f; // Indicates if a bus error occured while fetching the instruction in the F stage
331 `endif
333 `ifdef CFG_HW_DEBUG_ENABLED
334 reg jtag_access; // Indicates if a JTAG WB access is in progress
335 `endif
337 /////////////////////////////////////////////////////
338 // Functions
339 /////////////////////////////////////////////////////
341 `include "lm32_functions.v"
343 /////////////////////////////////////////////////////
344 // Instantiations
345 /////////////////////////////////////////////////////
347 // Instruction ROM
348 `ifdef CFG_IROM_ENABLED
349 pmi_ram_dp_true
350 #(
351 // ----- Parameters -------
352 .pmi_family (`LATTICE_FAMILY),
354 //.pmi_addr_depth_a (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
355 //.pmi_addr_width_a ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
356 //.pmi_data_width_a (`LM32_WORD_WIDTH),
357 //.pmi_addr_depth_b (1 << (clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
358 //.pmi_addr_width_b ((clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)),
359 //.pmi_data_width_b (`LM32_WORD_WIDTH),
361 .pmi_addr_depth_a (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
362 .pmi_addr_width_a (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
363 .pmi_data_width_a (`LM32_WORD_WIDTH),
364 .pmi_addr_depth_b (`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1),
365 .pmi_addr_width_b (clogb2_v1(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)),
366 .pmi_data_width_b (`LM32_WORD_WIDTH),
368 .pmi_regmode_a ("noreg"),
369 .pmi_regmode_b ("noreg"),
370 .pmi_gsr ("enable"),
371 .pmi_resetmode ("sync"),
372 .pmi_init_file (`CFG_IROM_INIT_FILE),
373 .pmi_init_file_format (`CFG_IROM_INIT_FILE_FORMAT),
374 .module_type ("pmi_ram_dp_true")
375 )
376 ram (
377 // ----- Inputs -------
378 .ClockA (clk_i),
379 .ClockB (clk_i),
380 .ResetA (rst_i),
381 .ResetB (rst_i),
382 .DataInA ({32{1'b0}}),
383 .DataInB (irom_store_data_m),
384 .AddressA (pc_a[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
385 .AddressB (irom_address_xm[(clogb2(`CFG_IROM_LIMIT/4-`CFG_IROM_BASE_ADDRESS/4+1)-1)+2-1:2]),
386 .ClockEnA (!stall_a),
387 .ClockEnB (!stall_x || !stall_m),
388 .WrA (`FALSE),
389 .WrB (irom_we_xm),
390 // ----- Outputs -------
391 .QA (irom_data_f),
392 .QB (irom_data_m)
393 );
394 `endif
396 `ifdef CFG_ICACHE_ENABLED
397 // Instruction cache
398 lm32_icache #(
399 .associativity (associativity),
400 .sets (sets),
401 .bytes_per_line (bytes_per_line),
402 .base_address (base_address),
403 .limit (limit)
404 ) icache (
405 // ----- Inputs -----
406 .clk_i (clk_i),
407 .rst_i (rst_i),
408 .stall_a (stall_a),
409 .stall_f (stall_f),
410 .branch_predict_taken_d (branch_predict_taken_d),
411 .valid_d (valid_d),
412 .address_a (pc_a),
413 .address_f (pc_f),
414 .read_enable_f (icache_read_enable_f),
415 .refill_ready (icache_refill_ready),
416 .refill_data (icache_refill_data),
417 .iflush (iflush),
418 // ----- Outputs -----
419 .stall_request (icache_stall_request),
420 .restart_request (icache_restart_request),
421 .refill_request (icache_refill_request),
422 .refill_address (icache_refill_address),
423 .refilling (icache_refilling),
424 .inst (icache_data_f)
425 );
426 `endif
428 /////////////////////////////////////////////////////
429 // Combinational Logic
430 /////////////////////////////////////////////////////
432 `ifdef CFG_ICACHE_ENABLED
433 // Generate signal that indicates when instruction cache misses are valid
434 assign icache_read_enable_f = (valid_f == `TRUE)
435 && (kill_f == `FALSE)
436 `ifdef CFG_DCACHE_ENABLED
437 && (dcache_restart_request == `FALSE)
438 `endif
439 `ifdef CFG_IROM_ENABLED
440 && (irom_select_f == `FALSE)
441 `endif
442 ;
443 `endif
445 // Compute address of next instruction to fetch
446 always @(*)
447 begin
448 // The request from the latest pipeline stage must take priority
449 `ifdef CFG_DCACHE_ENABLED
450 if (dcache_restart_request == `TRUE)
451 pc_a = restart_address;
452 else
453 `endif
454 if (branch_taken_m == `TRUE)
455 if ((branch_mispredict_taken_m == `TRUE) && (exception_m == `FALSE))
456 pc_a = pc_x;
457 else
458 pc_a = branch_target_m;
459 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
460 else if (branch_taken_x == `TRUE)
461 pc_a = branch_target_x;
462 `endif
463 else
464 if ( (valid_d == `TRUE) && (branch_predict_taken_d == `TRUE) )
465 pc_a = branch_predict_address_d;
466 else
467 `ifdef CFG_ICACHE_ENABLED
468 if (icache_restart_request == `TRUE)
469 pc_a = restart_address;
470 else
471 `endif
472 pc_a = pc_f + 1'b1;
473 end
475 // Select where instruction should be fetched from
476 `ifdef CFG_IROM_ENABLED
477 assign irom_select_a = ({pc_a, 2'b00} >= `CFG_IROM_BASE_ADDRESS) && ({pc_a, 2'b00} <= `CFG_IROM_LIMIT);
478 `endif
480 // Select instruction from selected source
481 `ifdef CFG_ICACHE_ENABLED
482 `ifdef CFG_IROM_ENABLED
483 assign instruction_f = irom_select_f == `TRUE ? irom_data_f : icache_data_f;
484 `else
485 assign instruction_f = icache_data_f;
486 `endif
487 `else
488 `ifdef CFG_IROM_ENABLED
489 `ifdef CFG_IWB_ENABLED
490 assign instruction_f = irom_select_f == `TRUE ? irom_data_f : wb_data_f;
491 `else
492 assign instruction_f = irom_data_f;
493 `endif
494 `else
495 assign instruction_f = wb_data_f;
496 `endif
497 `endif
499 // Unused/constant Wishbone signals
500 `ifdef CFG_IWB_ENABLED
501 `ifdef CFG_HW_DEBUG_ENABLED
502 `else
503 assign i_dat_o = 32'd0;
504 assign i_we_o = `FALSE;
505 assign i_sel_o = 4'b1111;
506 `endif
507 assign i_bte_o = `LM32_BTYPE_LINEAR;
508 `endif
510 `ifdef CFG_ICACHE_ENABLED
511 // Determine parameters for next cache refill Wishbone access
512 generate
513 case (bytes_per_line)
514 4:
515 begin
516 assign first_cycle_type = `LM32_CTYPE_END;
517 assign next_cycle_type = `LM32_CTYPE_END;
518 assign last_word = `TRUE;
519 assign first_address = icache_refill_address;
520 end
521 8:
522 begin
523 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
524 assign next_cycle_type = `LM32_CTYPE_END;
525 assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 1'b1;
526 assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
527 end
528 16:
529 begin
530 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
531 assign next_cycle_type = i_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
532 assign last_word = i_adr_o[addr_offset_msb:addr_offset_lsb] == 2'b11;
533 assign first_address = {icache_refill_address[`LM32_PC_WIDTH+2-1:addr_offset_msb+1], {addr_offset_width{1'b0}}};
534 end
535 endcase
536 endgenerate
537 `endif
539 /////////////////////////////////////////////////////
540 // Sequential Logic
541 /////////////////////////////////////////////////////
543 // PC
544 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
545 begin
546 if (rst_i == `TRUE)
547 begin
548 pc_f <= (`CFG_EBA_RESET-4)/4;
549 pc_d <= {`LM32_PC_WIDTH{1'b0}};
550 pc_x <= {`LM32_PC_WIDTH{1'b0}};
551 pc_m <= {`LM32_PC_WIDTH{1'b0}};
552 pc_w <= {`LM32_PC_WIDTH{1'b0}};
553 end
554 else
555 begin
556 if (stall_f == `FALSE)
557 pc_f <= pc_a;
558 if (stall_d == `FALSE)
559 pc_d <= pc_f;
560 if (stall_x == `FALSE)
561 pc_x <= pc_d;
562 if (stall_m == `FALSE)
563 pc_m <= pc_x;
564 pc_w <= pc_m;
565 end
566 end
568 `ifdef LM32_CACHE_ENABLED
569 // Address to restart from after a cache miss has been handled
570 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
571 begin
572 if (rst_i == `TRUE)
573 restart_address <= {`LM32_PC_WIDTH{1'b0}};
574 else
575 begin
576 `ifdef CFG_DCACHE_ENABLED
577 `ifdef CFG_ICACHE_ENABLED
578 // D-cache restart address must take priority, otherwise instructions will be lost
579 if (dcache_refill_request == `TRUE)
580 restart_address <= pc_w;
581 else if ((icache_refill_request == `TRUE) && (!dcache_refilling) && (!dcache_restart_request))
582 restart_address <= icache_refill_address;
583 `else
584 if (dcache_refill_request == `TRUE)
585 restart_address <= pc_w;
586 `endif
587 `else
588 `ifdef CFG_ICACHE_ENABLED
589 if (icache_refill_request == `TRUE)
590 restart_address <= icache_refill_address;
591 `endif
592 `endif
593 end
594 end
595 `endif
597 // Record where instruction was fetched from
598 `ifdef CFG_IROM_ENABLED
599 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
600 begin
601 if (rst_i == `TRUE)
602 irom_select_f <= `FALSE;
603 else
604 begin
605 if (stall_f == `FALSE)
606 irom_select_f <= irom_select_a;
607 end
608 end
609 `endif
611 `ifdef CFG_HW_DEBUG_ENABLED
612 assign jtag_access_complete = (i_cyc_o == `TRUE) && ((i_ack_i == `TRUE) || (i_err_i == `TRUE)) && (jtag_access == `TRUE);
613 always @(*)
614 begin
615 case (jtag_address[1:0])
616 2'b00: jtag_read_data = i_dat_i[`LM32_BYTE_3_RNG];
617 2'b01: jtag_read_data = i_dat_i[`LM32_BYTE_2_RNG];
618 2'b10: jtag_read_data = i_dat_i[`LM32_BYTE_1_RNG];
619 2'b11: jtag_read_data = i_dat_i[`LM32_BYTE_0_RNG];
620 endcase
621 end
622 `endif
624 `ifdef CFG_IWB_ENABLED
625 // Instruction Wishbone interface
626 `ifdef CFG_ICACHE_ENABLED
627 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
628 begin
629 if (rst_i == `TRUE)
630 begin
631 i_cyc_o <= `FALSE;
632 i_stb_o <= `FALSE;
633 i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
634 i_cti_o <= `LM32_CTYPE_END;
635 i_lock_o <= `FALSE;
636 icache_refill_data <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
637 icache_refill_ready <= `FALSE;
638 `ifdef CFG_BUS_ERRORS_ENABLED
639 bus_error_f <= `FALSE;
640 `endif
641 `ifdef CFG_HW_DEBUG_ENABLED
642 i_we_o <= `FALSE;
643 i_sel_o <= 4'b1111;
644 jtag_access <= `FALSE;
645 `endif
646 end
647 else
648 begin
649 icache_refill_ready <= `FALSE;
650 // Is a cycle in progress?
651 if (i_cyc_o == `TRUE)
652 begin
653 // Has cycle completed?
654 if ((i_ack_i == `TRUE) || (i_err_i == `TRUE))
655 begin
656 `ifdef CFG_HW_DEBUG_ENABLED
657 if (jtag_access == `TRUE)
658 begin
659 i_cyc_o <= `FALSE;
660 i_stb_o <= `FALSE;
661 i_we_o <= `FALSE;
662 jtag_access <= `FALSE;
663 end
664 else
665 `endif
666 begin
667 if (last_word == `TRUE)
668 begin
669 // Cache line fill complete
670 i_cyc_o <= `FALSE;
671 i_stb_o <= `FALSE;
672 i_lock_o <= `FALSE;
673 end
674 // Fetch next word in cache line
675 i_adr_o[addr_offset_msb:addr_offset_lsb] <= i_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
676 i_cti_o <= next_cycle_type;
677 // Write fetched data into instruction cache
678 icache_refill_ready <= `TRUE;
679 icache_refill_data <= i_dat_i;
680 end
681 end
682 `ifdef CFG_BUS_ERRORS_ENABLED
683 if (i_err_i == `TRUE)
684 begin
685 bus_error_f <= `TRUE;
686 $display ("Instruction bus error. Address: %x", i_adr_o);
687 end
688 `endif
689 end
690 else
691 begin
692 if ((icache_refill_request == `TRUE) && (icache_refill_ready == `FALSE))
693 begin
694 // Read first word of cache line
695 `ifdef CFG_HW_DEBUG_ENABLED
696 i_sel_o <= 4'b1111;
697 `endif
698 i_adr_o <= {first_address, 2'b00};
699 i_cyc_o <= `TRUE;
700 i_stb_o <= `TRUE;
701 i_cti_o <= first_cycle_type;
702 //i_lock_o <= `TRUE;
703 `ifdef CFG_BUS_ERRORS_ENABLED
704 bus_error_f <= `FALSE;
705 `endif
706 end
707 `ifdef CFG_HW_DEBUG_ENABLED
708 else
709 begin
710 if ((jtag_read_enable == `TRUE) || (jtag_write_enable == `TRUE))
711 begin
712 case (jtag_address[1:0])
713 2'b00: i_sel_o <= 4'b1000;
714 2'b01: i_sel_o <= 4'b0100;
715 2'b10: i_sel_o <= 4'b0010;
716 2'b11: i_sel_o <= 4'b0001;
717 endcase
718 i_adr_o <= jtag_address;
719 i_dat_o <= {4{jtag_write_data}};
720 i_cyc_o <= `TRUE;
721 i_stb_o <= `TRUE;
722 i_we_o <= jtag_write_enable;
723 i_cti_o <= `LM32_CTYPE_END;
724 jtag_access <= `TRUE;
725 end
726 end
727 `endif
728 `ifdef CFG_BUS_ERRORS_ENABLED
729 // Clear bus error when exception taken, otherwise they would be
730 // continually generated if exception handler is cached
731 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
732 if (branch_taken_x == `TRUE)
733 bus_error_f <= `FALSE;
734 `endif
735 if (branch_taken_m == `TRUE)
736 bus_error_f <= `FALSE;
737 `endif
738 end
739 end
740 end
741 `else
742 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
743 begin
744 if (rst_i == `TRUE)
745 begin
746 i_cyc_o <= `FALSE;
747 i_stb_o <= `FALSE;
748 i_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
749 i_cti_o <= `LM32_CTYPE_END;
750 i_lock_o <= `FALSE;
751 wb_data_f <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
752 `ifdef CFG_BUS_ERRORS_ENABLED
753 bus_error_f <= `FALSE;
754 `endif
755 end
756 else
757 begin
758 // Is a cycle in progress?
759 if (i_cyc_o == `TRUE)
760 begin
761 // Has cycle completed?
762 if((i_ack_i == `TRUE) || (i_err_i == `TRUE))
763 begin
764 // Cycle complete
765 i_cyc_o <= `FALSE;
766 i_stb_o <= `FALSE;
767 // Register fetched instruction
768 wb_data_f <= i_dat_i;
769 end
770 `ifdef CFG_BUS_ERRORS_ENABLED
771 if (i_err_i == `TRUE)
772 begin
773 bus_error_f <= `TRUE;
774 $display ("Instruction bus error. Address: %x", i_adr_o);
775 end
776 `endif
777 end
778 else
779 begin
780 // Wait for an instruction fetch from an external address
781 if ( (stall_a == `FALSE)
782 `ifdef CFG_IROM_ENABLED
783 && (irom_select_a == `FALSE)
784 `endif
785 )
786 begin
787 // Fetch instruction
788 `ifdef CFG_HW_DEBUG_ENABLED
789 i_sel_o <= 4'b1111;
790 `endif
791 i_adr_o <= {pc_a, 2'b00};
792 i_cyc_o <= `TRUE;
793 i_stb_o <= `TRUE;
794 `ifdef CFG_BUS_ERRORS_ENABLED
795 bus_error_f <= `FALSE;
796 `endif
797 end
798 else
799 begin
800 if ( (stall_a == `FALSE)
801 `ifdef CFG_IROM_ENABLED
802 && (irom_select_a == `TRUE)
803 `endif
804 )
805 begin
806 `ifdef CFG_BUS_ERRORS_ENABLED
807 bus_error_f <= `FALSE;
808 `endif
809 end
810 end
811 end
812 end
813 end
814 `endif
815 `endif
817 // Instruction register
818 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
819 begin
820 if (rst_i == `TRUE)
821 begin
822 instruction_d <= {`LM32_INSTRUCTION_WIDTH{1'b0}};
823 `ifdef CFG_BUS_ERRORS_ENABLED
824 bus_error_d <= `FALSE;
825 `endif
826 end
827 else
828 begin
829 if (stall_d == `FALSE)
830 begin
831 instruction_d <= instruction_f;
832 `ifdef CFG_BUS_ERRORS_ENABLED
833 bus_error_d <= bus_error_f;
834 `endif
835 end
836 end
837 end
839 endmodule