Sun, 06 Mar 2011 21:17:31 +0000
[MERGE] Merge changes from LatticeMico32 v3.6
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_include.v
19 // Title : CPU global macros
20 // Version : 6.1.17
21 // : Initial Release
22 // Version : 7.0SP2, 3.0
23 // : No Change
24 // Version : 3.1
25 // : No Change
26 // Version : 3.2
27 // : No Change
28 // Version : 3.3
29 // : Support for extended configuration register
30 // =============================================================================
32 `ifdef LM32_INCLUDE_V
33 `else
34 `define LM32_INCLUDE_V
36 //
37 // Common configuration options
38 //
40 `define CFG_EBA_RESET 32'h00000000
41 `define CFG_DEBA_RESET 32'h10000000
43 `define CFG_PL_MULTIPLY_ENABLED
44 `define CFG_PL_BARREL_SHIFT_ENABLED
45 `define CFG_SIGN_EXTEND_ENABLED
46 `define CFG_MC_DIVIDE_ENABLED
47 `define CFG_EBR_POSEDGE_REGISTER_FILE
49 // [found by Milkymist dev'rs]
50 // Bug in Xst:
51 // CFG_ICACHE_ASSOCIATIVITY=2 => works in most cases (random crash on complex software)
52 // CFG_ICACHE_ASSOCIATIVITY=1 => disaster, CPU will not work at all
53 // Works 100% OK with expensive synthesizers.
54 `define CFG_ICACHE_ENABLED
55 `define CFG_ICACHE_ASSOCIATIVITY 1
56 `define CFG_ICACHE_SETS 256
57 `define CFG_ICACHE_BYTES_PER_LINE 16
58 `define CFG_ICACHE_BASE_ADDRESS 32'h0
59 `define CFG_ICACHE_LIMIT 32'h7FFF_FFFF
61 `define CFG_DCACHE_ENABLED
62 `define CFG_DCACHE_ASSOCIATIVITY 1
63 `define CFG_DCACHE_SETS 256
64 `define CFG_DCACHE_BYTES_PER_LINE 16
65 `define CFG_DCACHE_BASE_ADDRESS 32'h0
66 `define CFG_DCACHE_LIMIT 32'h0FFF_FFFF
68 // Enable Debugging
69 //`define CFG_JTAG_ENABLED
70 //`define CFG_JTAG_UART_ENABLED
71 //`define CFG_DEBUG_ENABLED
72 //`define CFG_HW_DEBUG_ENABLED
73 //`define CFG_ROM_DEBUG_ENABLED
74 //`define CFG_BREAKPOINTS 32'h0
75 //`define CFG_WATCHPOINTS 32'h0
77 //
78 // End of common configuration options
79 //
81 `ifdef TRUE
82 `else
83 `define TRUE 1'b1
84 `define FALSE 1'b0
85 `define TRUE_N 1'b0
86 `define FALSE_N 1'b1
87 `endif
89 // Wishbone configuration
90 `define CFG_IWB_ENABLED
91 `define CFG_DWB_ENABLED
93 // Data-path width
94 `define LM32_WORD_WIDTH 32
95 `define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0
96 `define LM32_SHIFT_WIDTH 5
97 `define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0
98 `define LM32_BYTE_SELECT_WIDTH 4
99 `define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0
101 // Register file size
102 `define LM32_REGISTERS 32
103 `define LM32_REG_IDX_WIDTH 5
104 `define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0
106 // Standard register numbers
107 `define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29
108 `define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30
109 `define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31
111 // Range of Program Counter. Two LSBs are always 0.
112 // `ifdef CFG_ICACHE_ENABLED
113 // `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
114 // `else
115 // `ifdef CFG_IWB_ENABLED
116 `define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2)
117 // `else
118 // `define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH
119 // `endif
120 // `endif
121 `define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2
123 // Range of an instruction
124 `define LM32_INSTRUCTION_WIDTH 32
125 `define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0
127 // Adder operation
128 `define LM32_ADDER_OP_ADD 1'b0
129 `define LM32_ADDER_OP_SUBTRACT 1'b1
131 // Shift direction
132 `define LM32_SHIFT_OP_RIGHT 1'b0
133 `define LM32_SHIFT_OP_LEFT 1'b1
135 // Bus errors
136 //`define CFG_BUS_ERRORS_ENABLED
138 // Derive macro that indicates whether we have single-stepping or not
139 `ifdef CFG_ROM_DEBUG_ENABLED
140 `define LM32_SINGLE_STEP_ENABLED
141 `else
142 `ifdef CFG_HW_DEBUG_ENABLED
143 `define LM32_SINGLE_STEP_ENABLED
144 `endif
145 `endif
147 // Derive macro that indicates whether JTAG interface is required
148 `ifdef CFG_JTAG_UART_ENABLED
149 `define LM32_JTAG_ENABLED
150 `else
151 `ifdef CFG_DEBUG_ENABLED
152 `define LM32_JTAG_ENABLED
153 `else
154 `endif
155 `endif
157 // Derive macro that indicates whether we have a barrel-shifter or not
158 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
159 `define LM32_BARREL_SHIFT_ENABLED
160 `else // CFG_PL_BARREL_SHIFT_ENABLED
161 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
162 `define LM32_BARREL_SHIFT_ENABLED
163 `else
164 `define LM32_NO_BARREL_SHIFT
165 `endif
166 `endif // CFG_PL_BARREL_SHIFT_ENABLED
168 // Derive macro that indicates whether we have a multiplier or not
169 `ifdef CFG_PL_MULTIPLY_ENABLED
170 `define LM32_MULTIPLY_ENABLED
171 `else
172 `ifdef CFG_MC_MULTIPLY_ENABLED
173 `define LM32_MULTIPLY_ENABLED
174 `endif
175 `endif
177 // Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
178 `ifdef CFG_MC_DIVIDE_ENABLED
179 `define LM32_MC_ARITHMETIC_ENABLED
180 `endif
181 `ifdef CFG_MC_MULTIPLY_ENABLED
182 `define LM32_MC_ARITHMETIC_ENABLED
183 `endif
184 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
185 `define LM32_MC_ARITHMETIC_ENABLED
186 `endif
188 // Derive macro that indicates if we are using an EBR register file
189 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
190 `define LM32_EBR_REGISTER_FILE
191 `endif
192 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
193 `define LM32_EBR_REGISTER_FILE
194 `endif
196 // Revision number
197 `define LM32_REVISION 6'h02
199 // Logical operations - Function encoded directly in instruction
200 `define LM32_LOGIC_OP_RNG 3:0
202 // Conditions for conditional branches
203 `define LM32_CONDITION_WIDTH 3
204 `define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0
205 `define LM32_CONDITION_E 3'b001
206 `define LM32_CONDITION_G 3'b010
207 `define LM32_CONDITION_GE 3'b011
208 `define LM32_CONDITION_GEU 3'b100
209 `define LM32_CONDITION_GU 3'b101
210 `define LM32_CONDITION_NE 3'b111
211 `define LM32_CONDITION_U1 3'b000
212 `define LM32_CONDITION_U2 3'b110
214 // Size of load or store instruction - Encoding corresponds to opcode
215 `define LM32_SIZE_WIDTH 2
216 `define LM32_SIZE_RNG 1:0
217 `define LM32_SIZE_BYTE 2'b00
218 `define LM32_SIZE_HWORD 2'b11
219 `define LM32_SIZE_WORD 2'b10
220 `define LM32_ADDRESS_LSBS_WIDTH 2
222 // Width and range of a CSR index
223 `ifdef CFG_DEBUG_ENABLED
224 `define LM32_CSR_WIDTH 5
225 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
226 `else
227 `ifdef CFG_JTAG_ENABLED
228 `define LM32_CSR_WIDTH 4
229 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
230 `else
231 `define LM32_CSR_WIDTH 3
232 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
233 `endif
234 `endif
236 // CSR indices
237 `define LM32_CSR_IE `LM32_CSR_WIDTH'h0
238 `define LM32_CSR_IM `LM32_CSR_WIDTH'h1
239 `define LM32_CSR_IP `LM32_CSR_WIDTH'h2
240 `define LM32_CSR_ICC `LM32_CSR_WIDTH'h3
241 `define LM32_CSR_DCC `LM32_CSR_WIDTH'h4
242 `define LM32_CSR_CC `LM32_CSR_WIDTH'h5
243 `define LM32_CSR_CFG `LM32_CSR_WIDTH'h6
244 `define LM32_CSR_EBA `LM32_CSR_WIDTH'h7
245 `ifdef CFG_DEBUG_ENABLED
246 `define LM32_CSR_DC `LM32_CSR_WIDTH'h8
247 `define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9
248 `endif
249 `define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha
250 `ifdef CFG_JTAG_ENABLED
251 `define LM32_CSR_JTX `LM32_CSR_WIDTH'he
252 `define LM32_CSR_JRX `LM32_CSR_WIDTH'hf
253 `endif
254 `ifdef CFG_DEBUG_ENABLED
255 `define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10
256 `define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11
257 `define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12
258 `define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13
259 `define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18
260 `define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19
261 `define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a
262 `define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
263 `endif
265 // Values for WPC CSR
266 `define LM32_WPC_C_RNG 1:0
267 `define LM32_WPC_C_DISABLED 2'b00
268 `define LM32_WPC_C_READ 2'b01
269 `define LM32_WPC_C_WRITE 2'b10
270 `define LM32_WPC_C_READ_WRITE 2'b11
272 // Exception IDs
273 `define LM32_EID_WIDTH 3
274 `define LM32_EID_RNG (`LM32_EID_WIDTH-1):0
275 `define LM32_EID_RESET 3'h0
276 `define LM32_EID_BREAKPOINT 3'd1
277 `define LM32_EID_INST_BUS_ERROR 3'h2
278 `define LM32_EID_WATCHPOINT 3'd3
279 `define LM32_EID_DATA_BUS_ERROR 3'h4
280 `define LM32_EID_DIVIDE_BY_ZERO 3'h5
281 `define LM32_EID_INTERRUPT 3'h6
282 `define LM32_EID_SCALL 3'h7
284 // Pipeline result selection mux controls
286 `define LM32_D_RESULT_SEL_0_RNG 0:0
287 `define LM32_D_RESULT_SEL_0_REG_0 1'b0
288 `define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1
290 `define LM32_D_RESULT_SEL_1_RNG 1:0
291 `define LM32_D_RESULT_SEL_1_ZERO 2'b00
292 `define LM32_D_RESULT_SEL_1_REG_1 2'b01
293 `define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10
295 `define LM32_USER_OPCODE_WIDTH 11
296 `define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0
298 // Derive a macro to indicate if either of the caches are implemented
299 `ifdef CFG_ICACHE_ENABLED
300 `define LM32_CACHE_ENABLED
301 `else
302 `ifdef CFG_DCACHE_ENABLED
303 `define LM32_CACHE_ENABLED
304 `endif
305 `endif
307 /////////////////////////////////////////////////////
308 // Interrupts
309 /////////////////////////////////////////////////////
311 // Always enable interrupts
312 `define CFG_INTERRUPTS_ENABLED
314 // Currently this is fixed to 32 and should not be changed
315 `define CFG_INTERRUPTS 32
316 `define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS
317 `define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0
319 /////////////////////////////////////////////////////
320 // General
321 /////////////////////////////////////////////////////
323 // Sub-word range types
324 `define LM32_BYTE_WIDTH 8
325 `define LM32_BYTE_RNG 7:0
326 `define LM32_HWORD_WIDTH 16
327 `define LM32_HWORD_RNG 15:0
329 // Word sub-byte indicies
330 `define LM32_BYTE_0_RNG 7:0
331 `define LM32_BYTE_1_RNG 15:8
332 `define LM32_BYTE_2_RNG 23:16
333 `define LM32_BYTE_3_RNG 31:24
335 // Word sub-halfword indices
336 `define LM32_HWORD_0_RNG 15:0
337 `define LM32_HWORD_1_RNG 31:16
339 // Use an asynchronous reset
340 // To use a synchronous reset, define this macro as nothing
341 //`define CFG_RESET_SENSITIVITY or posedge rst_i
342 `define CFG_RESET_SENSITIVITY
344 // Whether to include context registers for debug exceptions
345 // in addition to standard exception handling registers
346 `define CFG_DEBUG_EXCEPTIONS_ENABLED
348 // Wishbone defines
349 // Refer to Wishbone System-on-Chip Interconnection Architecture
350 // These should probably be moved to a Wishbone common file
352 // Wishbone cycle types
353 `define LM32_CTYPE_WIDTH 3
354 `define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0
355 `define LM32_CTYPE_CLASSIC 3'b000
356 `define LM32_CTYPE_CONSTANT 3'b001
357 `define LM32_CTYPE_INCREMENTING 3'b010
358 `define LM32_CTYPE_END 3'b111
360 // Wishbone burst types
361 `define LM32_BTYPE_WIDTH 2
362 `define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0
363 `define LM32_BTYPE_LINEAR 2'b00
364 `define LM32_BTYPE_4_BEAT 2'b01
365 `define LM32_BTYPE_8_BEAT 2'b10
366 `define LM32_BTYPE_16_BEAT 2'b11
368 `endif