jtag_cores.v

Sun, 06 Mar 2011 19:32:57 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 19:32:57 +0000
changeset 15
27f96ec74b85
parent 14
54dd95f89113
child 16
5fb37de64edc
permissions
-rwxr-xr-x

fix jtag_cores typo

Original-Author: lekernel
Original-Source: milkymist 96d0e3995ce0c9d7cbb7

     1 // TODO
     3 module jtag_cores (
     4     // ----- Inputs -------
     5     reg_d,
     6     reg_addr_d,
     7     // ----- Outputs -------    
     8     reg_update,
     9     reg_q,
    10     reg_addr_q,
    11     jtck,
    12     jrstn
    13 );
    15 input [7:0] reg_d;
    16 input [2:0] reg_addr_d;
    18 output reg_update;
    19 wire   reg_update;
    20 output [7:0] reg_q;
    21 wire   [7:0] reg_q;
    22 output [2:0] reg_addr_q;
    23 wire   [2:0] reg_addr_q;
    25 output jtck;
    26 wire   jtck;
    27 output jrstn;
    28 wire   jrstn;
    30 assign reg_update = 1'b0;
    31 assign reg_q = 8'hxx;
    32 assign reg_addr_q = 3'bxxx;
    33 assign jtck = 1'b0;
    34 assign jrstn = 1'b1;
    36 endmodule