document/lm32.htm

Sun, 06 Mar 2011 21:14:43 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 21:14:43 +0000
changeset 22
35dc7ba83714
parent 8
07be9df9fee8
child 29
a82f6ed53fa6
permissions
-rwxr-xr-x

[UPSTREAM PULL] Update baseline to LatticeMico32 v3.6 from Diamond 1.1-lm32 distribution package (datestamp Nov 2010)

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   130 <h1>LatticeMico32 Processor &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<a title="View Reference Manual" href="lm32_archman.pdf" target="_blank" onmouseover="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_showtip(this,event,'View Reference Manual');" onmouseout="if ((parseInt(navigator.appVersion) == 4) && (navigator.appName == 'Netscape')) ehlp_hidetip();"><img src="ds_icon_ast.jpg" x-maintain-ratio="TRUE" width="29px" height="31px" border="0" class="img_whs1"></a></h1>
   132 <p>The LatticeMico32 processor is a high-performance 32-bit microprocessor 
   133  optimized for Lattice Semiconductor field-programmable gate arrays. </p>
   135 <p class="whs2"><span style="font-style: italic;"><I>*If the 
   136  processor manual fails to open, see the note at the bottom of this page.</I></span></p>
   138 <h2>Revision History</h2>
   140 <table x-use-null-cells cellspacing="0" width="738" height="84" class="whs3">
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   143 //--></script>
   144 <col class="whs4">
   145 <col class="whs5">
   147 <tr valign="top" class="whs6">
   148 <td bgcolor="#DEE8F4" width="93px" class="whs7">
   149 <p class=Table
   150 	style="font-weight: bold;">Version</td>
   151 <td bgcolor="#DEE8F4" width="598px" class="whs8">
   152 <p class=Table
   153 	style="font-weight: bold;">Description</td></tr>
   155 <tr valign="top" class="whs6">
   156 <td colspan="1" rowspan="1" width="93px" class="whs9">
   157 <p class=Table
   158 	style="font-weight: normal;">3.6</td>
   159 <td colspan="1" rowspan="1" width="598px" class="whs10">
   160 <p class=whs10
   161 	style="margin-left: 0px;">Fixed the issue of the processor locking 
   162  up when Instruction Cache is not used.</td></tr>
   164 <tr valign="top" class="whs6">
   165 <td colspan="1" rowspan="1" width="93px" class="whs9">
   166 <p class=Table
   167 	style="font-weight: normal;">3.5</td>
   168 <td colspan="1" rowspan="1" width="598px" class="whs10">
   169 <p class=whs10
   170 	style="margin-left: 0px;">Support added to allow Inline Memories to 
   171  be generated as non-power-of-two, as long as they are a multiple of 1024 
   172  bytes</td></tr>
   174 <tr valign="top" class="whs6">
   175 <td colspan="1" rowspan="1" width="93px" class="whs9">
   176 <p class=Table
   177 	style="font-weight: normal;">3.4</td>
   178 <td colspan="1" rowspan="1" width="598px" class="whs10">
   179 <p class=whs10
   180 	style="margin-left: 0px;">Updated to support ispLEVER 7.2 SP1.</td></tr>
   182 <tr valign="top" class="whs6">
   183 <td colspan="1" rowspan="1" width="93px" class="whs9">
   184 <p class=Table
   185 	style="font-weight: normal;">3.3</td>
   186 <td colspan="1" rowspan="1" width="598px" class="whs10">
   187 <p class=whs10
   188 	style="margin-left: 0px;">Updated to support ispLEVER 7.2.</p>
   189 <p class=whs10
   190 	style="margin-left: 0px;">Added Inline Memory to support on-chip memory 
   191  connected through a local bus.</td></tr>
   193 <tr valign="top" class="whs6">
   194 <td colspan="1" rowspan="1" width="93px" class="whs9">
   195 <p class=Table
   196 	style="font-weight: normal;">3.2</td>
   197 <td colspan="1" rowspan="1" width="598px" class="whs10">
   198 <p class=whs10
   199 	style="margin-left: 0px;">Updated to support ispLEVER 7.1 SP1</p>
   200 <p class=whs10
   201 	style="margin-left: 0px;">Added Memory Type to instruction cache and 
   202  data cache.</td></tr>
   204 <tr valign="top" class="whs6">
   205 <td colspan="1" rowspan="1" width="93px" class="whs9">
   206 <p class=Table
   207 	style="font-weight: normal;">3.1</td>
   208 <td colspan="1" rowspan="1" width="598px" class="whs10">
   209 <p class="whs11">Updated to support ispLEVER 7.1.</p>
   210 <p class="whs11">Added static predictor to improve the behavior 
   211  of branches.</p>
   212 <p class="whs11">Added support for optionally mapping the register 
   213  file to EBRs (on-chip memory).</p>
   214 <p class="whs11">Added support for selecting between distributed 
   215  RAM and EBRs (pseudo-dual port or true-dual port) for instruction and 
   216  data caches.</td></tr>
   218 <tr valign="top" class="whs6">
   219 <td colspan="1" rowspan="1" width="93px" class="whs9">
   220 <p class=Table
   221 	style="font-weight: normal;"><span style="font-weight: normal;">3.0 
   222  (7.0 SP2)</span></td>
   223 <td colspan="1" rowspan="1" width="598px" class="whs10">
   224 <p class="whs11">Updated to support ispLEVER 7.0 SP2.</p>
   225 <p class="whs11">Fixed incorrect handling of data cache miss 
   226  in the presence of an instruction cache miss.</td></tr>
   228 <tr valign="top" class="whs6">
   229 <td colspan="1" rowspan="1" width="93px" class="whs9">
   230 <p class="whs11">1.0</td>
   231 <td colspan="1" rowspan="1" width="598px" class="whs10">
   232 <p class="whs11">Initial version.</td></tr>
   233 <script language='JavaScript'><!--
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   236 </table>
   238 &nbsp; 
   240 <h2>Dialog Box Parameters &#8211; 
   241  General Tab</h2>
   243 <table x-use-null-cells cellspacing="0" class="whs12">
   244 <col class="whs13">
   245 <col class="whs14">
   247 <tr valign="top" class="whs15">
   248 <td bgcolor="#DEE8F4" width="167px" class="whs16">
   249 <p class=Table
   250 	style="font-weight: bold;">Parameter</td>
   251 <td bgcolor="#DEE8F4" width="524px" class="whs17">
   252 <p class=Table
   253 	style="font-weight: bold;">Description</td></tr>
   255 <tr valign="top" class="whs15">
   256 <td colspan="1" rowspan="1" width="167px" class="whs18">
   257 <p class=Table
   258 	style="font-weight: normal;">Instance Name</td>
   259 <td colspan="1" rowspan="1" width="524px" class="whs19">
   260 <p class=Table
   261 	style="margin-left: 14px;">Specifies the name of the LatticeMico32 
   262  processor. Alphanumeric values and underscores are supported. The default 
   263  is LM32.</td></tr>
   265 <tr valign="top" class="whs15">
   266 <td colspan="2" rowspan="1" width="691px" class="whs20">
   267 <p class=Table
   268 	style="font-weight: bold;">Settings</td>
   269 </tr>
   271 <tr valign="top" class="whs15">
   272 <td colspan="1" rowspan="1" width="167px" class="whs18">
   273 <p class=Table>Use EBRs for Register File</td>
   274 <td colspan="1" rowspan="1" width="524px" class="whs21">
   275 <p class=Table>Uses embedded block RAMS for the register file.</td></tr>
   277 <tr valign="top" class="whs15">
   278 <td colspan="1" rowspan="1" width="167px" class="whs18">
   279 <p class=Table>Enable Divide</td>
   280 <td colspan="1" rowspan="1" width="524px" class="whs21">
   281 <p class=Table>Enables the divide and modulus instructions (<span style="font-family: Verdana, sans-serif;">divu, 
   282  modu</span>).</td></tr>
   284 <tr valign="top" class="whs15">
   285 <td colspan="1" rowspan="1" width="167px" class="whs18">
   286 <p class=Table>Enable Sign Extend</td>
   287 <td colspan="1" rowspan="1" width="524px" class="whs21">
   288 <p class=Table>Enables the sign-extension instructions (<span style="font-family: Verdana, sans-serif;">sextb, 
   289  sexth</span><span style="font-family: Arial, sans-serif;">)</span>.</td></tr>
   291 <tr valign="top" class="whs15">
   292 <td colspan="1" rowspan="1" width="167px" class="whs18">
   293 <p class=Table>Location of Exception Handlers</td>
   294 <td colspan="1" rowspan="1" width="524px" class="whs21">
   295 <p class=Table>Specifies the default value for the vector table. This can 
   296  be changed by updating the EBA control register or status register.</p>
   297 <p class=Table>This address must be aligned to a 256-byte boundary, since 
   298  the hardware ignores the least-significant byte. Unpredictable behavior 
   299  occurs when the exception base address and the exception vectors are not 
   300  aligned on a 256-byte boundary.</td></tr>
   302 <tr valign="top" class="whs15">
   303 <td colspan="2" rowspan="1" width="691px" class="whs20">
   304 <p class=Table
   305 	style="font-weight: bold;">Multiplier Settings</td>
   306 </tr>
   308 <tr valign="top" class="whs15">
   309 <td colspan="1" rowspan="1" width="167px" class="whs18">
   310 <p class=Table>Enable Multiplier</td>
   311 <td colspan="1" rowspan="1" width="524px" class="whs21">
   312 <p class=Table>Enables the multiply instructions (<span style="font-family: Verdana, sans-serif;">mul, 
   313  muli)</span>.</td></tr>
   315 <tr valign="top" class="whs15">
   316 <td colspan="1" rowspan="1" width="167px" class="whs18">
   317 <p class=Table>Enable Pipelined Multiplier (DSP Block if available)</td>
   318 <td colspan="1" rowspan="1" width="524px" class="whs21">
   319 <p class=Table>Enables the multiplier using the DSP block, if available.</td></tr>
   321 <tr valign="top" class="whs15">
   322 <td colspan="1" rowspan="1" width="167px" class="whs18">
   323 <p class=Table>Enable Multicycle (LUT-based, 32 cycles) Multiplier</td>
   324 <td colspan="1" rowspan="1" width="524px" class="whs21">
   325 <p class=Table>Enables the multiplier using LUTs.</td></tr>
   327 <tr valign="top" class="whs15">
   328 <td colspan="2" rowspan="1" width="691px" class="whs20">
   329 <p class=Table
   330 	style="font-weight: bold;">Instruction Cache</td>
   331 </tr>
   333 <tr valign="top" class="whs15">
   334 <td colspan="1" rowspan="1" width="167px" class="whs18">
   335 <p class=Table>Instruction Cache Enabled</td>
   336 <td colspan="1" rowspan="1" width="524px" class="whs19">
   337 <p class=Table
   338 	style="margin-left: 14px;">Determines whether an instruction cache 
   339  is implemented.</td></tr>
   341 <tr valign="top" class="whs15">
   342 <td colspan="1" rowspan="1" width="167px" class="whs18">
   343 <p class=Table>Number of Sets</td>
   344 <td colspan="1" rowspan="1" width="524px" class="whs19">
   345 <p class=Table
   346 	style="margin-left: 14px;">Specifies the number of sets in the instruction 
   347  cache. Supported values are 128, 256, 512, 1024.</td></tr>
   349 <tr valign="top" class="whs15">
   350 <td colspan="1" rowspan="1" width="167px" class="whs18">
   351 <p class=Table>Set Associativity</td>
   352 <td colspan="1" rowspan="1" width="524px" class="whs19">
   353 <p class=Table
   354 	style="margin-left: 14px;">Specifies the associativity of the instruction 
   355  cache. Supported values are 1, 2.</td></tr>
   357 <tr valign="top" class="whs15">
   358 <td colspan="1" rowspan="1" width="167px" class="whs18">
   359 <p class=Table>Bytes/Cache Line</td>
   360 <td colspan="1" rowspan="1" width="524px" class="whs19">
   361 <p class=Table
   362 	style="margin-left: 15px;">Specifies the number of bytes per instruction 
   363  cache line. Supported values are 4, 8, 16.</td></tr>
   365 <tr valign="top" class="whs15">
   366 <td colspan="1" rowspan="1" width="167px" class="whs18">
   367 <p class=Table>Memory Type</td>
   368 <td colspan="1" rowspan="1" width="524px" class="whs19">
   369 <p class=Table
   370 	style="margin-left: 15px;">Determines the FPGA resource to be used 
   371  to implement the instruction cache. The decision can be left to the synthesis 
   372  tool (Auto), or you can select from the following options:</p>
   373 <ul type="disc" class="whs22">
   375 	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
   376  Leaves the implementation of the instruction cache to the synthesis tool.</p></li>
   378 	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
   379  Implements the instruction cache as distributed RAM.</p></li>
   381 	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
   382  Implements the instruction cache as dual-port EBR (two read/write ports).</p></li>
   384 	<li class=kadov-p-CBullet><p class=Bullet>Pseudo Dual-Port EBR &#8211; Implements 
   385  the instruction cache as pseudo-dual-port EBR (one read port and one write 
   386  port). </p></li>
   387 </ul></td></tr>
   389 <tr valign="top" class="whs15">
   390 <td colspan="2" rowspan="1" width="691px" class="whs20">
   391 <p class=Table
   392 	style="font-weight: bold;">Debug Setting</td>
   393 </tr>
   395 <tr valign="top" class="whs15">
   396 <td colspan="1" rowspan="1" width="167px" class="whs18">
   397 <p class=Table>Enable Debug Interface</td>
   398 <td colspan="1" rowspan="1" width="524px" class="whs21">
   399 <p class=Table>Includes the debugger stub in the CPU, which is required 
   400  for debugging.</td></tr>
   402 <tr valign="top" class="whs15">
   403 <td colspan="1" rowspan="1" width="167px" class="whs18">
   404 <p class=Table># of H/W Watchpoint Registers</td>
   405 <td colspan="1" rowspan="1" width="524px" class="whs21">
   406 <p class=Table
   407 	style="font-weight: normal;">Specifies the number of hardware watchpoint 
   408  registers to be used in the debugging process.</td></tr>
   410 <tr valign="top" class="whs15">
   411 <td colspan="1" rowspan="1" width="167px" class="whs18">
   412 <p class=Table>Enable Debugging Code in Flash or ROM</td>
   413 <td colspan="1" rowspan="1" width="524px" class="whs21">
   414 <p class=Table
   415 	style="font-weight: normal;">Enables you to set hardware breakpoints 
   416  in read-only memory.</td></tr>
   418 <tr valign="top" class="whs15">
   419 <td colspan="1" rowspan="1" width="167px" class="whs18">
   420 <p class=Table># of H/W Breakpoint Registers</td>
   421 <td colspan="1" rowspan="1" width="524px" class="whs21">
   422 <p class=Table>Specifies the number of hardware breakpoint registers to 
   423  be used in the debugging process.</td></tr>
   425 <tr valign="top" class="whs15">
   426 <td colspan="1" rowspan="1" width="167px" class="whs18">
   427 <p class=Table>Enable PC Trace</td>
   428 <td colspan="1" rowspan="1" width="524px" class="whs21">
   429 <p class=Table>Enables the Program Counter Trace feature, which enables 
   430  you to run the program trace during debug to find items in your C or C++ 
   431  Code during debug, such as breakpoints and exceptions. Refer to <span 
   432  style="font-weight: bold;"><B>Help &gt; Help Contents &gt; C/C++ SPE</B></span> 
   433  and <span style="font-weight: bold;"><B>Debug &gt; Concepts &gt; Program 
   434  Counter Trace</B></span> for more information on Program Counter Trace.</td></tr>
   436 <tr valign="top" class="whs15">
   437 <td colspan="1" rowspan="1" width="167px" class="whs18">
   438 <p class=Table>Trace Depth</td>
   439 <td colspan="1" rowspan="1" width="524px" class="whs21">
   440 <p class=Table>Enables you to specify the depth of the Program Counter 
   441  Trace buffer. Refer to <span style="font-weight: bold;"><B>Help &gt; Help 
   442  Contents &gt; C/C++ SPE</B></span> and <span style="font-weight: bold;"><B>Debug 
   443  &gt; Concepts &gt; Program Counter Trace</B></span> for more information on 
   444  Program Counter Trace.</td></tr>
   446 <tr valign="top" class="whs15">
   447 <td colspan="2" rowspan="1" width="691px" class="whs20">
   448 <p class=Table
   449 	style="font-weight: bold;">Shifter Settings</td>
   450 </tr>
   452 <tr valign="top" class="whs15">
   453 <td colspan="1" rowspan="1" width="167px" class="whs18">
   454 <p class=Table>Enable Piplined Barrel Shifter</td>
   455 <td colspan="1" rowspan="1" width="524px" class="whs19">
   456 <p>Enables the barrel shifter to be pipelined. The barrel shifter is implemented 
   457  to perform a shift operation in three cycles.</td></tr>
   459 <tr valign="top" class="whs15">
   460 <td colspan="1" rowspan="1" width="167px" class="whs18">
   461 <p class=Table>Enable Multicycle Barrel Shifter (up to 32 cycles)</td>
   462 <td colspan="1" rowspan="1" width="524px" class="whs19">
   463 <p>Enables multi-cycle shift operation for the barrel shifter. The barrel 
   464  shifter is implemented to shift one bit per cycle and take thirty-two 
   465  cycles to complete.</td></tr>
   467 <tr valign="top" class="whs15">
   468 <td colspan="2" rowspan="1" width="691px" class="whs20">
   469 <p class=Table><span style="font-weight: bold;"><B>Data Cache</B></span></td>
   470 </tr>
   472 <tr valign="top" class="whs15">
   473 <td colspan="1" rowspan="1" width="167px" class="whs18">
   474 <p class=Table>Data Cache Enabled</td>
   475 <td colspan="1" rowspan="1" width="524px" class="whs21">
   476 <p class=Table>Determines whether a data cache is implemented.</td></tr>
   478 <tr valign="top" class="whs15">
   479 <td colspan="1" rowspan="1" width="167px" class="whs18">
   480 <p class=Table>Number of Sets</td>
   481 <td colspan="1" rowspan="1" width="524px" class="whs21">
   482 <p class=Table>Specifies the number of sets in the data cache. Supported 
   483  values are 128, 256, 512, 1024.</td></tr>
   485 <tr valign="top" class="whs15">
   486 <td colspan="1" rowspan="1" width="167px" class="whs18">
   487 <p class=Table>Set Associativity</td>
   488 <td colspan="1" rowspan="1" width="524px" class="whs21">
   489 <p class=Table>Specifies the associativity of the data cache. Supported 
   490  values are 1, 2.</td></tr>
   492 <tr valign="top" class="whs15">
   493 <td colspan="1" rowspan="1" width="167px" class="whs18">
   494 <p class=Table>Bytes/Cache Line</td>
   495 <td colspan="1" rowspan="1" width="524px" class="whs21">
   496 <p class=Table>Specifies the number of bytes per data cache line. Supported 
   497  values are 4, 8, 16.</td></tr>
   499 <tr valign="top" class="whs15">
   500 <td colspan="1" rowspan="1" width="167px" class="whs23">
   501 <p class=Table>Memory Type</td>
   502 <td colspan="1" rowspan="1" width="524px" class="whs24">
   503 <p class=Table>Determines the FPGA resource to be used to implement the 
   504  data cache. The decision can be left to the synthesis tool (Auto), or 
   505  you can select from the following options:</p>
   506 <ul>
   508 	<li class=kadov-p-CBullet><p class=Bullet>Auto &#8211; 
   509  Leaves the implementation of the data cache to the synthesis tool.</p></li>
   511 	<li class=kadov-p-CBullet><p class=Bullet>Distributed RAM &#8211; 
   512  Implements the data cache as distributed RAM.</p></li>
   514 	<li class=kadov-p-CBullet><p class=Bullet>Dual-Port EBR &#8211; 
   515  Implements the data cache as dual-port EBR (two read/write ports).</p></li>
   516 </ul></td></tr>
   517 </table>
   519 <p>&nbsp;</p>
   521 <h2>Dialog Box Parameters &#8211; 
   522  Inline Memory Tab</h2>
   524 <table x-use-null-cells cellspacing="0" class="whs12">
   525 <col class="whs13">
   526 <col class="whs14">
   528 <tr valign="top" class="whs15">
   529 <td bgcolor="#DEE8F4" width="167px" class="whs25">
   530 <p class=Table
   531 	style="font-weight: bold;">Parameter</td>
   532 <td bgcolor="#DEE8F4" width="524px" class="whs26">
   533 <p class=Table
   534 	style="font-weight: bold;">Description</td></tr>
   536 <tr valign="top" class="whs15">
   537 <td rowspan="1" colspan="2" width="691px" class="whs27">
   538 <p class=Table
   539 	style="font-weight: bold;">Instruction Inline Memory</td>
   540 </tr>
   542 <tr valign="top" class="whs15">
   543 <td width="167px" class="whs28">
   544 <p class=Table>Enable</td>
   545 <td width="524px" class="whs29">
   546 <p class=Table>Enables the instruction inline memory</td></tr>
   548 <tr valign="top" class="whs15">
   549 <td width="167px" class="whs28">
   550 <p class=Table>Instance Name</td>
   551 <td width="524px" class="whs29">
   552 <p class=Table>Specifics the name of the instruction inline memory. Alphanumeric 
   553  values and underscores are supported. The default is Instruction_IM.</td></tr>
   555 <tr valign="top" class="whs15">
   556 <td width="167px" class="whs28">
   557 <p class=Table>Base Address</td>
   558 <td width="524px" class="whs29">
   559 <p class=Table>Specifies the base address for the instruction inline memory. 
   560  The default is 0x10000000.</td></tr>
   562 <tr valign="top" class="whs15">
   563 <td width="167px" class="whs28">
   564 <p class=Table>Size of Memory in Bytes</td>
   565 <td width="524px" class="whs29">
   566 <p class=Table>Specifies the size of the instruction inline memory.</td></tr>
   568 <tr valign="top" class="whs15">
   569 <td rowspan="1" colspan="2" width="691px" class="whs27">
   570 <p class=Table><span style="font-weight: bold;"><B>Memory File</B></span></td>
   571 </tr>
   573 <tr valign="top" class="whs15">
   574 <td width="167px" class="whs28">
   575 <p class=Table>Initialization File Name</td>
   576 <td width="524px" class="whs29">
   577 <p class=Table>Specifies the name of the memory initialization file for 
   578  instruction inline memory.</td></tr>
   580 <tr valign="top" class="whs15">
   581 <td width="167px" class="whs28">
   582 <p class=Table>File Format</td>
   583 <td width="524px" class="whs29">
   584 <p class=Table>Specifies the format of the memory initialization file: 
   585  hex or binary.</td></tr>
   587 <tr valign="top" class="whs15">
   588 <td rowspan="1" colspan="2" width="691px" class="whs27">
   589 <p class=Table
   590 	style="font-weight: bold;">Data Inline Memory</td>
   591 </tr>
   593 <tr valign="top" class="whs15">
   594 <td width="167px" class="whs28">
   595 <p class=Table>Enabled</td>
   596 <td width="524px" class="whs29">
   597 <p class=Table>Enables the data inline memory.</td></tr>
   599 <tr valign="top" class="whs15">
   600 <td width="167px" class="whs28">
   601 <p class=Table>Instance Name</td>
   602 <td width="524px" class="whs29">
   603 <p class=Table>Specifies the name of the data inline memory. Alphanumeric 
   604  values and underscores are supported. The default is Data_IM.</td></tr>
   606 <tr valign="top" class="whs15">
   607 <td width="167px" class="whs28">
   608 <p class=Table>Base Address</td>
   609 <td width="524px" class="whs29">
   610 <p class=Table>Specifies the base address for the data inline memory. The 
   611  default is 0x20000000.</td></tr>
   613 <tr valign="top" class="whs15">
   614 <td width="167px" class="whs28">
   615 <p class=Table>Size of Memory in Bytes</td>
   616 <td width="524px" class="whs29">
   617 <p class=Table>Specifies the size of the data inline memory.</td></tr>
   619 <tr valign="top" class="whs15">
   620 <td colspan="2" rowspan="1" width="691px" class="whs27">
   621 <p class=Table
   622 	style="font-weight: bold;">Memory File</td>
   623 </tr>
   625 <tr valign="top" class="whs15">
   626 <td colspan="1" rowspan="1" width="167px" class="whs28">
   627 <p class=Table>Initialization File Name</td>
   628 <td colspan="1" rowspan="1" width="524px" class="whs29">
   629 <p class=Table>Specifies the name of the memory initialization file for 
   630  data inline memory.</td></tr>
   632 <tr valign="top" class="whs15">
   633 <td colspan="1" rowspan="1" width="167px" class="whs30">
   634 <p class=Table>File Format</td>
   635 <td colspan="1" rowspan="1" width="524px" class="whs31">
   636 <p class=Table>Specifies the format of the memory initialization file: 
   637  hex or binary.</td></tr>
   638 </table>
   640 <p>&nbsp;</p>
   642 <p>For the revision history of the component RTL files, refer to the header 
   643  of each component Verilog source file. </p>
   645 <p><span style="font-weight: bold;"><B>Note</B></span>: If the processor manual 
   646  fails to open, click <img src="qm_icon.jpg" x-maintain-ratio="TRUE" width="14px" height="16px" border="0" class="img_whs32"> on the Available Components toolbar, 
   647  and then click the note button.</p>
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