Sun, 06 Mar 2011 21:14:43 +0000
[UPSTREAM PULL] Update baseline to LatticeMico32 v3.6 from Diamond 1.1-lm32 distribution package (datestamp Nov 2010)
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_include.v
19 // Title : CPU global macros
20 // Version : 6.1.17
21 // : Initial Release
22 // Version : 7.0SP2, 3.0
23 // : No Change
24 // Version : 3.1
25 // : No Change
26 // Version : 3.2
27 // : No Change
28 // Version : 3.3
29 // : Support for extended configuration register
30 // =============================================================================
32 `ifdef LM32_INCLUDE_V
33 `else
34 `define LM32_INCLUDE_V
36 // Configuration options
37 `include "system_conf.v"
39 `ifdef TRUE
40 `else
41 `define TRUE 1'b1
42 `define FALSE 1'b0
43 `define TRUE_N 1'b0
44 `define FALSE_N 1'b1
45 `endif
47 // Wishbone configuration
48 `define CFG_IWB_ENABLED
49 `define CFG_DWB_ENABLED
51 // Data-path width
52 `define LM32_WORD_WIDTH 32
53 `define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0
54 `define LM32_SHIFT_WIDTH 5
55 `define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0
56 `define LM32_BYTE_SELECT_WIDTH 4
57 `define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0
59 // Register file size
60 `define LM32_REGISTERS 32
61 `define LM32_REG_IDX_WIDTH 5
62 `define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0
64 // Standard register numbers
65 `define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29
66 `define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30
67 `define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31
69 // Range of Program Counter. Two LSBs are always 0.
70 // `ifdef CFG_ICACHE_ENABLED
71 // `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
72 // `else
73 // `ifdef CFG_IWB_ENABLED
74 `define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2)
75 // `else
76 // `define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH
77 // `endif
78 // `endif
79 `define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2
81 // Range of an instruction
82 `define LM32_INSTRUCTION_WIDTH 32
83 `define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0
85 // Adder operation
86 `define LM32_ADDER_OP_ADD 1'b0
87 `define LM32_ADDER_OP_SUBTRACT 1'b1
89 // Shift direction
90 `define LM32_SHIFT_OP_RIGHT 1'b0
91 `define LM32_SHIFT_OP_LEFT 1'b1
93 // Currently always enabled
94 `define CFG_BUS_ERRORS_ENABLED
96 // Derive macro that indicates whether we have single-stepping or not
97 `ifdef CFG_ROM_DEBUG_ENABLED
98 `define LM32_SINGLE_STEP_ENABLED
99 `else
100 `ifdef CFG_HW_DEBUG_ENABLED
101 `define LM32_SINGLE_STEP_ENABLED
102 `endif
103 `endif
105 // Derive macro that indicates whether JTAG interface is required
106 `ifdef CFG_JTAG_UART_ENABLED
107 `define LM32_JTAG_ENABLED
108 `else
109 `ifdef CFG_DEBUG_ENABLED
110 `define LM32_JTAG_ENABLED
111 `else
112 `endif
113 `endif
115 // Derive macro that indicates whether we have a barrel-shifter or not
116 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
117 `define LM32_BARREL_SHIFT_ENABLED
118 `else // CFG_PL_BARREL_SHIFT_ENABLED
119 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
120 `define LM32_BARREL_SHIFT_ENABLED
121 `else
122 `define LM32_NO_BARREL_SHIFT
123 `endif
124 `endif // CFG_PL_BARREL_SHIFT_ENABLED
126 // Derive macro that indicates whether we have a multiplier or not
127 `ifdef CFG_PL_MULTIPLY_ENABLED
128 `define LM32_MULTIPLY_ENABLED
129 `else
130 `ifdef CFG_MC_MULTIPLY_ENABLED
131 `define LM32_MULTIPLY_ENABLED
132 `endif
133 `endif
135 // Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
136 `ifdef CFG_MC_DIVIDE_ENABLED
137 `define LM32_MC_ARITHMETIC_ENABLED
138 `endif
139 `ifdef CFG_MC_MULTIPLY_ENABLED
140 `define LM32_MC_ARITHMETIC_ENABLED
141 `endif
142 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
143 `define LM32_MC_ARITHMETIC_ENABLED
144 `endif
146 // Derive macro that indicates if we are using an EBR register file
147 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
148 `define LM32_EBR_REGISTER_FILE
149 `endif
150 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
151 `define LM32_EBR_REGISTER_FILE
152 `endif
154 // Revision number
155 `define LM32_REVISION 6'h02
157 // Logical operations - Function encoded directly in instruction
158 `define LM32_LOGIC_OP_RNG 3:0
160 // Conditions for conditional branches
161 `define LM32_CONDITION_WIDTH 3
162 `define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0
163 `define LM32_CONDITION_E 3'b001
164 `define LM32_CONDITION_G 3'b010
165 `define LM32_CONDITION_GE 3'b011
166 `define LM32_CONDITION_GEU 3'b100
167 `define LM32_CONDITION_GU 3'b101
168 `define LM32_CONDITION_NE 3'b111
169 `define LM32_CONDITION_U1 3'b000
170 `define LM32_CONDITION_U2 3'b110
172 // Size of load or store instruction - Encoding corresponds to opcode
173 `define LM32_SIZE_WIDTH 2
174 `define LM32_SIZE_RNG 1:0
175 `define LM32_SIZE_BYTE 2'b00
176 `define LM32_SIZE_HWORD 2'b11
177 `define LM32_SIZE_WORD 2'b10
178 `define LM32_ADDRESS_LSBS_WIDTH 2
180 // Width and range of a CSR index
181 `ifdef CFG_DEBUG_ENABLED
182 `define LM32_CSR_WIDTH 5
183 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
184 `else
185 `ifdef CFG_JTAG_ENABLED
186 `define LM32_CSR_WIDTH 4
187 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
188 `else
189 `define LM32_CSR_WIDTH 3
190 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
191 `endif
192 `endif
194 // CSR indices
195 `define LM32_CSR_IE `LM32_CSR_WIDTH'h0
196 `define LM32_CSR_IM `LM32_CSR_WIDTH'h1
197 `define LM32_CSR_IP `LM32_CSR_WIDTH'h2
198 `define LM32_CSR_ICC `LM32_CSR_WIDTH'h3
199 `define LM32_CSR_DCC `LM32_CSR_WIDTH'h4
200 `define LM32_CSR_CC `LM32_CSR_WIDTH'h5
201 `define LM32_CSR_CFG `LM32_CSR_WIDTH'h6
202 `define LM32_CSR_EBA `LM32_CSR_WIDTH'h7
203 `ifdef CFG_DEBUG_ENABLED
204 `define LM32_CSR_DC `LM32_CSR_WIDTH'h8
205 `define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9
206 `endif
207 `define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha
208 `ifdef CFG_JTAG_ENABLED
209 `define LM32_CSR_JTX `LM32_CSR_WIDTH'he
210 `define LM32_CSR_JRX `LM32_CSR_WIDTH'hf
211 `endif
212 `ifdef CFG_DEBUG_ENABLED
213 `define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10
214 `define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11
215 `define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12
216 `define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13
217 `define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18
218 `define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19
219 `define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a
220 `define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
221 `endif
223 // Values for WPC CSR
224 `define LM32_WPC_C_RNG 1:0
225 `define LM32_WPC_C_DISABLED 2'b00
226 `define LM32_WPC_C_READ 2'b01
227 `define LM32_WPC_C_WRITE 2'b10
228 `define LM32_WPC_C_READ_WRITE 2'b11
230 // Exception IDs
231 `define LM32_EID_WIDTH 3
232 `define LM32_EID_RNG (`LM32_EID_WIDTH-1):0
233 `define LM32_EID_RESET 3'h0
234 `define LM32_EID_BREAKPOINT 3'd1
235 `define LM32_EID_INST_BUS_ERROR 3'h2
236 `define LM32_EID_WATCHPOINT 3'd3
237 `define LM32_EID_DATA_BUS_ERROR 3'h4
238 `define LM32_EID_DIVIDE_BY_ZERO 3'h5
239 `define LM32_EID_INTERRUPT 3'h6
240 `define LM32_EID_SCALL 3'h7
242 // Pipeline result selection mux controls
244 `define LM32_D_RESULT_SEL_0_RNG 0:0
245 `define LM32_D_RESULT_SEL_0_REG_0 1'b0
246 `define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1
248 `define LM32_D_RESULT_SEL_1_RNG 1:0
249 `define LM32_D_RESULT_SEL_1_ZERO 2'b00
250 `define LM32_D_RESULT_SEL_1_REG_1 2'b01
251 `define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10
253 `define LM32_USER_OPCODE_WIDTH 11
254 `define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0
256 // Derive a macro to indicate if either of the caches are implemented
257 `ifdef CFG_ICACHE_ENABLED
258 `define LM32_CACHE_ENABLED
259 `else
260 `ifdef CFG_DCACHE_ENABLED
261 `define LM32_CACHE_ENABLED
262 `endif
263 `endif
265 /////////////////////////////////////////////////////
266 // Interrupts
267 /////////////////////////////////////////////////////
269 // Always enable interrupts
270 `define CFG_INTERRUPTS_ENABLED
272 // Currently this is fixed to 32 and should not be changed
273 `define CFG_INTERRUPTS 32
274 `define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS
275 `define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0
277 /////////////////////////////////////////////////////
278 // General
279 /////////////////////////////////////////////////////
281 // Sub-word range types
282 `define LM32_BYTE_WIDTH 8
283 `define LM32_BYTE_RNG 7:0
284 `define LM32_HWORD_WIDTH 16
285 `define LM32_HWORD_RNG 15:0
287 // Word sub-byte indicies
288 `define LM32_BYTE_0_RNG 7:0
289 `define LM32_BYTE_1_RNG 15:8
290 `define LM32_BYTE_2_RNG 23:16
291 `define LM32_BYTE_3_RNG 31:24
293 // Word sub-halfword indices
294 `define LM32_HWORD_0_RNG 15:0
295 `define LM32_HWORD_1_RNG 31:16
297 // Use an asynchronous reset
298 // To use a synchronous reset, define this macro as nothing
299 `define CFG_RESET_SENSITIVITY or posedge rst_i
301 // V.T. Srce
302 `define SRCE
304 // Whether to include context registers for debug exceptions
305 // in addition to standard exception handling registers
306 // Bizarre - Removing this increases LUT count!
307 `define CFG_DEBUG_EXCEPTIONS_ENABLED
309 // Wishbone defines
310 // Refer to Wishbone System-on-Chip Interconnection Architecture
311 // These should probably be moved to a Wishbone common file
313 // Wishbone cycle types
314 `define LM32_CTYPE_WIDTH 3
315 `define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0
316 `define LM32_CTYPE_CLASSIC 3'b000
317 `define LM32_CTYPE_CONSTANT 3'b001
318 `define LM32_CTYPE_INCREMENTING 3'b010
319 `define LM32_CTYPE_END 3'b111
321 // Wishbone burst types
322 `define LM32_BTYPE_WIDTH 2
323 `define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0
324 `define LM32_BTYPE_LINEAR 2'b00
325 `define LM32_BTYPE_4_BEAT 2'b01
326 `define LM32_BTYPE_8_BEAT 2'b10
327 `define LM32_BTYPE_16_BEAT 2'b11
329 `endif