jtag_cores.v

Sun, 06 Mar 2011 19:49:17 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 19:49:17 +0000
changeset 17
50bf3061dbff
parent 16
5fb37de64edc
child 18
cc945f778cd7
permissions
-rwxr-xr-x

Enable Spartan 6 JTAG TAP only if selected (Michael Walle)

Original-Author: Michael Walle <michael walle.cc>
Original-Source: milkymist e7d77749236d73fcdc65

     1 module jtag_cores (
     2     input [7:0] reg_d,
     3     input [2:0] reg_addr_d,
     4     output reg_update,
     5     output [7:0] reg_q,
     6     output [2:0] reg_addr_q,
     7     output jtck,
     8     output jrstn
     9 );
    11 wire tck;
    12 wire tdi;
    13 wire tdo;
    14 wire shift;
    15 wire update;
    16 wire reset;
    18 jtag_tap jtag_tap (
    19 	.tck(tck),
    20 	.tdi(tdi),
    21 	.tdo(tdo),
    22 	.shift(shift),
    23 	.update(update),
    24 	.reset(reset)
    25 );
    27 reg [10:0] jtag_shift;
    28 reg [10:0] jtag_latched;
    30 always @(posedge tck or posedge reset)
    31 begin
    32 	if(reset)
    33 		jtag_shift <= 11'b0;
    34 	else begin
    35 		if(shift)
    36 			jtag_shift <= {tdi, jtag_shift[10:1]};
    37 		else
    38 			jtag_shift <= {reg_d, reg_addr_d};
    39 	end
    40 end
    42 assign tdo = jtag_shift[0];
    44 always @(posedge reg_update or posedge reset)
    45 begin
    46 	if(reset)
    47 		jtag_latched <= 11'b0;
    48 	else
    49 		jtag_latched <= jtag_shift;
    50 end
    52 assign reg_update = update;
    53 assign reg_q = jtag_latched[10:3];
    54 assign reg_addr_q = jtag_latched[2:0];
    55 assign jtck = tck;
    56 assign jrstn = ~reset;
    58 endmodule