Sun, 06 Mar 2011 19:48:34 +0000
Add JTAG interface for Xilinx Spartan 6 (Michael Walle)
Original-Source: Milkymist mailing list posting, 2010-09-23
Original-Message-Id: <201009232334.04219.michael@walle.cc>
Original-Author: Michael Walle <michael walle.cc>
1 module jtag_cores (
2 input [7:0] reg_d,
3 input [2:0] reg_addr_d,
4 output reg_update,
5 output [7:0] reg_q,
6 output [2:0] reg_addr_q,
7 output jtck,
8 output jrstn
9 );
11 wire sel;
12 wire tck;
13 wire tdi;
14 wire tdo;
15 wire shift;
16 wire update;
17 wire reset;
19 jtag_tap jtag_tap (
20 .sel(sel),
21 .tck(tck),
22 .tdi(tdi),
23 .tdo(tdo),
24 .shift(shift),
25 .update(update),
26 .reset(reset)
27 );
29 reg [10:0] jtag_shift;
30 reg [10:0] jtag_latched;
32 always @(posedge tck or posedge reset)
33 begin
34 if(reset)
35 jtag_shift <= 11'b0;
36 else begin
37 if(shift)
38 jtag_shift <= {tdi, jtag_shift[10:1]};
39 else
40 jtag_shift <= {reg_d, reg_addr_d};
41 end
42 end
44 assign tdo = jtag_shift[0];
46 always @(posedge reg_update or posedge reset)
47 begin
48 if(reset)
49 jtag_latched <= 11'b0;
50 else
51 jtag_latched <= jtag_shift;
52 end
54 assign reg_update = update & sel;
55 assign reg_q = jtag_latched[10:3];
56 assign reg_addr_q = jtag_latched[2:0];
57 assign jtck = tck;
58 assign jrstn = ~reset;
60 endmodule