lm32_jtag.v

Sun, 06 Mar 2011 19:48:34 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 19:48:34 +0000
changeset 16
5fb37de64edc
parent 14
54dd95f89113
child 18
cc945f778cd7
permissions
-rwxr-xr-x

Add JTAG interface for Xilinx Spartan 6 (Michael Walle)

Original-Source: Milkymist mailing list posting, 2010-09-23
Original-Message-Id: <201009232334.04219.michael@walle.cc>
Original-Author: Michael Walle <michael walle.cc>

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : lm32_jtag.v
    19 // Title            : JTAG interface
    20 // Dependencies     : lm32_include.v
    21 // Version          : 6.1.17
    22 //                  : Initial Release
    23 // Version          : 7.0SP2, 3.0
    24 //                  : No Change
    25 // Version          : 3.1
    26 //                  : No Change
    27 // =============================================================================
    29 `include "lm32_include.v"
    31 `ifdef CFG_JTAG_ENABLED
    33 `define LM32_DP                             3'b000
    34 `define LM32_TX                             3'b001
    35 `define LM32_RX                             3'b010
    37 // LM32 Debug Protocol commands IDs
    38 `define LM32_DP_RNG                         3:0
    39 `define LM32_DP_READ_MEMORY                 4'b0001
    40 `define LM32_DP_WRITE_MEMORY                4'b0010
    41 `define LM32_DP_READ_SEQUENTIAL             4'b0011
    42 `define LM32_DP_WRITE_SEQUENTIAL            4'b0100
    43 `define LM32_DP_WRITE_CSR                   4'b0101
    44 `define LM32_DP_BREAK                       4'b0110
    45 `define LM32_DP_RESET                       4'b0111
    47 // States for FSM
    48 `define LM32_JTAG_STATE_RNG                 3:0
    49 `define LM32_JTAG_STATE_READ_COMMAND        4'h0
    50 `define LM32_JTAG_STATE_READ_BYTE_0         4'h1
    51 `define LM32_JTAG_STATE_READ_BYTE_1         4'h2
    52 `define LM32_JTAG_STATE_READ_BYTE_2         4'h3
    53 `define LM32_JTAG_STATE_READ_BYTE_3         4'h4
    54 `define LM32_JTAG_STATE_READ_BYTE_4         4'h5
    55 `define LM32_JTAG_STATE_PROCESS_COMMAND     4'h6
    56 `define LM32_JTAG_STATE_WAIT_FOR_MEMORY     4'h7
    57 `define LM32_JTAG_STATE_WAIT_FOR_CSR        4'h8
    59 /////////////////////////////////////////////////////
    60 // Module interface
    61 /////////////////////////////////////////////////////
    63 module lm32_jtag (
    64     // ----- Inputs -------
    65     clk_i,
    66     rst_i,
    67     jtag_clk, 
    68     jtag_update,
    69     jtag_reg_q,
    70     jtag_reg_addr_q,
    71 `ifdef CFG_JTAG_UART_ENABLED
    72     csr,
    73     csr_write_enable,
    74     csr_write_data,
    75     stall_x,
    76 `endif
    77 `ifdef CFG_HW_DEBUG_ENABLED
    78     jtag_read_data,
    79     jtag_access_complete,
    80 `endif
    81 `ifdef CFG_DEBUG_ENABLED
    82     exception_q_w,
    83 `endif
    84     // ----- Outputs -------
    85 `ifdef CFG_JTAG_UART_ENABLED
    86     jtx_csr_read_data,
    87     jrx_csr_read_data,
    88 `endif
    89 `ifdef CFG_HW_DEBUG_ENABLED
    90     jtag_csr_write_enable,
    91     jtag_csr_write_data,
    92     jtag_csr,
    93     jtag_read_enable,
    94     jtag_write_enable,
    95     jtag_write_data,
    96     jtag_address,
    97 `endif
    98 `ifdef CFG_DEBUG_ENABLED
    99     jtag_break,
   100     jtag_reset,
   101 `endif
   102     jtag_reg_d,
   103     jtag_reg_addr_d
   104     );
   106 /////////////////////////////////////////////////////
   107 // Inputs
   108 /////////////////////////////////////////////////////
   110 input clk_i;                                            // Clock
   111 input rst_i;                                            // Reset
   113 input jtag_clk;                                         // JTAG clock
   114 input jtag_update;                                      // JTAG data register has been updated
   115 input [`LM32_BYTE_RNG] jtag_reg_q;                      // JTAG data register
   116 input [2:0] jtag_reg_addr_q;                            // JTAG data register
   118 `ifdef CFG_JTAG_UART_ENABLED
   119 input [`LM32_CSR_RNG] csr;                              // CSR to write
   120 input csr_write_enable;                                 // CSR write enable
   121 input [`LM32_WORD_RNG] csr_write_data;                  // Data to write to specified CSR
   122 input stall_x;                                          // Stall instruction in X stage
   123 `endif
   124 `ifdef CFG_HW_DEBUG_ENABLED
   125 input [`LM32_BYTE_RNG] jtag_read_data;                  // Data read from requested address
   126 input jtag_access_complete;                             // Memory access if complete
   127 `endif
   128 `ifdef CFG_DEBUG_ENABLED
   129 input exception_q_w;                                    // Indicates an exception has occured in W stage
   130 `endif
   132 /////////////////////////////////////////////////////
   133 // Outputs
   134 /////////////////////////////////////////////////////
   136 `ifdef CFG_JTAG_UART_ENABLED
   137 output [`LM32_WORD_RNG] jtx_csr_read_data;              // Value of JTX CSR for rcsr instructions
   138 wire   [`LM32_WORD_RNG] jtx_csr_read_data;
   139 output [`LM32_WORD_RNG] jrx_csr_read_data;              // Value of JRX CSR for rcsr instructions
   140 wire   [`LM32_WORD_RNG] jrx_csr_read_data;
   141 `endif
   142 `ifdef CFG_HW_DEBUG_ENABLED
   143 output jtag_csr_write_enable;                           // CSR write enable
   144 reg    jtag_csr_write_enable;
   145 output [`LM32_WORD_RNG] jtag_csr_write_data;            // Data to write to specified CSR
   146 wire   [`LM32_WORD_RNG] jtag_csr_write_data;
   147 output [`LM32_CSR_RNG] jtag_csr;                        // CSR to write
   148 wire   [`LM32_CSR_RNG] jtag_csr;
   149 output jtag_read_enable;                                // Memory read enable
   150 reg    jtag_read_enable;
   151 output jtag_write_enable;                               // Memory write enable
   152 reg    jtag_write_enable;
   153 output [`LM32_BYTE_RNG] jtag_write_data;                // Data to write to specified address
   154 wire   [`LM32_BYTE_RNG] jtag_write_data;        
   155 output [`LM32_WORD_RNG] jtag_address;                   // Memory read/write address
   156 wire   [`LM32_WORD_RNG] jtag_address;
   157 `endif
   158 `ifdef CFG_DEBUG_ENABLED
   159 output jtag_break;                                      // Request to raise a breakpoint exception
   160 reg    jtag_break;
   161 output jtag_reset;                                      // Request to raise a reset exception
   162 reg    jtag_reset;
   163 `endif
   164 output [`LM32_BYTE_RNG] jtag_reg_d;
   165 reg    [`LM32_BYTE_RNG] jtag_reg_d;
   166 output [2:0] jtag_reg_addr_d;
   167 wire   [2:0] jtag_reg_addr_d;
   169 /////////////////////////////////////////////////////
   170 // Internal nets and registers 
   171 /////////////////////////////////////////////////////
   173 reg rx_toggle;                          // Clock-domain crossing registers
   174 reg rx_toggle_r;                        // Registered version of rx_toggle
   175 reg rx_toggle_r_r;                      // Registered version of rx_toggle_r
   176 reg rx_toggle_r_r_r;                    // Registered version of rx_toggle_r_r
   178 reg [`LM32_BYTE_RNG] rx_byte;   
   179 reg [2:0] rx_addr;
   181 `ifdef CFG_JTAG_UART_ENABLED                 
   182 reg [`LM32_BYTE_RNG] uart_tx_byte;      // UART TX data
   183 reg uart_tx_valid;                      // TX data is valid
   184 reg [`LM32_BYTE_RNG] uart_rx_byte;      // UART RX data
   185 reg uart_rx_valid;                      // RX data is valid
   186 `endif
   188 reg [`LM32_DP_RNG] command;             // The last received command
   189 `ifdef CFG_HW_DEBUG_ENABLED
   190 reg [`LM32_BYTE_RNG] jtag_byte_0;       // Registers to hold command paramaters
   191 reg [`LM32_BYTE_RNG] jtag_byte_1;
   192 reg [`LM32_BYTE_RNG] jtag_byte_2;
   193 reg [`LM32_BYTE_RNG] jtag_byte_3;
   194 reg [`LM32_BYTE_RNG] jtag_byte_4;
   195 reg processing;                         // Indicates if we're still processing a memory read/write
   196 `endif
   198 reg [`LM32_JTAG_STATE_RNG] state;       // Current state of FSM
   200 /////////////////////////////////////////////////////
   201 // Combinational Logic
   202 /////////////////////////////////////////////////////
   204 `ifdef CFG_HW_DEBUG_ENABLED
   205 assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
   206 assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
   207 assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
   208 assign jtag_write_data = jtag_byte_4;
   209 `endif
   211 // Generate status flags for reading via the JTAG interface                 
   212 `ifdef CFG_JTAG_UART_ENABLED                 
   213 assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};         
   214 `else
   215 assign jtag_reg_addr_d[1:0] = 2'b00;
   216 `endif
   217 `ifdef CFG_HW_DEBUG_ENABLED
   218 assign jtag_reg_addr_d[2] = processing;
   219 `else
   220 assign jtag_reg_addr_d[2] = 1'b0;
   221 `endif
   223 `ifdef CFG_JTAG_UART_ENABLED                 
   224 assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
   225 assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
   226 `endif         
   228 /////////////////////////////////////////////////////
   229 // Sequential Logic
   230 /////////////////////////////////////////////////////
   232 // Toggle a flag when a JTAG write occurs
   234 always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
   235 begin
   236 if (rst_i == `TRUE)
   237   rx_toggle <= 1'b0;
   238 else 
   239   rx_toggle <= ~rx_toggle;
   240 end
   242 always @(*)
   243 begin
   244     rx_byte = jtag_reg_q;
   245     rx_addr = jtag_reg_addr_q;
   246 end
   248 // Clock domain crossing from JTAG clock domain to CPU clock domain
   249 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   250 begin
   251     if (rst_i == `TRUE)
   252     begin
   253         rx_toggle_r <= 1'b0;
   254         rx_toggle_r_r <= 1'b0;
   255         rx_toggle_r_r_r <= 1'b0;
   256     end
   257     else
   258     begin
   259         rx_toggle_r <= rx_toggle;
   260         rx_toggle_r_r <= rx_toggle_r;
   261         rx_toggle_r_r_r <= rx_toggle_r_r;
   262     end
   263 end
   265 // LM32 debug protocol state machine
   266 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   267 begin
   268     if (rst_i == `TRUE)
   269     begin
   270         state <= `LM32_JTAG_STATE_READ_COMMAND;
   271         command <= 4'b0000;
   272         jtag_reg_d <= 8'h00;
   273 `ifdef CFG_HW_DEBUG_ENABLED
   274         processing <= `FALSE;
   275         jtag_csr_write_enable <= `FALSE;
   276         jtag_read_enable <= `FALSE;
   277         jtag_write_enable <= `FALSE;
   278 `endif
   279 `ifdef CFG_DEBUG_ENABLED
   280         jtag_break <= `FALSE;
   281         jtag_reset <= `FALSE;
   282 `endif
   283 `ifdef CFG_JTAG_UART_ENABLED                 
   284         uart_tx_byte <= 8'h00;
   285         uart_tx_valid <= `FALSE;
   286         uart_rx_byte <= 8'h00;
   287         uart_rx_valid <= `FALSE;
   288 `endif
   289     end
   290     else
   291     begin
   292 `ifdef CFG_JTAG_UART_ENABLED                 
   293         if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
   294         begin
   295             case (csr)
   296             `LM32_CSR_JTX:
   297             begin
   298                 // Set flag indicating data is available
   299                 uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
   300                 uart_tx_valid <= `TRUE;
   301             end
   302             `LM32_CSR_JRX:
   303             begin
   304                 // Clear flag indidicating data has been received
   305                 uart_rx_valid <= `FALSE;
   306             end
   307             endcase
   308         end
   309 `endif
   310 `ifdef CFG_DEBUG_ENABLED
   311         // When an exception has occured, clear the requests
   312         if (exception_q_w == `TRUE)
   313         begin
   314             jtag_break <= `FALSE;
   315             jtag_reset <= `FALSE;
   316         end
   317 `endif
   318         case (state)
   319         `LM32_JTAG_STATE_READ_COMMAND:
   320         begin
   321             // Wait for rx register to toggle which indicates new data is available
   322             if (rx_toggle_r_r != rx_toggle_r_r_r)
   323             begin
   324                 command <= rx_byte[7:4];                
   325                 case (rx_addr)
   326 `ifdef CFG_DEBUG_ENABLED
   327                 `LM32_DP:
   328                 begin
   329                     case (rx_byte[7:4])
   330 `ifdef CFG_HW_DEBUG_ENABLED
   331                     `LM32_DP_READ_MEMORY:
   332                         state <= `LM32_JTAG_STATE_READ_BYTE_0;
   333                     `LM32_DP_READ_SEQUENTIAL:
   334                     begin
   335                         {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
   336                         state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   337                     end
   338                     `LM32_DP_WRITE_MEMORY:
   339                         state <= `LM32_JTAG_STATE_READ_BYTE_0;
   340                     `LM32_DP_WRITE_SEQUENTIAL:
   341                     begin
   342                         {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
   343                         state <= 5;
   344                     end
   345                     `LM32_DP_WRITE_CSR:
   346                         state <= `LM32_JTAG_STATE_READ_BYTE_0;
   347 `endif                    
   348                     `LM32_DP_BREAK:
   349                     begin
   350 `ifdef CFG_JTAG_UART_ENABLED     
   351                         uart_rx_valid <= `FALSE;    
   352                         uart_tx_valid <= `FALSE;         
   353 `endif
   354                         jtag_break <= `TRUE;
   355                     end
   356                     `LM32_DP_RESET:
   357                     begin
   358 `ifdef CFG_JTAG_UART_ENABLED     
   359                         uart_rx_valid <= `FALSE;    
   360                         uart_tx_valid <= `FALSE;         
   361 `endif
   362                         jtag_reset <= `TRUE;
   363                     end
   364                     endcase                               
   365                 end
   366 `endif
   367 `ifdef CFG_JTAG_UART_ENABLED                 
   368                 `LM32_TX:
   369                 begin
   370                     uart_rx_byte <= rx_byte;
   371                     uart_rx_valid <= `TRUE;
   372                 end                    
   373                 `LM32_RX:
   374                 begin
   375                     jtag_reg_d <= uart_tx_byte;
   376                     uart_tx_valid <= `FALSE;
   377                 end
   378 `endif
   379                 default:
   380                     ;
   381                 endcase                
   382             end
   383         end
   384 `ifdef CFG_HW_DEBUG_ENABLED
   385         `LM32_JTAG_STATE_READ_BYTE_0:
   386         begin
   387             if (rx_toggle_r_r != rx_toggle_r_r_r)
   388             begin
   389                 jtag_byte_0 <= rx_byte;
   390                 state <= `LM32_JTAG_STATE_READ_BYTE_1;
   391             end
   392         end
   393         `LM32_JTAG_STATE_READ_BYTE_1:
   394         begin
   395             if (rx_toggle_r_r != rx_toggle_r_r_r)
   396             begin
   397                 jtag_byte_1 <= rx_byte;
   398                 state <= `LM32_JTAG_STATE_READ_BYTE_2;
   399             end
   400         end
   401         `LM32_JTAG_STATE_READ_BYTE_2:
   402         begin
   403             if (rx_toggle_r_r != rx_toggle_r_r_r)
   404             begin
   405                 jtag_byte_2 <= rx_byte;
   406                 state <= `LM32_JTAG_STATE_READ_BYTE_3;
   407             end
   408         end
   409         `LM32_JTAG_STATE_READ_BYTE_3:
   410         begin
   411             if (rx_toggle_r_r != rx_toggle_r_r_r)
   412             begin
   413                 jtag_byte_3 <= rx_byte;
   414                 if (command == `LM32_DP_READ_MEMORY)
   415                     state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   416                 else 
   417                     state <= `LM32_JTAG_STATE_READ_BYTE_4;
   418             end
   419         end
   420         `LM32_JTAG_STATE_READ_BYTE_4:
   421         begin
   422             if (rx_toggle_r_r != rx_toggle_r_r_r)
   423             begin
   424                 jtag_byte_4 <= rx_byte;
   425                 state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   426             end
   427         end
   428         `LM32_JTAG_STATE_PROCESS_COMMAND:
   429         begin
   430             case (command)
   431             `LM32_DP_READ_MEMORY,
   432             `LM32_DP_READ_SEQUENTIAL:
   433             begin
   434                 jtag_read_enable <= `TRUE;
   435                 processing <= `TRUE;
   436                 state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   437             end
   438             `LM32_DP_WRITE_MEMORY,
   439             `LM32_DP_WRITE_SEQUENTIAL:
   440             begin
   441                 jtag_write_enable <= `TRUE;
   442                 processing <= `TRUE;
   443                 state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   444             end
   445             `LM32_DP_WRITE_CSR:
   446             begin
   447                 jtag_csr_write_enable <= `TRUE;
   448                 processing <= `TRUE;
   449                 state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
   450             end
   451             endcase
   452         end
   453         `LM32_JTAG_STATE_WAIT_FOR_MEMORY:
   454         begin
   455             if (jtag_access_complete == `TRUE)
   456             begin          
   457                 jtag_read_enable <= `FALSE;
   458                 jtag_reg_d <= jtag_read_data;
   459                 jtag_write_enable <= `FALSE;  
   460                 processing <= `FALSE;
   461                 state <= `LM32_JTAG_STATE_READ_COMMAND;
   462             end
   463         end    
   464         `LM32_JTAG_STATE_WAIT_FOR_CSR:
   465         begin
   466             jtag_csr_write_enable <= `FALSE;
   467             processing <= `FALSE;
   468             state <= `LM32_JTAG_STATE_READ_COMMAND;
   469         end    
   470 `endif
   471         endcase
   472     end
   473 end
   475 endmodule
   477 `endif