lm32_top.v

Sun, 06 Mar 2011 19:48:34 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 19:48:34 +0000
changeset 16
5fb37de64edc
parent 14
54dd95f89113
permissions
-rwxr-xr-x

Add JTAG interface for Xilinx Spartan 6 (Michael Walle)

Original-Source: Milkymist mailing list posting, 2010-09-23
Original-Message-Id: <201009232334.04219.michael@walle.cc>
Original-Author: Michael Walle <michael walle.cc>

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : lm32_top.v
    19 // Title            : Top-level of CPU.
    20 // Dependencies     : lm32_include.v
    21 // Version          : 6.1.17
    22 //                  : removed SPI - 04/12/07
    23 // Version          : 7.0SP2, 3.0
    24 //                  : No Change
    25 // Version          : 3.1
    26 //                  : No Change
    27 // =============================================================================
    29 `include "lm32_include.v"
    31 /////////////////////////////////////////////////////
    32 // Module interface
    33 /////////////////////////////////////////////////////
    35 module lm32_top (
    36     // ----- Inputs -------
    37     clk_i,
    38     rst_i,
    39     // From external devices
    40 `ifdef CFG_INTERRUPTS_ENABLED
    41     interrupt,
    42 `endif
    43     // From user logic
    44 `ifdef CFG_USER_ENABLED
    45     user_result,
    46     user_complete,
    47 `endif     
    48 `ifdef CFG_IWB_ENABLED
    49     // Instruction Wishbone master
    50     I_DAT_I,
    51     I_ACK_I,
    52     I_ERR_I,
    53     I_RTY_I,
    54 `endif
    55     // Data Wishbone master
    56     D_DAT_I,
    57     D_ACK_I,
    58     D_ERR_I,
    59     D_RTY_I,
    60     // ----- Outputs -------
    61 `ifdef CFG_USER_ENABLED    
    62     user_valid,
    63     user_opcode,
    64     user_operand_0,
    65     user_operand_1,
    66 `endif    
    67 `ifdef CFG_IWB_ENABLED
    68     // Instruction Wishbone master
    69     I_DAT_O,
    70     I_ADR_O,
    71     I_CYC_O,
    72     I_SEL_O,
    73     I_STB_O,
    74     I_WE_O,
    75     I_CTI_O,
    76     I_LOCK_O,
    77     I_BTE_O,
    78 `endif
    79     // Data Wishbone master
    80     D_DAT_O,
    81     D_ADR_O,
    82     D_CYC_O,
    83     D_SEL_O,
    84     D_STB_O,
    85     D_WE_O,
    86     D_CTI_O,
    87     D_LOCK_O,
    88     D_BTE_O
    89     );
    91 /////////////////////////////////////////////////////
    92 // Inputs
    93 /////////////////////////////////////////////////////
    95 input clk_i;                                    // Clock
    96 input rst_i;                                    // Reset
    98 `ifdef CFG_INTERRUPTS_ENABLED
    99 input [`LM32_INTERRUPT_RNG] interrupt;          // Interrupt pins
   100 `endif
   102 `ifdef CFG_USER_ENABLED
   103 input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
   104 input user_complete;                            // Indicates the user-defined instruction result is valid
   105 `endif    
   107 `ifdef CFG_IWB_ENABLED
   108 input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
   109 input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
   110 input I_ERR_I;                                  // Instruction Wishbone interface error
   111 input I_RTY_I;                                  // Instruction Wishbone interface retry
   112 `endif
   114 input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
   115 input D_ACK_I;                                  // Data Wishbone interface acknowledgement
   116 input D_ERR_I;                                  // Data Wishbone interface error
   117 input D_RTY_I;                                  // Data Wishbone interface retry
   119 /////////////////////////////////////////////////////
   120 // Outputs
   121 /////////////////////////////////////////////////////
   123 `ifdef CFG_USER_ENABLED
   124 output user_valid;                              // Indicates that user_opcode and user_operand_* are valid
   125 wire   user_valid;
   126 output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
   127 reg    [`LM32_USER_OPCODE_RNG] user_opcode;
   128 output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
   129 wire   [`LM32_WORD_RNG] user_operand_0;
   130 output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
   131 wire   [`LM32_WORD_RNG] user_operand_1;
   132 `endif
   134 `ifdef CFG_IWB_ENABLED
   135 output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
   136 wire   [`LM32_WORD_RNG] I_DAT_O;
   137 output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
   138 wire   [`LM32_WORD_RNG] I_ADR_O;
   139 output I_CYC_O;                                 // Instruction Wishbone interface cycle
   140 wire   I_CYC_O;
   141 output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
   142 wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
   143 output I_STB_O;                                 // Instruction Wishbone interface strobe
   144 wire   I_STB_O;
   145 output I_WE_O;                                  // Instruction Wishbone interface write enable
   146 wire   I_WE_O;
   147 output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type 
   148 wire   [`LM32_CTYPE_RNG] I_CTI_O;
   149 output I_LOCK_O;                                // Instruction Wishbone interface lock bus
   150 wire   I_LOCK_O;
   151 output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type 
   152 wire   [`LM32_BTYPE_RNG] I_BTE_O;
   153 `endif
   155 output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
   156 wire   [`LM32_WORD_RNG] D_DAT_O;
   157 output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
   158 wire   [`LM32_WORD_RNG] D_ADR_O;
   159 output D_CYC_O;                                 // Data Wishbone interface cycle
   160 wire   D_CYC_O;
   161 output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
   162 wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
   163 output D_STB_O;                                 // Data Wishbone interface strobe
   164 wire   D_STB_O;
   165 output D_WE_O;                                  // Data Wishbone interface write enable
   166 wire   D_WE_O;
   167 output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type 
   168 wire   [`LM32_CTYPE_RNG] D_CTI_O;
   169 output D_LOCK_O;                                // Date Wishbone interface lock bus
   170 wire   D_LOCK_O;
   171 output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
   172 wire   [`LM32_BTYPE_RNG] D_BTE_O;
   174 /////////////////////////////////////////////////////
   175 // Internal nets and registers 
   176 /////////////////////////////////////////////////////
   178 `ifdef CFG_JTAG_ENABLED
   179 // Signals between JTAG interface and CPU
   180 wire [`LM32_BYTE_RNG] jtag_reg_d;
   181 wire [`LM32_BYTE_RNG] jtag_reg_q;
   182 wire jtag_update;
   183 wire [2:0] jtag_reg_addr_d;
   184 wire [2:0] jtag_reg_addr_q;
   185 wire jtck;
   186 wire jrstn;
   187 `endif
   189 // TODO: get the trace signals out
   190 `ifdef CFG_TRACE_ENABLED
   191 // PC trace signals
   192 wire [`LM32_PC_RNG] trace_pc;                   // PC to trace (address of next non-sequential instruction)
   193 wire trace_pc_valid;                            // Indicates that a new trace PC is valid
   194 wire trace_exception;                           // Indicates an exception has occured
   195 wire [`LM32_EID_RNG] trace_eid;                 // Indicates what type of exception has occured
   196 wire trace_eret;                                // Indicates an eret instruction has been executed
   197 `ifdef CFG_DEBUG_ENABLED
   198 wire trace_bret;                                // Indicates a bret instruction has been executed
   199 `endif
   200 `endif
   202 /////////////////////////////////////////////////////
   203 // Functions
   204 /////////////////////////////////////////////////////
   206 `include "lm32_functions.v"
   207 /////////////////////////////////////////////////////
   208 // Instantiations
   209 ///////////////////////////////////////////////////// 
   211 // LM32 CPU
   212 lm32_cpu cpu (
   213     // ----- Inputs -------
   214     .clk_i                 (clk_i),
   215 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
   216     .clk_n_i               (clk_n),
   217 `endif
   218     .rst_i                 (rst_i),
   219     // From external devices
   220 `ifdef CFG_INTERRUPTS_ENABLED
   221     .interrupt             (interrupt),
   222 `endif
   223     // From user logic
   224 `ifdef CFG_USER_ENABLED
   225     .user_result           (user_result),
   226     .user_complete         (user_complete),
   227 `endif     
   228 `ifdef CFG_JTAG_ENABLED
   229     // From JTAG
   230     .jtag_clk              (jtck),
   231     .jtag_update           (jtag_update),
   232     .jtag_reg_q            (jtag_reg_q),
   233     .jtag_reg_addr_q       (jtag_reg_addr_q),
   234 `endif
   235 `ifdef CFG_IWB_ENABLED
   236      // Instruction Wishbone master
   237     .I_DAT_I               (I_DAT_I),
   238     .I_ACK_I               (I_ACK_I),
   239     .I_ERR_I               (I_ERR_I),
   240     .I_RTY_I               (I_RTY_I),
   241 `endif
   242     // Data Wishbone master
   243     .D_DAT_I               (D_DAT_I),
   244     .D_ACK_I               (D_ACK_I),
   245     .D_ERR_I               (D_ERR_I),
   246     .D_RTY_I               (D_RTY_I),
   247     // ----- Outputs -------
   248 `ifdef CFG_TRACE_ENABLED
   249     .trace_pc              (trace_pc),
   250     .trace_pc_valid        (trace_pc_valid),
   251     .trace_exception       (trace_exception),
   252     .trace_eid             (trace_eid),
   253     .trace_eret            (trace_eret),
   254 `ifdef CFG_DEBUG_ENABLED
   255     .trace_bret            (trace_bret),
   256 `endif
   257 `endif
   258 `ifdef CFG_JTAG_ENABLED
   259     .jtag_reg_d            (jtag_reg_d),
   260     .jtag_reg_addr_d       (jtag_reg_addr_d),
   261 `endif
   262 `ifdef CFG_USER_ENABLED    
   263     .user_valid            (user_valid),
   264     .user_opcode           (user_opcode),
   265     .user_operand_0        (user_operand_0),
   266     .user_operand_1        (user_operand_1),
   267 `endif    
   268 `ifdef CFG_IWB_ENABLED
   269     // Instruction Wishbone master
   270     .I_DAT_O               (I_DAT_O),
   271     .I_ADR_O               (I_ADR_O),
   272     .I_CYC_O               (I_CYC_O),
   273     .I_SEL_O               (I_SEL_O),
   274     .I_STB_O               (I_STB_O),
   275     .I_WE_O                (I_WE_O),
   276     .I_CTI_O               (I_CTI_O),
   277     .I_LOCK_O              (I_LOCK_O),
   278     .I_BTE_O               (I_BTE_O),
   279     `endif
   280     // Data Wishbone master
   281     .D_DAT_O               (D_DAT_O),
   282     .D_ADR_O               (D_ADR_O),
   283     .D_CYC_O               (D_CYC_O),
   284     .D_SEL_O               (D_SEL_O),
   285     .D_STB_O               (D_STB_O),
   286     .D_WE_O                (D_WE_O),
   287     .D_CTI_O               (D_CTI_O),
   288     .D_LOCK_O              (D_LOCK_O),
   289     .D_BTE_O               (D_BTE_O)
   290     );
   292    wire TRACE_ACK_O;
   293    wire [`LM32_WORD_RNG] TRACE_DAT_O;
   294 `ifdef CFG_TRACE_ENABLED
   295    lm32_trace trace_module (.clk_i	(clk_i),
   296 			    .rst_i	(rst_i),
   297 			    .stb_i	(DEBUG_STB_I & DEBUG_ADR_I[13]),
   298 			    .we_i	(DEBUG_WE_I),
   299 			    .sel_i	(DEBUG_SEL_I),
   300 			    .dat_i	(DEBUG_DAT_I),
   301 			    .adr_i	(DEBUG_ADR_I),
   302 			    .trace_pc	(trace_pc),
   303 			    .trace_eid	(trace_eid),
   304 			    .trace_eret (trace_eret),
   305 			    .trace_bret (trace_bret),
   306 			    .trace_pc_valid (trace_pc_valid),
   307 			    .trace_exception (trace_exception),
   308 			    .ack_o	(TRACE_ACK_O),
   309 			    .dat_o 	(TRACE_DAT_O));   
   310 `else
   311    assign 		 TRACE_ACK_O = 0;
   312    assign 		 TRACE_DAT_O = 0;   
   313 `endif   
   314 `ifdef DEBUG_ROM
   315    wire ROM_ACK_O;
   316    wire [`LM32_WORD_RNG] ROM_DAT_O;
   318    assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O;
   319    assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O;
   321    // ROM monitor
   322    lm32_monitor debug_rom (
   323 			   // ----- Inputs -------
   324 			   .clk_i                 (clk_i),
   325 			   .rst_i                 (rst_i),
   326 			   .MON_ADR_I             (DEBUG_ADR_I[10:2]),
   327 			   .MON_STB_I             (DEBUG_STB_I & ~DEBUG_ADR_I[13]),
   328 			   .MON_CYC_I             (DEBUG_CYC_I & ~DEBUG_ADR_I[13]),
   329 			   .MON_WE_I              (DEBUG_WE_I),
   330 			   .MON_SEL_I             (DEBUG_SEL_I),
   331 			   .MON_DAT_I             (DEBUG_DAT_I),
   332 			   // ----- Outputs ------    
   333 			   .MON_RTY_O             (DEBUG_RTY_O),
   334 			   .MON_ERR_O             (DEBUG_ERR_O),
   335 			   .MON_ACK_O             (ROM_ACK_O),
   336 			   .MON_DAT_O             (ROM_DAT_O)
   337 			   );
   338 `endif 
   340 `ifdef CFG_JTAG_ENABLED		   
   341 // JTAG cores 
   342 jtag_cores jtag_cores (
   343     // ----- Inputs -----
   344     .reg_d                 (jtag_reg_d),
   345     .reg_addr_d            (jtag_reg_addr_d),
   346     // ----- Outputs -----
   347     .reg_update            (jtag_update),
   348     .reg_q                 (jtag_reg_q),
   349     .reg_addr_q            (jtag_reg_addr_q),
   350     .jtck                  (jtck),
   351     .jrstn                 (jrstn)
   352     );
   353 `endif        
   355 endmodule