Sat, 06 Aug 2011 00:02:46 +0100
[UPSTREAM PULL] Update baseline to LatticeMico32 v3.8 from Diamond 1.3-lm32 distribution package (datestamp May 2011)
1 // ==================================================================
2 // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 // ------------------------------------------------------------------
4 // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
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6 // ------------------------------------------------------------------
7 //
8 // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 //
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11 //
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14 // Open Source License Agreement.
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17 //
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21 // the use of formal verification methods.
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36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_debug.v
40 // Title : Hardware debug registers and associated logic.
41 // Dependencies : lm32_include.v
42 // Version : 6.1.17
43 // : Initial Release
44 // Version : 7.0SP2, 3.0
45 // : No Change
46 // Version : 3.1
47 // : No Change
48 // Version : 3.2
49 // : Fixed simulation bug which flares up when number of
50 // : watchpoints is zero.
51 // =============================================================================
53 `include "lm32_include.v"
55 `ifdef CFG_DEBUG_ENABLED
57 // States for single-step FSM
58 `define LM32_DEBUG_SS_STATE_RNG 2:0
59 `define LM32_DEBUG_SS_STATE_IDLE 3'b000
60 `define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001
61 `define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010
62 `define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011
63 `define LM32_DEBUG_SS_STATE_RESTART 3'b100
65 /////////////////////////////////////////////////////
66 // Module interface
67 /////////////////////////////////////////////////////
69 module lm32_debug (
70 // ----- Inputs -------
71 clk_i,
72 rst_i,
73 pc_x,
74 load_x,
75 store_x,
76 load_store_address_x,
77 csr_write_enable_x,
78 csr_write_data,
79 csr_x,
80 `ifdef CFG_HW_DEBUG_ENABLED
81 jtag_csr_write_enable,
82 jtag_csr_write_data,
83 jtag_csr,
84 `endif
85 `ifdef LM32_SINGLE_STEP_ENABLED
86 eret_q_x,
87 bret_q_x,
88 stall_x,
89 exception_x,
90 q_x,
91 `ifdef CFG_DCACHE_ENABLED
92 dcache_refill_request,
93 `endif
94 `endif
95 // ----- Outputs -------
96 `ifdef LM32_SINGLE_STEP_ENABLED
97 dc_ss,
98 `endif
99 dc_re,
100 bp_match,
101 wp_match
102 );
104 /////////////////////////////////////////////////////
105 // Parameters
106 /////////////////////////////////////////////////////
108 parameter breakpoints = 0; // Number of breakpoint CSRs
109 parameter watchpoints = 0; // Number of watchpoint CSRs
111 /////////////////////////////////////////////////////
112 // Inputs
113 /////////////////////////////////////////////////////
115 input clk_i; // Clock
116 input rst_i; // Reset
118 input [`LM32_PC_RNG] pc_x; // X stage PC
119 input load_x; // Load instruction in X stage
120 input store_x; // Store instruction in X stage
121 input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address
122 input csr_write_enable_x; // wcsr instruction in X stage
123 input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR
124 input [`LM32_CSR_RNG] csr_x; // Which CSR to write
125 `ifdef CFG_HW_DEBUG_ENABLED
126 input jtag_csr_write_enable; // JTAG interface CSR write enable
127 input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR
128 input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
129 `endif
130 `ifdef LM32_SINGLE_STEP_ENABLED
131 input eret_q_x; // eret instruction in X stage
132 input bret_q_x; // bret instruction in X stage
133 input stall_x; // Instruction in X stage is stalled
134 input exception_x; // An exception has occured in X stage
135 input q_x; // Indicates the instruction in the X stage is qualified
136 `ifdef CFG_DCACHE_ENABLED
137 input dcache_refill_request; // Indicates data cache wants to be refilled
138 `endif
139 `endif
141 /////////////////////////////////////////////////////
142 // Outputs
143 /////////////////////////////////////////////////////
145 `ifdef LM32_SINGLE_STEP_ENABLED
146 output dc_ss; // Single-step enable
147 reg dc_ss;
148 `endif
149 output dc_re; // Remap exceptions
150 reg dc_re;
151 output bp_match; // Indicates a breakpoint has matched
152 wire bp_match;
153 output wp_match; // Indicates a watchpoint has matched
154 wire wp_match;
156 /////////////////////////////////////////////////////
157 // Internal nets and registers
158 /////////////////////////////////////////////////////
160 genvar i; // Loop index for generate statements
162 // Debug CSRs
164 reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address
165 reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable
166 wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched
168 reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable
169 reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address
170 wire [0:watchpoints]wp_match_n; // Indicates if a h/w data watchpoint matched
172 wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger)
173 wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR
174 wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to
176 `ifdef LM32_SINGLE_STEP_ENABLED
177 // FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
178 //reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM
179 integer state; // State of single-step FSM
180 `endif
182 /////////////////////////////////////////////////////
183 // Functions
184 /////////////////////////////////////////////////////
186 `include "lm32_functions.v"
188 /////////////////////////////////////////////////////
189 // Combinational Logic
190 /////////////////////////////////////////////////////
192 // Check for breakpoints
193 generate
194 for (i = 0; i < breakpoints; i = i + 1)
195 begin : bp_comb
196 assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
197 end
198 endgenerate
199 generate
200 `ifdef LM32_SINGLE_STEP_ENABLED
201 if (breakpoints > 0)
202 assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
203 else
204 assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
205 `else
206 if (breakpoints > 0)
207 assign bp_match = |bp_match_n;
208 else
209 assign bp_match = `FALSE;
210 `endif
211 endgenerate
213 // Check for watchpoints
214 generate
215 for (i = 0; i < watchpoints; i = i + 1)
216 begin : wp_comb
217 assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
218 end
219 endgenerate
220 generate
221 if (watchpoints > 0)
222 assign wp_match = |wp_match_n;
223 else
224 assign wp_match = `FALSE;
225 endgenerate
227 `ifdef CFG_HW_DEBUG_ENABLED
228 // Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
229 assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
230 assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
231 assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
232 `else
233 assign debug_csr_write_enable = csr_write_enable_x;
234 assign debug_csr_write_data = csr_write_data;
235 assign debug_csr = csr_x;
236 `endif
238 /////////////////////////////////////////////////////
239 // Sequential Logic
240 /////////////////////////////////////////////////////
242 // Breakpoint address and enable CSRs
243 generate
244 for (i = 0; i < breakpoints; i = i + 1)
245 begin : bp_seq
246 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
247 begin
248 if (rst_i == `TRUE)
249 begin
250 bp_a[i] <= #1 {`LM32_PC_WIDTH{1'bx}};
251 bp_e[i] <= #1 `FALSE;
252 end
253 else
254 begin
255 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
256 begin
257 bp_a[i] <= #1 debug_csr_write_data[`LM32_PC_RNG];
258 bp_e[i] <= #1 debug_csr_write_data[0];
259 end
260 end
261 end
262 end
263 endgenerate
265 // Watchpoint address and control flags CSRs
266 generate
267 for (i = 0; i < watchpoints; i = i + 1)
268 begin : wp_seq
269 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
270 begin
271 if (rst_i == `TRUE)
272 begin
273 wp[i] <= #1 {`LM32_WORD_WIDTH{1'bx}};
274 wpc_c[i] <= #1 `LM32_WPC_C_DISABLED;
275 end
276 else
277 begin
278 if (debug_csr_write_enable == `TRUE)
279 begin
280 if (debug_csr == `LM32_CSR_DC)
281 wpc_c[i] <= #1 debug_csr_write_data[3+i*2:2+i*2];
282 if (debug_csr == `LM32_CSR_WP0 + i)
283 wp[i] <= #1 debug_csr_write_data;
284 end
285 end
286 end
287 end
288 endgenerate
290 // Remap exceptions control bit
291 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
292 begin
293 if (rst_i == `TRUE)
294 dc_re <= #1 `FALSE;
295 else
296 begin
297 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
298 dc_re <= #1 debug_csr_write_data[1];
299 end
300 end
302 `ifdef LM32_SINGLE_STEP_ENABLED
303 // Single-step control flag
304 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
305 begin
306 if (rst_i == `TRUE)
307 begin
308 state <= #1 `LM32_DEBUG_SS_STATE_IDLE;
309 dc_ss <= #1 `FALSE;
310 end
311 else
312 begin
313 if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
314 begin
315 dc_ss <= #1 debug_csr_write_data[0];
316 if (debug_csr_write_data[0] == `FALSE)
317 state <= #1 `LM32_DEBUG_SS_STATE_IDLE;
318 else
319 state <= #1 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
320 end
321 case (state)
322 `LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
323 begin
324 // Wait for eret or bret instruction to be executed
325 if ( ( (eret_q_x == `TRUE)
326 || (bret_q_x == `TRUE)
327 )
328 && (stall_x == `FALSE)
329 )
330 state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
331 end
332 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
333 begin
334 // Wait for an instruction to be executed
335 if ((q_x == `TRUE) && (stall_x == `FALSE))
336 state <= #1 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
337 end
338 `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
339 begin
340 // Wait for exception to be raised
341 `ifdef CFG_DCACHE_ENABLED
342 if (dcache_refill_request == `TRUE)
343 state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
344 else
345 `endif
346 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
347 begin
348 dc_ss <= #1 `FALSE;
349 state <= #1 `LM32_DEBUG_SS_STATE_RESTART;
350 end
351 end
352 `LM32_DEBUG_SS_STATE_RESTART:
353 begin
354 // Watch to see if stepped instruction is restarted due to a cache miss
355 `ifdef CFG_DCACHE_ENABLED
356 if (dcache_refill_request == `TRUE)
357 state <= #1 `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
358 else
359 `endif
360 state <= #1 `LM32_DEBUG_SS_STATE_IDLE;
361 end
362 endcase
363 end
364 end
365 `endif
367 endmodule
369 `endif