Sat, 06 Aug 2011 00:02:46 +0100
[UPSTREAM PULL] Update baseline to LatticeMico32 v3.8 from Diamond 1.3-lm32 distribution package (datestamp May 2011)
1 // ==================================================================
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11 //
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17 //
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36 // --------------------------------------------------------------------
37 // FILE DETAILS
38 // Project : LatticeMico32
39 // File : lm32_monitor.v
40 // Title : Debug monitor memory Wishbone interface
41 // Version : 6.1.17
42 // : Initial Release
43 // Version : 7.0SP2, 3.0
44 // : No Change
45 // Version : 3.3
46 // : Removed port mismatch in instantiation of module
47 // : lm32_monitor_ram.
48 // =============================================================================
50 `include "system_conf.v"
51 `include "lm32_include.v"
53 /////////////////////////////////////////////////////
54 // Module interface
55 /////////////////////////////////////////////////////
57 module lm32_monitor (
58 // ----- Inputs -------
59 clk_i,
60 rst_i,
61 MON_ADR_I,
62 MON_CYC_I,
63 MON_DAT_I,
64 MON_SEL_I,
65 MON_STB_I,
66 MON_WE_I,
67 // ----- Outputs -------
68 MON_ACK_O,
69 MON_RTY_O,
70 MON_DAT_O,
71 MON_ERR_O
72 );
74 /////////////////////////////////////////////////////
75 // Inputs
76 /////////////////////////////////////////////////////
78 input clk_i; // Wishbone clock
79 input rst_i; // Wishbone reset
80 input [10:2] MON_ADR_I; // Wishbone address
81 input MON_STB_I; // Wishbone strobe
82 input MON_CYC_I; // Wishbone cycle
83 input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data
84 input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select
85 input MON_WE_I; // Wishbone write enable
87 /////////////////////////////////////////////////////
88 // Outputs
89 /////////////////////////////////////////////////////
91 output MON_ACK_O; // Wishbone acknowlege
92 reg MON_ACK_O;
93 output [`LM32_WORD_RNG] MON_DAT_O; // Wishbone data output
94 reg [`LM32_WORD_RNG] MON_DAT_O;
95 output MON_RTY_O; // Wishbone retry
96 wire MON_RTY_O;
97 output MON_ERR_O; // Wishbone error
98 wire MON_ERR_O;
100 /////////////////////////////////////////////////////
101 // Internal nets and registers
102 /////////////////////////////////////////////////////
104 reg [1:0] state; // Current state of FSM
105 wire [`LM32_WORD_RNG] data, dataB; // Data read from RAM
106 reg write_enable; // RAM write enable
107 reg [`LM32_WORD_RNG] write_data; // RAM write data
109 /////////////////////////////////////////////////////
110 // Instantiations
111 /////////////////////////////////////////////////////
113 lm32_monitor_ram ram (
114 // ----- Inputs -------
115 .ClockA (clk_i),
116 .ClockB (clk_i),
117 .ResetA (rst_i),
118 .ResetB (rst_i),
119 .ClockEnA (`TRUE),
120 .ClockEnB (`FALSE),
121 .AddressA (MON_ADR_I[10:2]),
122 .AddressB (9'b0),
123 .DataInA (write_data),
124 .DataInB (32'b0),
125 .WrA (write_enable),
126 .WrB (`FALSE),
127 // ----- Outputs -------
128 .QA (data),
129 .QB (dataB)
130 );
132 /////////////////////////////////////////////////////
133 // Combinational Logic
134 /////////////////////////////////////////////////////
136 assign MON_RTY_O = `FALSE;
137 assign MON_ERR_O = `FALSE;
139 /////////////////////////////////////////////////////
140 // Sequential Logic
141 /////////////////////////////////////////////////////
143 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
144 begin
145 if (rst_i == `TRUE)
146 begin
147 write_enable <= #1 `FALSE;
148 MON_ACK_O <= #1 `FALSE;
149 MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}};
150 state <= #1 2'b00;
151 end
152 else
153 begin
154 casez (state)
155 2'b01:
156 begin
157 // Output read data to Wishbone
158 MON_ACK_O <= #1 `TRUE;
159 MON_DAT_O <= #1 data;
160 // Sub-word writes are performed using read-modify-write
161 // as the Lattice EBRs don't support byte enables
162 if (MON_WE_I == `TRUE)
163 write_enable <= #1 `TRUE;
164 write_data[7:0] <= #1 MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
165 write_data[15:8] <= #1 MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
166 write_data[23:16] <= #1 MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
167 write_data[31:24] <= #1 MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
168 state <= #1 2'b10;
169 end
170 2'b10:
171 begin
172 // Wishbone access occurs in this cycle
173 write_enable <= #1 `FALSE;
174 MON_ACK_O <= #1 `FALSE;
175 MON_DAT_O <= #1 {`LM32_WORD_WIDTH{1'bx}};
176 state <= #1 2'b00;
177 end
178 default:
179 begin
180 write_enable <= #1 `FALSE;
181 MON_ACK_O <= #1 `FALSE;
182 // Wait for a Wishbone access
183 if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
184 state <= #1 2'b01;
185 end
186 endcase
187 end
188 end
190 endmodule