typea.v

Sat, 06 Aug 2011 00:02:46 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 00:02:46 +0100
changeset 26
73de224304c1
parent 0
cd0b58aa6f83
child 27
d6c693415d59
permissions
-rwxr-xr-x

[UPSTREAM PULL] Update baseline to LatticeMico32 v3.8 from Diamond 1.3-lm32 distribution package (datestamp May 2011)

     1 //   ==================================================================
     2 //   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     3 //   ------------------------------------------------------------------
     4 //   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
     5 //   ALL RIGHTS RESERVED 
     6 //   ------------------------------------------------------------------
     7 //
     8 //   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
     9 //
    10 //   Permission:
    11 //
    12 //      Lattice Semiconductor grants permission to use this code
    13 //      pursuant to the terms of the Lattice Semiconductor Corporation
    14 //      Open Source License Agreement.  
    15 //
    16 //   Disclaimer:
    17 //
    18 //      Lattice Semiconductor provides no warranty regarding the use or
    19 //      functionality of this code. It is the user's responsibility to
    20 //      verify the userís design for consistency and functionality through
    21 //      the use of formal verification methods.
    22 //
    23 //   --------------------------------------------------------------------
    24 //
    25 //                  Lattice Semiconductor Corporation
    26 //                  5555 NE Moore Court
    27 //                  Hillsboro, OR 97214
    28 //                  U.S.A
    29 //
    30 //                  TEL: 1-800-Lattice (USA and Canada)
    31 //                         503-286-8001 (other locations)
    32 //
    33 //                  web: http://www.latticesemi.com/
    34 //                  email: techsupport@latticesemi.com
    35 //
    36 //   --------------------------------------------------------------------
    37 //                         FILE DETAILS
    38 // Project          : LatticeMico32
    39 // File             : TYPEA.v
    40 // Description:
    41 //    This is one of the two types of cells that are used to create ER1/ER2
    42 //    register bits.
    43 // Dependencies     : None
    44 // Version          : 6.1.17
    45 //   The SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 signals of the
    46 //   dedicate logic JTAG_PORT didn't act as what their names implied.
    47 //   The SHIFT_DR_CAPTURE_DR actually acts as SHIFT_DR.
    48 //   The ENABLE_ER1/2 actually acts as SHIFT_DR_CAPTURE_DR.
    49 //   These had caused a lot of headaches for a long time and now they are
    50 //   fixed by:
    51 //   (1) Use SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 to create
    52 //       CAPTURE_DR for all typeA, typeB bits in the ER1, ER2 registers.
    53 //   (2) Use ENABLE_ER1 or the enESR, enCSR, enBAR (these 3 signals
    54 //       have the same waveform of ENABLE_ER2) directly to be the CLKEN
    55 //       of all typeA, typeB bits in the ER1, ER2 registers.
    56 //   (3) Modify typea.vhd to use only UPDATE_DR signal for the clock enable
    57 //       of the holding flip-flop.
    58 //   These changes caused ispTracy.vhd and cge.dat changes and the new
    59 //   CGE.exe version will be 1.3.5.
    60 // Version          : 7.0SP2, 3.0
    61 //                  : No Change
    62 // Version          : 3.1
    63 //                  : No Change
    64 // =============================================================================
    65 module TYPEA(
    66       input CLK,
    67       input RESET_N,
    68       input CLKEN,
    69       input TDI,
    70       output TDO,
    71       output reg DATA_OUT,
    72       input DATA_IN,
    73       input CAPTURE_DR,
    74       input UPDATE_DR
    75    );
    77   reg tdoInt;
    80   always @ (negedge CLK or negedge RESET_N)
    81   begin
    82       if (RESET_N == 1'b0)
    83          tdoInt <= #1 1'b0;
    84       else if (CLK == 1'b0)
    85          if (CLKEN == 1'b1)
    86             if (CAPTURE_DR == 1'b0)
    87                tdoInt <= #1 TDI;
    88             else
    89                tdoInt <= #1 DATA_IN;
    90   end
    92    assign TDO = tdoInt;
    94   always @ (negedge CLK or negedge RESET_N)
    95    begin
    96       if (RESET_N == 1'b0)
    97          DATA_OUT <= #1 1'b0;
    98       else if (CLK == 1'b0)
    99          if (UPDATE_DR == 1'b1)
   100             DATA_OUT <= #1 tdoInt;
   101    end
   102 endmodule