jtag_cores.v

Mon, 05 Apr 2010 20:23:04 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Mon, 05 Apr 2010 20:23:04 +0100
changeset 4
99b7b037ce82
parent 0
cd0b58aa6f83
child 14
54dd95f89113
child 26
73de224304c1
permissions
-rw-r--r--

add better comment re Xilinx Xst cache issues

     1 // ============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // ============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : jtag_cores.v
    19 // Title            : Instantiates all IP cores on JTAG chain.
    20 // Dependencies     : system_conf.v
    21 // Version          : 6.0.14
    22 //                  : modified to use jtagconn for LM32,
    23 //                  : all technologies 7/10/07
    24 // Version          : 7.0SP2, 3.0
    25 //                  : No Change
    26 // Version          : 3.1
    27 //                  : No Change
    28 // ============================================================================
    30 `include "system_conf.v"
    32 /////////////////////////////////////////////////////
    33 // jtagconn16 Module Definition
    34 /////////////////////////////////////////////////////
    36 module jtagconn16 (er2_tdo, jtck, jtdi, jshift, jupdate, jrstn, jce2, ip_enable) ;
    37     input  er2_tdo ; 
    38     output jtck ; 
    39     output jtdi ; 
    40     output jshift ; 
    41     output jupdate ; 
    42     output jrstn ; 
    43     output jce2 ; 
    44     output ip_enable ; 
    45 endmodule
    47 /////////////////////////////////////////////////////
    48 // Module interface
    49 /////////////////////////////////////////////////////
    51 (* syn_hier="hard" *) module jtag_cores (
    52     // ----- Inputs -------
    53     reg_d,
    54     reg_addr_d,
    55     // ----- Outputs -------    
    56     reg_update,
    57     reg_q,
    58     reg_addr_q,
    59     jtck,
    60     jrstn
    61     );
    63 /////////////////////////////////////////////////////
    64 // Inputs
    65 /////////////////////////////////////////////////////
    67 input [7:0] reg_d;
    68 input [2:0] reg_addr_d;
    70 /////////////////////////////////////////////////////
    71 // Outputs
    72 /////////////////////////////////////////////////////
    74 output reg_update;
    75 wire   reg_update;
    76 output [7:0] reg_q;
    77 wire   [7:0] reg_q;
    78 output [2:0] reg_addr_q;
    79 wire   [2:0] reg_addr_q;
    81 output jtck;
    82 wire   jtck; 	/* synthesis syn_keep=1 */
    83 output jrstn;
    84 wire   jrstn;  /* synthesis syn_keep=1 */	
    86 /////////////////////////////////////////////////////
    87 // Instantiations
    88 /////////////////////////////////////////////////////
    90 wire jtdi;          /* synthesis syn_keep=1 */
    91 wire er2_tdo2;      /* synthesis syn_keep=1 */
    92 wire jshift;        /* synthesis syn_keep=1 */
    93 wire jupdate;       /* synthesis syn_keep=1 */
    94 wire jce2;          /* synthesis syn_keep=1 */
    95 wire ip_enable;     /* synthesis syn_keep=1 */
    97 (* JTAG_IP="LM32", IP_ID="0", HUB_ID="0", syn_noprune=1 *) jtagconn16 jtagconn16_lm32_inst (
    98     .er2_tdo        (er2_tdo2),
    99     .jtck           (jtck),
   100     .jtdi           (jtdi),
   101     .jshift         (jshift),
   102     .jupdate        (jupdate),
   103     .jrstn          (jrstn),
   104     .jce2           (jce2),
   105     .ip_enable      (ip_enable)
   106 );
   108 (* syn_noprune=1 *) jtag_lm32 jtag_lm32_inst (
   109     .JTCK           (jtck),
   110     .JTDI           (jtdi),
   111     .JTDO2          (er2_tdo2),
   112     .JSHIFT         (jshift),
   113     .JUPDATE        (jupdate),
   114     .JRSTN          (jrstn),
   115     .JCE2           (jce2),
   116     .JTAGREG_ENABLE (ip_enable),
   117     .CONTROL_DATAN  (),
   118     .REG_UPDATE     (reg_update),
   119     .REG_D          (reg_d),
   120     .REG_ADDR_D     (reg_addr_d),
   121     .REG_Q          (reg_q),
   122     .REG_ADDR_Q     (reg_addr_q)
   123     );
   125 endmodule