lm32_include.v

Mon, 05 Apr 2010 20:23:04 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Mon, 05 Apr 2010 20:23:04 +0100
changeset 4
99b7b037ce82
parent 1
ae6035050124
child 5
35ebde37101f
permissions
-rw-r--r--

add better comment re Xilinx Xst cache issues

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : lm32_include.v
    19 // Title            : CPU global macros
    20 // Version          : 6.1.17
    21 //                  : Initial Release
    22 // Version          : 7.0SP2, 3.0
    23 //                  : No Change
    24 // Version          : 3.1
    25 //                  : No Change
    26 // Version          : 3.2
    27 //                  : No Change
    28 // Version          : 3.3
    29 //                  : Support for extended configuration register
    30 // =============================================================================
    32 `ifdef LM32_INCLUDE_V
    33 `else
    34 `define LM32_INCLUDE_V
    36 // (config opts from http://www.reflextor.org/trac/a51/browser/fpga/main/cores/lm32/rtl/lm32_include.v?rev=20)
    37 //
    38 // Common configuration options
    39 //
    41 `define CFG_EBA_RESET 32'h0
    42 `define CFG_DEBA_RESET 32'h0
    44 `define CFG_PL_MULTIPLY_ENABLED
    45 `define CFG_PL_BARREL_SHIFT_ENABLED
    46 `define CFG_SIGN_EXTEND_ENABLED
    47 `define CFG_MC_DIVIDE_ENABLED
    49 // [found by Milkymist dev'rs]
    50 // Bug in Xst:
    51 // CFG_ICACHE_ASSOCIATIVITY=2 => works in most cases (random crash on complex software)
    52 // CFG_ICACHE_ASSOCIATIVITY=1 => disaster, CPU will not work at all
    53 // Works 100% OK with expensive synthesizers.
    54 `define CFG_ICACHE_ENABLED
    55 `define CFG_ICACHE_ASSOCIATIVITY   2
    56 `define CFG_ICACHE_SETS            512
    57 `define CFG_ICACHE_BYTES_PER_LINE  16
    58 `define CFG_ICACHE_BASE_ADDRESS    32'h0
    59 `define CFG_ICACHE_LIMIT           32'h7fffffff
    61 `define CFG_DCACHE_ENABLED
    62 `define CFG_DCACHE_ASSOCIATIVITY   2
    63 `define CFG_DCACHE_SETS            512
    64 `define CFG_DCACHE_BYTES_PER_LINE  16
    65 `define CFG_DCACHE_BASE_ADDRESS    32'h0
    66 `define CFG_DCACHE_LIMIT           32'h7fffffff
    68 //
    69 // End of common configuration options
    70 //
    72 `ifdef TRUE
    73 `else
    74 `define TRUE    1'b1
    75 `define FALSE   1'b0
    76 `define TRUE_N  1'b0
    77 `define FALSE_N 1'b1
    78 `endif
    80 // Wishbone configuration
    81 `define CFG_IWB_ENABLED
    82 `define CFG_DWB_ENABLED
    84 // Data-path width
    85 `define LM32_WORD_WIDTH                 32
    86 `define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
    87 `define LM32_SHIFT_WIDTH                5
    88 `define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
    89 `define LM32_BYTE_SELECT_WIDTH          4
    90 `define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
    92 // Register file size
    93 `define LM32_REGISTERS                  32
    94 `define LM32_REG_IDX_WIDTH              5
    95 `define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
    97 // Standard register numbers
    98 `define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
    99 `define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
   100 `define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
   102 // Range of Program Counter. Two LSBs are always 0. 
   103 // `ifdef CFG_ICACHE_ENABLED
   104 // `define LM32_PC_WIDTH                   (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
   105 // `else
   106 // `ifdef CFG_IWB_ENABLED
   107 `define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
   108 // `else
   109 // `define LM32_PC_WIDTH                   `LM32_IROM_ADDRESS_WIDTH
   110 // `endif
   111 // `endif
   112 `define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
   114 // Range of an instruction
   115 `define LM32_INSTRUCTION_WIDTH          32
   116 `define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
   118 // Adder operation
   119 `define LM32_ADDER_OP_ADD               1'b0
   120 `define LM32_ADDER_OP_SUBTRACT          1'b1
   122 // Shift direction
   123 `define LM32_SHIFT_OP_RIGHT             1'b0
   124 `define LM32_SHIFT_OP_LEFT              1'b1
   126 // Currently always enabled
   127 `define CFG_BUS_ERRORS_ENABLED
   129 // Derive macro that indicates whether we have single-stepping or not
   130 `ifdef CFG_ROM_DEBUG_ENABLED
   131 `define LM32_SINGLE_STEP_ENABLED
   132 `else
   133 `ifdef CFG_HW_DEBUG_ENABLED
   134 `define LM32_SINGLE_STEP_ENABLED
   135 `endif
   136 `endif
   138 // Derive macro that indicates whether JTAG interface is required
   139 `ifdef CFG_JTAG_UART_ENABLED
   140 `define LM32_JTAG_ENABLED
   141 `else
   142 `ifdef CFG_DEBUG_ENABLED
   143 `define LM32_JTAG_ENABLED
   144 `else
   145 `endif
   146 `endif
   148 // Derive macro that indicates whether we have a barrel-shifter or not
   149 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   150 `define LM32_BARREL_SHIFT_ENABLED
   151 `else // CFG_PL_BARREL_SHIFT_ENABLED
   152 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   153 `define LM32_BARREL_SHIFT_ENABLED
   154 `else
   155 `define LM32_NO_BARREL_SHIFT
   156 `endif
   157 `endif // CFG_PL_BARREL_SHIFT_ENABLED
   159 // Derive macro that indicates whether we have a multiplier or not
   160 `ifdef CFG_PL_MULTIPLY_ENABLED
   161 `define LM32_MULTIPLY_ENABLED
   162 `else
   163 `ifdef CFG_MC_MULTIPLY_ENABLED
   164 `define LM32_MULTIPLY_ENABLED
   165 `endif
   166 `endif
   168 // Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
   169 `ifdef CFG_MC_DIVIDE_ENABLED
   170 `define LM32_MC_ARITHMETIC_ENABLED
   171 `endif
   172 `ifdef CFG_MC_MULTIPLY_ENABLED
   173 `define LM32_MC_ARITHMETIC_ENABLED
   174 `endif
   175 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   176 `define LM32_MC_ARITHMETIC_ENABLED
   177 `endif
   179 // Derive macro that indicates if we are using an EBR register file
   180 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   181 `define LM32_EBR_REGISTER_FILE
   182 `endif
   183 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
   184 `define LM32_EBR_REGISTER_FILE
   185 `endif
   187 // Revision number
   188 `define LM32_REVISION                   6'h02
   190 // Logical operations - Function encoded directly in instruction
   191 `define LM32_LOGIC_OP_RNG               3:0
   193 // Conditions for conditional branches
   194 `define LM32_CONDITION_WIDTH            3
   195 `define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
   196 `define LM32_CONDITION_E                3'b001
   197 `define LM32_CONDITION_G                3'b010
   198 `define LM32_CONDITION_GE               3'b011
   199 `define LM32_CONDITION_GEU              3'b100
   200 `define LM32_CONDITION_GU               3'b101
   201 `define LM32_CONDITION_NE               3'b111
   202 `define LM32_CONDITION_U1               3'b000
   203 `define LM32_CONDITION_U2               3'b110
   205 // Size of load or store instruction - Encoding corresponds to opcode
   206 `define LM32_SIZE_WIDTH                 2
   207 `define LM32_SIZE_RNG                   1:0
   208 `define LM32_SIZE_BYTE                  2'b00
   209 `define LM32_SIZE_HWORD                 2'b11
   210 `define LM32_SIZE_WORD                  2'b10
   211 `define LM32_ADDRESS_LSBS_WIDTH         2
   213 // Width and range of a CSR index
   214 `ifdef CFG_DEBUG_ENABLED
   215 `define LM32_CSR_WIDTH                  5
   216 `define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
   217 `else
   218 `ifdef CFG_JTAG_ENABLED
   219 `define LM32_CSR_WIDTH                  4
   220 `define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
   221 `else
   222 `define LM32_CSR_WIDTH                  3
   223 `define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
   224 `endif
   225 `endif
   227 // CSR indices
   228 `define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
   229 `define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
   230 `define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
   231 `define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
   232 `define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
   233 `define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
   234 `define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
   235 `define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
   236 `ifdef CFG_DEBUG_ENABLED
   237 `define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
   238 `define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
   239 `endif
   240 `define LM32_CSR_CFG2                   `LM32_CSR_WIDTH'ha
   241 `ifdef CFG_JTAG_ENABLED
   242 `define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
   243 `define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
   244 `endif
   245 `ifdef CFG_DEBUG_ENABLED
   246 `define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
   247 `define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
   248 `define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
   249 `define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
   250 `define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
   251 `define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
   252 `define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
   253 `define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
   254 `endif 
   256 // Values for WPC CSR
   257 `define LM32_WPC_C_RNG                  1:0
   258 `define LM32_WPC_C_DISABLED             2'b00
   259 `define LM32_WPC_C_READ                 2'b01
   260 `define LM32_WPC_C_WRITE                2'b10
   261 `define LM32_WPC_C_READ_WRITE           2'b11
   263 // Exception IDs
   264 `define LM32_EID_WIDTH                  3
   265 `define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
   266 `define LM32_EID_RESET                  3'h0
   267 `define LM32_EID_BREAKPOINT             3'd1
   268 `define LM32_EID_INST_BUS_ERROR         3'h2
   269 `define LM32_EID_WATCHPOINT             3'd3
   270 `define LM32_EID_DATA_BUS_ERROR         3'h4
   271 `define LM32_EID_DIVIDE_BY_ZERO         3'h5
   272 `define LM32_EID_INTERRUPT              3'h6
   273 `define LM32_EID_SCALL                  3'h7
   275 // Pipeline result selection mux controls
   277 `define LM32_D_RESULT_SEL_0_RNG          0:0
   278 `define LM32_D_RESULT_SEL_0_REG_0        1'b0
   279 `define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
   281 `define LM32_D_RESULT_SEL_1_RNG          1:0
   282 `define LM32_D_RESULT_SEL_1_ZERO         2'b00
   283 `define LM32_D_RESULT_SEL_1_REG_1        2'b01
   284 `define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
   286 `define LM32_USER_OPCODE_WIDTH           11
   287 `define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
   289 // Derive a macro to indicate if either of the caches are implemented
   290 `ifdef CFG_ICACHE_ENABLED
   291 `define LM32_CACHE_ENABLED      
   292 `else
   293 `ifdef CFG_DCACHE_ENABLED
   294 `define LM32_CACHE_ENABLED
   295 `endif
   296 `endif
   298 /////////////////////////////////////////////////////
   299 // Interrupts
   300 /////////////////////////////////////////////////////
   302 // Always enable interrupts
   303 `define CFG_INTERRUPTS_ENABLED
   305 // Currently this is fixed to 32 and should not be changed
   306 `define CFG_INTERRUPTS                  32
   307 `define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
   308 `define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
   310 /////////////////////////////////////////////////////
   311 // General
   312 /////////////////////////////////////////////////////
   314 // Sub-word range types
   315 `define LM32_BYTE_WIDTH                 8
   316 `define LM32_BYTE_RNG                   7:0
   317 `define LM32_HWORD_WIDTH                16
   318 `define LM32_HWORD_RNG                  15:0
   320 // Word sub-byte indicies
   321 `define LM32_BYTE_0_RNG                  7:0
   322 `define LM32_BYTE_1_RNG                  15:8
   323 `define LM32_BYTE_2_RNG                  23:16
   324 `define LM32_BYTE_3_RNG                  31:24
   326 // Word sub-halfword indices
   327 `define LM32_HWORD_0_RNG                 15:0
   328 `define LM32_HWORD_1_RNG                 31:16
   330 // Use an asynchronous reset
   331 // To use a synchronous reset, define this macro as nothing
   332 `define CFG_RESET_SENSITIVITY 
   334 // V.T. Srce
   335 `define SRCE
   337 // Whether to include context registers for debug exceptions
   338 // in addition to standard exception handling registers
   339 // Bizarre - Removing this increases LUT count!
   340 `define CFG_DEBUG_EXCEPTIONS_ENABLED
   342 // Wishbone defines 
   343 // Refer to Wishbone System-on-Chip Interconnection Architecture
   344 // These should probably be moved to a Wishbone common file
   346 // Wishbone cycle types
   347 `define LM32_CTYPE_WIDTH                3
   348 `define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
   349 `define LM32_CTYPE_CLASSIC              3'b000
   350 `define LM32_CTYPE_CONSTANT             3'b001
   351 `define LM32_CTYPE_INCREMENTING         3'b010
   352 `define LM32_CTYPE_END                  3'b111
   354 // Wishbone burst types
   355 `define LM32_BTYPE_WIDTH                2
   356 `define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
   357 `define LM32_BTYPE_LINEAR               2'b00
   358 `define LM32_BTYPE_4_BEAT               2'b01
   359 `define LM32_BTYPE_8_BEAT               2'b10
   360 `define LM32_BTYPE_16_BEAT              2'b11
   362 `endif