lm32_jtag.v

Mon, 05 Apr 2010 20:23:04 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Mon, 05 Apr 2010 20:23:04 +0100
changeset 4
99b7b037ce82
parent 0
cd0b58aa6f83
child 14
54dd95f89113
child 26
73de224304c1
permissions
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add better comment re Xilinx Xst cache issues

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : lm32_jtag.v
    19 // Title            : JTAG interface
    20 // Dependencies     : lm32_include.v
    21 // Version          : 6.1.17
    22 //                  : Initial Release
    23 // Version          : 7.0SP2, 3.0
    24 //                  : No Change
    25 // Version          : 3.1
    26 //                  : No Change
    27 // =============================================================================
    29 `include "lm32_include.v"
    31 `ifdef CFG_JTAG_ENABLED
    33 `define LM32_DP                             3'b000
    34 `define LM32_TX                             3'b001
    35 `define LM32_RX                             3'b010
    37 // LM32 Debug Protocol commands IDs
    38 `define LM32_DP_RNG                         3:0
    39 `define LM32_DP_READ_MEMORY                 4'b0001
    40 `define LM32_DP_WRITE_MEMORY                4'b0010
    41 `define LM32_DP_READ_SEQUENTIAL             4'b0011
    42 `define LM32_DP_WRITE_SEQUENTIAL            4'b0100
    43 `define LM32_DP_WRITE_CSR                   4'b0101
    44 `define LM32_DP_BREAK                       4'b0110
    45 `define LM32_DP_RESET                       4'b0111
    47 // States for FSM
    48 `define LM32_JTAG_STATE_RNG                 3:0
    49 `define LM32_JTAG_STATE_READ_COMMAND        4'h0
    50 `define LM32_JTAG_STATE_READ_BYTE_0         4'h1
    51 `define LM32_JTAG_STATE_READ_BYTE_1         4'h2
    52 `define LM32_JTAG_STATE_READ_BYTE_2         4'h3
    53 `define LM32_JTAG_STATE_READ_BYTE_3         4'h4
    54 `define LM32_JTAG_STATE_READ_BYTE_4         4'h5
    55 `define LM32_JTAG_STATE_PROCESS_COMMAND     4'h6
    56 `define LM32_JTAG_STATE_WAIT_FOR_MEMORY     4'h7
    57 `define LM32_JTAG_STATE_WAIT_FOR_CSR        4'h8
    59 /////////////////////////////////////////////////////
    60 // Module interface
    61 /////////////////////////////////////////////////////
    63 module lm32_jtag (
    64     // ----- Inputs -------
    65     clk_i,
    66     rst_i,
    67     jtag_clk, 
    68     jtag_update,
    69     jtag_reg_q,
    70     jtag_reg_addr_q,
    71 `ifdef CFG_JTAG_UART_ENABLED
    72     csr,
    73     csr_write_enable,
    74     csr_write_data,
    75     stall_x,
    76 `endif
    77 `ifdef CFG_HW_DEBUG_ENABLED
    78     jtag_read_data,
    79     jtag_access_complete,
    80 `endif
    81 `ifdef CFG_DEBUG_ENABLED
    82     exception_q_w,
    83 `endif
    84     // ----- Outputs -------
    85 `ifdef CFG_JTAG_UART_ENABLED
    86     jtx_csr_read_data,
    87     jrx_csr_read_data,
    88 `endif
    89 `ifdef CFG_HW_DEBUG_ENABLED
    90     jtag_csr_write_enable,
    91     jtag_csr_write_data,
    92     jtag_csr,
    93     jtag_read_enable,
    94     jtag_write_enable,
    95     jtag_write_data,
    96     jtag_address,
    97 `endif
    98 `ifdef CFG_DEBUG_ENABLED
    99     jtag_break,
   100     jtag_reset,
   101 `endif
   102     jtag_reg_d,
   103     jtag_reg_addr_d
   104     );
   106    parameter lat_family = `LATTICE_FAMILY;
   108 /////////////////////////////////////////////////////
   109 // Inputs
   110 /////////////////////////////////////////////////////
   112 input clk_i;                                            // Clock
   113 input rst_i;                                            // Reset
   115 input jtag_clk;                                         // JTAG clock
   116 input jtag_update;                                      // JTAG data register has been updated
   117 input [`LM32_BYTE_RNG] jtag_reg_q;                      // JTAG data register
   118 input [2:0] jtag_reg_addr_q;                            // JTAG data register
   120 `ifdef CFG_JTAG_UART_ENABLED
   121 input [`LM32_CSR_RNG] csr;                              // CSR to write
   122 input csr_write_enable;                                 // CSR write enable
   123 input [`LM32_WORD_RNG] csr_write_data;                  // Data to write to specified CSR
   124 input stall_x;                                          // Stall instruction in X stage
   125 `endif
   126 `ifdef CFG_HW_DEBUG_ENABLED
   127 input [`LM32_BYTE_RNG] jtag_read_data;                  // Data read from requested address
   128 input jtag_access_complete;                             // Memory access if complete
   129 `endif
   130 `ifdef CFG_DEBUG_ENABLED
   131 input exception_q_w;                                    // Indicates an exception has occured in W stage
   132 `endif
   134 /////////////////////////////////////////////////////
   135 // Outputs
   136 /////////////////////////////////////////////////////
   138 `ifdef CFG_JTAG_UART_ENABLED
   139 output [`LM32_WORD_RNG] jtx_csr_read_data;              // Value of JTX CSR for rcsr instructions
   140 wire   [`LM32_WORD_RNG] jtx_csr_read_data;
   141 output [`LM32_WORD_RNG] jrx_csr_read_data;              // Value of JRX CSR for rcsr instructions
   142 wire   [`LM32_WORD_RNG] jrx_csr_read_data;
   143 `endif
   144 `ifdef CFG_HW_DEBUG_ENABLED
   145 output jtag_csr_write_enable;                           // CSR write enable
   146 reg    jtag_csr_write_enable;
   147 output [`LM32_WORD_RNG] jtag_csr_write_data;            // Data to write to specified CSR
   148 wire   [`LM32_WORD_RNG] jtag_csr_write_data;
   149 output [`LM32_CSR_RNG] jtag_csr;                        // CSR to write
   150 wire   [`LM32_CSR_RNG] jtag_csr;
   151 output jtag_read_enable;                                // Memory read enable
   152 reg    jtag_read_enable;
   153 output jtag_write_enable;                               // Memory write enable
   154 reg    jtag_write_enable;
   155 output [`LM32_BYTE_RNG] jtag_write_data;                // Data to write to specified address
   156 wire   [`LM32_BYTE_RNG] jtag_write_data;        
   157 output [`LM32_WORD_RNG] jtag_address;                   // Memory read/write address
   158 wire   [`LM32_WORD_RNG] jtag_address;
   159 `endif
   160 `ifdef CFG_DEBUG_ENABLED
   161 output jtag_break;                                      // Request to raise a breakpoint exception
   162 reg    jtag_break;
   163 output jtag_reset;                                      // Request to raise a reset exception
   164 reg    jtag_reset;
   165 `endif
   166 output [`LM32_BYTE_RNG] jtag_reg_d;
   167 reg    [`LM32_BYTE_RNG] jtag_reg_d;
   168 output [2:0] jtag_reg_addr_d;
   169 wire   [2:0] jtag_reg_addr_d;
   171 /////////////////////////////////////////////////////
   172 // Internal nets and registers 
   173 /////////////////////////////////////////////////////
   175 reg rx_toggle;                          // Clock-domain crossing registers
   176 reg rx_toggle_r;                        // Registered version of rx_toggle
   177 reg rx_toggle_r_r;                      // Registered version of rx_toggle_r
   178 reg rx_toggle_r_r_r;                    // Registered version of rx_toggle_r_r
   180 reg [`LM32_BYTE_RNG] rx_byte;   
   181 reg [2:0] rx_addr;
   183 `ifdef CFG_JTAG_UART_ENABLED                 
   184 reg [`LM32_BYTE_RNG] uart_tx_byte;      // UART TX data
   185 reg uart_tx_valid;                      // TX data is valid
   186 reg [`LM32_BYTE_RNG] uart_rx_byte;      // UART RX data
   187 reg uart_rx_valid;                      // RX data is valid
   188 `endif
   190 reg [`LM32_DP_RNG] command;             // The last received command
   191 `ifdef CFG_HW_DEBUG_ENABLED
   192 reg [`LM32_BYTE_RNG] jtag_byte_0;       // Registers to hold command paramaters
   193 reg [`LM32_BYTE_RNG] jtag_byte_1;
   194 reg [`LM32_BYTE_RNG] jtag_byte_2;
   195 reg [`LM32_BYTE_RNG] jtag_byte_3;
   196 reg [`LM32_BYTE_RNG] jtag_byte_4;
   197 reg processing;                         // Indicates if we're still processing a memory read/write
   198 `endif
   200 reg [`LM32_JTAG_STATE_RNG] state;       // Current state of FSM
   202 /////////////////////////////////////////////////////
   203 // Combinational Logic
   204 /////////////////////////////////////////////////////
   206 `ifdef CFG_HW_DEBUG_ENABLED
   207 assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
   208 assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
   209 assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
   210 assign jtag_write_data = jtag_byte_4;
   211 `endif
   213 // Generate status flags for reading via the JTAG interface                 
   214 `ifdef CFG_JTAG_UART_ENABLED                 
   215 assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};         
   216 `else
   217 assign jtag_reg_addr_d[1:0] = 2'b00;
   218 `endif
   219 `ifdef CFG_HW_DEBUG_ENABLED
   220 assign jtag_reg_addr_d[2] = processing;
   221 `else
   222 assign jtag_reg_addr_d[2] = 1'b0;
   223 `endif
   225 `ifdef CFG_JTAG_UART_ENABLED                 
   226 assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
   227 assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
   228 `endif         
   230 /////////////////////////////////////////////////////
   231 // Sequential Logic
   232 /////////////////////////////////////////////////////
   234 // Toggle a flag when a JTAG write occurs
   236 always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
   237 begin
   238 if (rst_i == `TRUE)
   239   rx_toggle <= 1'b0;
   240 else 
   241   rx_toggle <= ~rx_toggle;
   242 end
   244 always @(*)
   245 begin
   246     rx_byte = jtag_reg_q;
   247     rx_addr = jtag_reg_addr_q;
   248 end
   250 // Clock domain crossing from JTAG clock domain to CPU clock domain
   251 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   252 begin
   253     if (rst_i == `TRUE)
   254     begin
   255         rx_toggle_r <= 1'b0;
   256         rx_toggle_r_r <= 1'b0;
   257         rx_toggle_r_r_r <= 1'b0;
   258     end
   259     else
   260     begin
   261         rx_toggle_r <= rx_toggle;
   262         rx_toggle_r_r <= rx_toggle_r;
   263         rx_toggle_r_r_r <= rx_toggle_r_r;
   264     end
   265 end
   267 // LM32 debug protocol state machine
   268 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   269 begin
   270     if (rst_i == `TRUE)
   271     begin
   272         state <= `LM32_JTAG_STATE_READ_COMMAND;
   273         command <= 4'b0000;
   274         jtag_reg_d <= 8'h00;
   275 `ifdef CFG_HW_DEBUG_ENABLED
   276         processing <= `FALSE;
   277         jtag_csr_write_enable <= `FALSE;
   278         jtag_read_enable <= `FALSE;
   279         jtag_write_enable <= `FALSE;
   280 `endif
   281 `ifdef CFG_DEBUG_ENABLED
   282         jtag_break <= `FALSE;
   283         jtag_reset <= `FALSE;
   284 `endif
   285 `ifdef CFG_JTAG_UART_ENABLED                 
   286         uart_tx_byte <= 8'h00;
   287         uart_tx_valid <= `FALSE;
   288         uart_rx_byte <= 8'h00;
   289         uart_rx_valid <= `FALSE;
   290 `endif
   291     end
   292     else
   293     begin
   294 `ifdef CFG_JTAG_UART_ENABLED                 
   295         if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
   296         begin
   297             case (csr)
   298             `LM32_CSR_JTX:
   299             begin
   300                 // Set flag indicating data is available
   301                 uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
   302                 uart_tx_valid <= `TRUE;
   303             end
   304             `LM32_CSR_JRX:
   305             begin
   306                 // Clear flag indidicating data has been received
   307                 uart_rx_valid <= `FALSE;
   308             end
   309             endcase
   310         end
   311 `endif
   312 `ifdef CFG_DEBUG_ENABLED
   313         // When an exception has occured, clear the requests
   314         if (exception_q_w == `TRUE)
   315         begin
   316             jtag_break <= `FALSE;
   317             jtag_reset <= `FALSE;
   318         end
   319 `endif
   320         case (state)
   321         `LM32_JTAG_STATE_READ_COMMAND:
   322         begin
   323             // Wait for rx register to toggle which indicates new data is available
   324             if (rx_toggle_r_r != rx_toggle_r_r_r)
   325             begin
   326                 command <= rx_byte[7:4];                
   327                 case (rx_addr)
   328 `ifdef CFG_DEBUG_ENABLED
   329                 `LM32_DP:
   330                 begin
   331                     case (rx_byte[7:4])
   332 `ifdef CFG_HW_DEBUG_ENABLED
   333                     `LM32_DP_READ_MEMORY:
   334                         state <= `LM32_JTAG_STATE_READ_BYTE_0;
   335                     `LM32_DP_READ_SEQUENTIAL:
   336                     begin
   337                         {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
   338                         state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   339                     end
   340                     `LM32_DP_WRITE_MEMORY:
   341                         state <= `LM32_JTAG_STATE_READ_BYTE_0;
   342                     `LM32_DP_WRITE_SEQUENTIAL:
   343                     begin
   344                         {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
   345                         state <= 5;
   346                     end
   347                     `LM32_DP_WRITE_CSR:
   348                         state <= `LM32_JTAG_STATE_READ_BYTE_0;
   349 `endif                    
   350                     `LM32_DP_BREAK:
   351                     begin
   352 `ifdef CFG_JTAG_UART_ENABLED     
   353                         uart_rx_valid <= `FALSE;    
   354                         uart_tx_valid <= `FALSE;         
   355 `endif
   356                         jtag_break <= `TRUE;
   357                     end
   358                     `LM32_DP_RESET:
   359                     begin
   360 `ifdef CFG_JTAG_UART_ENABLED     
   361                         uart_rx_valid <= `FALSE;    
   362                         uart_tx_valid <= `FALSE;         
   363 `endif
   364                         jtag_reset <= `TRUE;
   365                     end
   366                     endcase                               
   367                 end
   368 `endif
   369 `ifdef CFG_JTAG_UART_ENABLED                 
   370                 `LM32_TX:
   371                 begin
   372                     uart_rx_byte <= rx_byte;
   373                     uart_rx_valid <= `TRUE;
   374                 end                    
   375                 `LM32_RX:
   376                 begin
   377                     jtag_reg_d <= uart_tx_byte;
   378                     uart_tx_valid <= `FALSE;
   379                 end
   380 `endif
   381                 default:
   382                     ;
   383                 endcase                
   384             end
   385         end
   386 `ifdef CFG_HW_DEBUG_ENABLED
   387         `LM32_JTAG_STATE_READ_BYTE_0:
   388         begin
   389             if (rx_toggle_r_r != rx_toggle_r_r_r)
   390             begin
   391                 jtag_byte_0 <= rx_byte;
   392                 state <= `LM32_JTAG_STATE_READ_BYTE_1;
   393             end
   394         end
   395         `LM32_JTAG_STATE_READ_BYTE_1:
   396         begin
   397             if (rx_toggle_r_r != rx_toggle_r_r_r)
   398             begin
   399                 jtag_byte_1 <= rx_byte;
   400                 state <= `LM32_JTAG_STATE_READ_BYTE_2;
   401             end
   402         end
   403         `LM32_JTAG_STATE_READ_BYTE_2:
   404         begin
   405             if (rx_toggle_r_r != rx_toggle_r_r_r)
   406             begin
   407                 jtag_byte_2 <= rx_byte;
   408                 state <= `LM32_JTAG_STATE_READ_BYTE_3;
   409             end
   410         end
   411         `LM32_JTAG_STATE_READ_BYTE_3:
   412         begin
   413             if (rx_toggle_r_r != rx_toggle_r_r_r)
   414             begin
   415                 jtag_byte_3 <= rx_byte;
   416                 if (command == `LM32_DP_READ_MEMORY)
   417                     state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   418                 else 
   419                     state <= `LM32_JTAG_STATE_READ_BYTE_4;
   420             end
   421         end
   422         `LM32_JTAG_STATE_READ_BYTE_4:
   423         begin
   424             if (rx_toggle_r_r != rx_toggle_r_r_r)
   425             begin
   426                 jtag_byte_4 <= rx_byte;
   427                 state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   428             end
   429         end
   430         `LM32_JTAG_STATE_PROCESS_COMMAND:
   431         begin
   432             case (command)
   433             `LM32_DP_READ_MEMORY,
   434             `LM32_DP_READ_SEQUENTIAL:
   435             begin
   436                 jtag_read_enable <= `TRUE;
   437                 processing <= `TRUE;
   438                 state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   439             end
   440             `LM32_DP_WRITE_MEMORY,
   441             `LM32_DP_WRITE_SEQUENTIAL:
   442             begin
   443                 jtag_write_enable <= `TRUE;
   444                 processing <= `TRUE;
   445                 state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   446             end
   447             `LM32_DP_WRITE_CSR:
   448             begin
   449                 jtag_csr_write_enable <= `TRUE;
   450                 processing <= `TRUE;
   451                 state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
   452             end
   453             endcase
   454         end
   455         `LM32_JTAG_STATE_WAIT_FOR_MEMORY:
   456         begin
   457             if (jtag_access_complete == `TRUE)
   458             begin          
   459                 jtag_read_enable <= `FALSE;
   460                 jtag_reg_d <= jtag_read_data;
   461                 jtag_write_enable <= `FALSE;  
   462                 processing <= `FALSE;
   463                 state <= `LM32_JTAG_STATE_READ_COMMAND;
   464             end
   465         end    
   466         `LM32_JTAG_STATE_WAIT_FOR_CSR:
   467         begin
   468             jtag_csr_write_enable <= `FALSE;
   469             processing <= `FALSE;
   470             state <= `LM32_JTAG_STATE_READ_COMMAND;
   471         end    
   472 `endif
   473         endcase
   474     end
   475 end
   477 endmodule
   479 `endif