lm32_monitor.v

Mon, 05 Apr 2010 20:23:04 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Mon, 05 Apr 2010 20:23:04 +0100
changeset 4
99b7b037ce82
parent 0
cd0b58aa6f83
child 8
07be9df9fee8
permissions
-rw-r--r--

add better comment re Xilinx Xst cache issues

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : lm32_monitor.v
    19 // Title            : Debug monitor memory Wishbone interface
    20 // Version          : 6.1.17
    21 //                  : Initial Release
    22 // Version          : 7.0SP2, 3.0
    23 //                  : No Change
    24 // Version          : 3.3
    25 //                  : Removed port mismatch in instantiation of module
    26 //                  : lm32_monitor_ram.
    27 // =============================================================================
    29 `include "system_conf.v"
    30 `include "lm32_include.v"
    32 /////////////////////////////////////////////////////
    33 // Module interface
    34 /////////////////////////////////////////////////////
    36 module lm32_monitor (
    37     // ----- Inputs -------
    38     clk_i, 
    39     rst_i,
    40     MON_ADR_I,
    41     MON_CYC_I,
    42     MON_DAT_I,
    43     MON_SEL_I,
    44     MON_STB_I,
    45     MON_WE_I,
    46     MON_LOCK_I,
    47     MON_CTI_I,
    48     MON_BTE_I,
    49     // ----- Outputs -------
    50     MON_ACK_O,
    51     MON_RTY_O,
    52     MON_DAT_O,
    53     MON_ERR_O
    54     );
    56 /////////////////////////////////////////////////////
    57 // Inputs
    58 /////////////////////////////////////////////////////
    60 input clk_i;                                        // Wishbone clock
    61 input rst_i;                                        // Wishbone reset
    62 input [`LM32_WORD_RNG] MON_ADR_I;                   // Wishbone address
    63 input MON_STB_I;                                    // Wishbone strobe
    64 input MON_CYC_I;                                    // Wishbone cycle
    65 input [`LM32_WORD_RNG] MON_DAT_I;                   // Wishbone write data
    66 input [`LM32_BYTE_SELECT_RNG] MON_SEL_I;            // Wishbone byte select
    67 input MON_WE_I;                                     // Wishbone write enable
    68 input MON_LOCK_I;                                   // Wishbone locked transfer
    69 input [`LM32_CTYPE_RNG] MON_CTI_I;                  // Wishbone cycle type
    70 input [`LM32_BTYPE_RNG] MON_BTE_I;                  // Wishbone burst type
    72 /////////////////////////////////////////////////////
    73 // Outputs
    74 /////////////////////////////////////////////////////
    76 output MON_ACK_O;                                   // Wishbone acknowlege
    77 reg    MON_ACK_O;
    78 output [`LM32_WORD_RNG] MON_DAT_O;                  // Wishbone data output
    79 reg    [`LM32_WORD_RNG] MON_DAT_O;
    80 output MON_RTY_O;                                   // Wishbone retry
    81 wire   MON_RTY_O;       
    82 output MON_ERR_O;                                   // Wishbone error
    83 wire   MON_ERR_O;
    85 /////////////////////////////////////////////////////
    86 // Internal nets and registers 
    87 /////////////////////////////////////////////////////
    89 reg [1:0] state;                                    // Current state of FSM
    90 wire [`LM32_WORD_RNG] data, dataB;                  // Data read from RAM
    91 reg write_enable;                                   // RAM write enable
    92 reg [`LM32_WORD_RNG] write_data;                    // RAM write data
    94 /////////////////////////////////////////////////////
    95 // Instantiations
    96 /////////////////////////////////////////////////////
    98 lm32_monitor_ram ram (
    99     // ----- Inputs -------
   100     .ClockA             (clk_i),
   101     .ClockB             (clk_i),
   102     .ResetA             (rst_i),
   103     .ResetB             (rst_i),
   104     .ClockEnA           (`TRUE),
   105     .ClockEnB           (`FALSE),
   106     .AddressA           (MON_ADR_I[10:2]),
   107     .AddressB           (9'b0),
   108     .DataInA            (write_data),
   109     .DataInB            (32'b0),
   110     .WrA                (write_enable),
   111     .WrB                (`FALSE),
   112     // ----- Outputs -------
   113     .QA                 (data),
   114     .QB                 (dataB)
   115     );
   117 /////////////////////////////////////////////////////
   118 // Combinational Logic
   119 /////////////////////////////////////////////////////
   121 assign MON_RTY_O = `FALSE;
   122 assign MON_ERR_O = `FALSE;
   124 /////////////////////////////////////////////////////
   125 // Sequential Logic
   126 /////////////////////////////////////////////////////
   128 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   129 begin
   130     if (rst_i == `TRUE)
   131     begin
   132         write_enable <= `FALSE;
   133         MON_ACK_O <= `FALSE;
   134         MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
   135         state <= 2'b00;
   136     end
   137     else
   138     begin
   139         case (state)
   140         2'b00:
   141         begin
   142             // Wait for a Wishbone access
   143             if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
   144                 state <= 2'b01;
   145         end
   146         2'b01:
   147         begin
   148             // Output read data to Wishbone
   149             MON_ACK_O <= `TRUE;
   150             MON_DAT_O <= data;
   151             // Sub-word writes are performed using read-modify-write  
   152             // as the Lattice EBRs don't support byte enables
   153             if (MON_WE_I == `TRUE)
   154                 write_enable <= `TRUE;
   155             write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
   156             write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
   157             write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
   158             write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
   159             state <= 2'b10;
   160         end
   161         2'b10:
   162         begin
   163             // Wishbone access occurs in this cycle
   164             write_enable <= `FALSE;
   165             MON_ACK_O <= `FALSE;
   166             MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
   167             state <= 2'b00;
   168         end
   169         endcase        
   170     end
   171 end
   173 endmodule