typeb.v

Mon, 05 Apr 2010 20:23:04 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Mon, 05 Apr 2010 20:23:04 +0100
changeset 4
99b7b037ce82
parent 0
cd0b58aa6f83
child 26
73de224304c1
permissions
-rw-r--r--

add better comment re Xilinx Xst cache issues

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : TYPEB.v
    19 // Description:
    20 //    This is one of the two types of cells that are used to create ER1/ER2
    21 //    register bits.
    22 // Dependencies     : None
    23 // Version          : 6.1.17
    24 //   Modified typeb module to remove redundant DATA_OUT port.
    25 // Version          : 7.0SP2, 3.0
    26 //                  : No Change
    27 // Version          : 3.1
    28 //                  : No Change
    29 // =============================================================================
    30 module TYPEB
    31    (
    32       input CLK,
    33       input RESET_N,
    34       input CLKEN,
    35       input TDI,
    36       output TDO,
    37       input DATA_IN,
    38       input CAPTURE_DR
    39    );
    41    reg tdoInt;
    43    always @ (negedge CLK or negedge RESET_N)
    44    begin
    45       if (RESET_N== 1'b0)
    46          tdoInt <= 1'b0;
    47       else if (CLK == 1'b0)
    48          if (CLKEN==1'b1)
    49             if (CAPTURE_DR==1'b0)
    50                tdoInt <= TDI;
    51             else
    52                tdoInt <= DATA_IN;
    53    end
    55    assign TDO = tdoInt;
    57 endmodule