lm32_load_store_unit.v

Sun, 04 Apr 2010 20:52:32 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 04 Apr 2010 20:52:32 +0100
changeset 2
a61bb364ae1f
parent 0
cd0b58aa6f83
child 8
07be9df9fee8
permissions
-rw-r--r--

Disable Lattice-specific stuff by default

To build on Lattice platforms, `define PLATFORM_LATTICE in lm32_include.v.
Otherwise, non-optimal "platform independent" HDL will be used.
This means LM32 can now be built for non-Lattice FPGAs.

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project      : LatticeMico32
    18 // File         : lm32_load_store_unit.v
    19 // Title        : Load and store unit
    20 // Dependencies : lm32_include.v
    21 // Version      : 6.1.17
    22 //              : Initial Release
    23 // Version      : 7.0SP2, 3.0
    24 //              : No Change
    25 // Version      : 3.1
    26 //              : Instead of disallowing an instruction cache miss on a data cache 
    27 //              : miss, both can now occur at the same time. If both occur at same 
    28 //              : time, then restart address is the address of instruction that 
    29 //              : caused data cache miss.
    30 // Version      : 3.2
    31 //              : EBRs use SYNC resets instead of ASYNC resets.
    32 // Version      : 3.3
    33 //              : Support for new non-cacheable Data Memory that is accessible by 
    34 //              : the data port and has a one cycle access latency.
    35 // Version      : 3.4
    36 //              : No change
    37 // Version      : 3.5
    38 //              : Bug fix: Inline memory is correctly generated if it is not a
    39 //              : power-of-two
    40 // =============================================================================
    42 `include "lm32_include.v"
    44 /////////////////////////////////////////////////////
    45 // Module interface
    46 /////////////////////////////////////////////////////
    48 module lm32_load_store_unit (
    49     // ----- Inputs -------
    50     clk_i,
    51     rst_i,
    52     // From pipeline
    53     stall_a,
    54     stall_x,
    55     stall_m,
    56     kill_x,
    57     kill_m,
    58     exception_m,
    59     store_operand_x,
    60     load_store_address_x,
    61     load_store_address_m,
    62     load_store_address_w,
    63     load_x,
    64     store_x,
    65     load_q_x,
    66     store_q_x,
    67     load_q_m,
    68     store_q_m,
    69     sign_extend_x,
    70     size_x,
    71 `ifdef CFG_DCACHE_ENABLED
    72     dflush,
    73 `endif
    74 `ifdef CFG_IROM_ENABLED
    75     irom_data_m,
    76 `endif
    77     // From Wishbone
    78     d_dat_i,
    79     d_ack_i,
    80     d_err_i,
    81     d_rty_i,
    82     // ----- Outputs -------
    83     // To pipeline
    84 `ifdef CFG_DCACHE_ENABLED
    85     dcache_refill_request,
    86     dcache_restart_request,
    87     dcache_stall_request,
    88     dcache_refilling,
    89 `endif    
    90 `ifdef CFG_IROM_ENABLED
    91     irom_store_data_m,
    92     irom_address_xm,
    93     irom_we_xm,
    94     irom_stall_request_x,
    95 `endif			     
    96     load_data_w,
    97     stall_wb_load,
    98     // To Wishbone
    99     d_dat_o,
   100     d_adr_o,
   101     d_cyc_o,
   102     d_sel_o,
   103     d_stb_o,
   104     d_we_o,
   105     d_cti_o,
   106     d_lock_o,
   107     d_bte_o
   108     );
   110 /////////////////////////////////////////////////////
   111 // Parameters
   112 /////////////////////////////////////////////////////
   114 parameter associativity = 1;                            // Associativity of the cache (Number of ways)
   115 parameter sets = 512;                                   // Number of sets
   116 parameter bytes_per_line = 16;                          // Number of bytes per cache line
   117 parameter base_address = 0;                             // Base address of cachable memory
   118 parameter limit = 0;                                    // Limit (highest address) of cachable memory
   120 // For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used 
   121 localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
   122 localparam addr_offset_lsb = 2;
   123 localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
   125 /////////////////////////////////////////////////////
   126 // Inputs
   127 /////////////////////////////////////////////////////
   129 input clk_i;                                            // Clock 
   130 input rst_i;                                            // Reset
   132 input stall_a;                                          // A stage stall 
   133 input stall_x;                                          // X stage stall        
   134 input stall_m;                                          // M stage stall
   135 input kill_x;                                           // Kill instruction in X stage
   136 input kill_m;                                           // Kill instruction in M stage
   137 input exception_m;                                      // An exception occured in the M stage
   139 input [`LM32_WORD_RNG] store_operand_x;                 // Data read from register to store
   140 input [`LM32_WORD_RNG] load_store_address_x;            // X stage load/store address
   141 input [`LM32_WORD_RNG] load_store_address_m;            // M stage load/store address
   142 input [1:0] load_store_address_w;                       // W stage load/store address (only least two significant bits are needed)
   143 input load_x;                                           // Load instruction in X stage
   144 input store_x;                                          // Store instruction in X stage
   145 input load_q_x;                                         // Load instruction in X stage
   146 input store_q_x;                                        // Store instruction in X stage
   147 input load_q_m;                                         // Load instruction in M stage
   148 input store_q_m;                                        // Store instruction in M stage
   149 input sign_extend_x;                                    // Whether load instruction in X stage should sign extend or zero extend
   150 input [`LM32_SIZE_RNG] size_x;                          // Size of load or store (byte, hword, word)
   152 `ifdef CFG_DCACHE_ENABLED
   153 input dflush;                                           // Flush the data cache
   154 `endif
   156 `ifdef CFG_IROM_ENABLED   
   157 input [`LM32_WORD_RNG] irom_data_m;                     // Data from Instruction-ROM
   158 `endif
   160 input [`LM32_WORD_RNG] d_dat_i;                         // Data Wishbone interface read data
   161 input d_ack_i;                                          // Data Wishbone interface acknowledgement
   162 input d_err_i;                                          // Data Wishbone interface error
   163 input d_rty_i;                                          // Data Wishbone interface retry
   165 /////////////////////////////////////////////////////
   166 // Outputs
   167 /////////////////////////////////////////////////////
   169 `ifdef CFG_DCACHE_ENABLED
   170 output dcache_refill_request;                           // Request to refill data cache
   171 wire   dcache_refill_request;
   172 output dcache_restart_request;                          // Request to restart the instruction that caused a data cache miss
   173 wire   dcache_restart_request;
   174 output dcache_stall_request;                            // Data cache stall request
   175 wire   dcache_stall_request;
   176 output dcache_refilling;
   177 wire   dcache_refilling;
   178 `endif
   180 `ifdef CFG_IROM_ENABLED   
   181 output irom_store_data_m;                               // Store data to Instruction ROM
   182 wire   [`LM32_WORD_RNG] irom_store_data_m;
   183 output [`LM32_WORD_RNG] irom_address_xm;                // Load/store address to Instruction ROM
   184 wire   [`LM32_WORD_RNG] irom_address_xm;
   185 output irom_we_xm;                                      // Write-enable of 2nd port of Instruction ROM
   186 wire   irom_we_xm;
   187 output irom_stall_request_x;                            // Stall instruction in D stage  
   188 wire   irom_stall_request_x;                            
   189 `endif
   191 output [`LM32_WORD_RNG] load_data_w;                    // Result of a load instruction
   192 reg    [`LM32_WORD_RNG] load_data_w;
   193 output stall_wb_load;                                   // Request to stall pipeline due to a load from the Wishbone interface
   194 reg    stall_wb_load;
   196 output [`LM32_WORD_RNG] d_dat_o;                        // Data Wishbone interface write data
   197 reg    [`LM32_WORD_RNG] d_dat_o;
   198 output [`LM32_WORD_RNG] d_adr_o;                        // Data Wishbone interface address
   199 reg    [`LM32_WORD_RNG] d_adr_o;
   200 output d_cyc_o;                                         // Data Wishbone interface cycle
   201 reg    d_cyc_o;
   202 output [`LM32_BYTE_SELECT_RNG] d_sel_o;                 // Data Wishbone interface byte select
   203 reg    [`LM32_BYTE_SELECT_RNG] d_sel_o;
   204 output d_stb_o;                                         // Data Wishbone interface strobe
   205 reg    d_stb_o; 
   206 output d_we_o;                                          // Data Wishbone interface write enable
   207 reg    d_we_o;
   208 output [`LM32_CTYPE_RNG] d_cti_o;                       // Data Wishbone interface cycle type 
   209 reg    [`LM32_CTYPE_RNG] d_cti_o;
   210 output d_lock_o;                                        // Date Wishbone interface lock bus
   211 reg    d_lock_o;
   212 output [`LM32_BTYPE_RNG] d_bte_o;                       // Data Wishbone interface burst type 
   213 wire   [`LM32_BTYPE_RNG] d_bte_o;
   215 /////////////////////////////////////////////////////
   216 // Internal nets and registers 
   217 /////////////////////////////////////////////////////
   219 // Microcode pipeline registers - See inputs for description
   220 reg [`LM32_SIZE_RNG] size_m;
   221 reg [`LM32_SIZE_RNG] size_w;
   222 reg sign_extend_m;
   223 reg sign_extend_w;
   224 reg [`LM32_WORD_RNG] store_data_x;       
   225 reg [`LM32_WORD_RNG] store_data_m;       
   226 reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
   227 reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
   228 wire [`LM32_WORD_RNG] data_m;
   229 reg [`LM32_WORD_RNG] data_w;
   231 `ifdef CFG_DCACHE_ENABLED
   232 wire dcache_select_x;                                   // Select data cache to load from / store to
   233 reg dcache_select_m;
   234 wire [`LM32_WORD_RNG] dcache_data_m;                    // Data read from cache
   235 wire [`LM32_WORD_RNG] dcache_refill_address;            // Address to refill data cache from
   236 reg dcache_refill_ready;                                // Indicates the next word of refill data is ready
   237 wire [`LM32_CTYPE_RNG] first_cycle_type;                // First Wishbone cycle type
   238 wire [`LM32_CTYPE_RNG] next_cycle_type;                 // Next Wishbone cycle type
   239 wire last_word;                                         // Indicates if this is the last word in the cache line
   240 wire [`LM32_WORD_RNG] first_address;                    // First cache refill address
   241 `endif
   242 `ifdef CFG_DRAM_ENABLED
   243 wire dram_select_x;                                     // Select data RAM to load from / store to
   244 reg dram_select_m;
   245 reg dram_bypass_en;                                     // RAW in data RAM; read latched (bypass) value rather than value from memory
   246 reg [`LM32_WORD_RNG] dram_bypass_data;                  // Latched value of store'd data to data RAM
   247 wire [`LM32_WORD_RNG] dram_data_out;                    // Data read from data RAM
   248 wire [`LM32_WORD_RNG] dram_data_m;                      // Data read from data RAM: bypass value or value from memory
   249 wire [`LM32_WORD_RNG] dram_store_data_m;                // Data to write to RAM
   250 `endif
   251 wire wb_select_x;                                       // Select Wishbone to load from / store to
   252 `ifdef CFG_IROM_ENABLED
   253 wire irom_select_x;                                     // Select instruction ROM to load from / store to
   254 reg  irom_select_m;
   255 `endif
   256 reg wb_select_m;
   257 reg [`LM32_WORD_RNG] wb_data_m;                         // Data read from Wishbone
   258 reg wb_load_complete;                                   // Indicates when a Wishbone load is complete
   260 /////////////////////////////////////////////////////
   261 // Functions
   262 /////////////////////////////////////////////////////
   264 `include "lm32_functions.v"
   266 /////////////////////////////////////////////////////
   267 // Instantiations
   268 /////////////////////////////////////////////////////
   270 `ifdef CFG_DRAM_ENABLED
   271    // Data RAM
   272    pmi_ram_dp_true 
   273      #(
   274        // ----- Parameters -------
   275        .pmi_family             (`LATTICE_FAMILY),
   277        //.pmi_addr_depth_a       (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
   278        //.pmi_addr_width_a       ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
   279        //.pmi_data_width_a       (`LM32_WORD_WIDTH),
   280        //.pmi_addr_depth_b       (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
   281        //.pmi_addr_width_b       ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
   282        //.pmi_data_width_b       (`LM32_WORD_WIDTH),
   284        .pmi_addr_depth_a       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
   285        .pmi_addr_width_a       (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
   286        .pmi_data_width_a       (`LM32_WORD_WIDTH),
   287        .pmi_addr_depth_b       (`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1),
   288        .pmi_addr_width_b       (clogb2_v1(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)),
   289        .pmi_data_width_b       (`LM32_WORD_WIDTH),
   291        .pmi_regmode_a          ("noreg"),
   292        .pmi_regmode_b          ("noreg"),
   293        .pmi_gsr                ("enable"),
   294        .pmi_resetmode          ("sync"),
   295        .pmi_init_file          (`CFG_DRAM_INIT_FILE),
   296        .pmi_init_file_format   (`CFG_DRAM_INIT_FILE_FORMAT),
   297        .module_type            ("pmi_ram_dp_true")
   298        ) 
   299        ram (
   300 	    // ----- Inputs -------
   301 	    .ClockA                 (clk_i),
   302 	    .ClockB                 (clk_i),
   303 	    .ResetA                 (rst_i),
   304 	    .ResetB                 (rst_i),
   305 	    .DataInA                ({32{1'b0}}),
   306 	    .DataInB                (dram_store_data_m),
   307 	    .AddressA               (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
   308 	    .AddressB               (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
   309 	    // .ClockEnA               (!stall_x & (load_x | store_x)),
   310 	    .ClockEnA               (!stall_x),
   311 	    .ClockEnB               (!stall_m),
   312 	    .WrA                    (`FALSE),
   313 	    .WrB                    (store_q_m & dram_select_m), 
   314 	    // ----- Outputs -------
   315 	    .QA                     (dram_data_out),
   316 	    .QB                     ()
   317 	    );
   319    /*----------------------------------------------------------------------
   320     EBRs cannot perform reads from location 'written to' on the same clock
   321     edge. Therefore bypass logic is required to latch the store'd value
   322     and use it for the load (instead of value from memory).
   323     ----------------------------------------------------------------------*/
   324    always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   325      if (rst_i == `TRUE)
   326        begin
   327 	  dram_bypass_en <= `FALSE;
   328 	  dram_bypass_data <= 0;
   329        end
   330      else
   331        begin
   332 	  if (stall_x == `FALSE)
   333 	    dram_bypass_data <= dram_store_data_m;
   335 	  if (   (stall_m == `FALSE) 
   336               && (stall_x == `FALSE)
   337 	      && (store_q_m == `TRUE)
   338 	      && (   (load_x == `TRUE)
   339 	          || (store_x == `TRUE)
   340 		 )
   341 	      && (load_store_address_x[(`LM32_WORD_WIDTH-1):2] == load_store_address_m[(`LM32_WORD_WIDTH-1):2])
   342 	     )
   343 	    dram_bypass_en <= `TRUE;
   344 	  else
   345 	    if (   (dram_bypass_en == `TRUE)
   346 		&& (stall_x == `FALSE)
   347 	       )
   348 	      dram_bypass_en <= `FALSE;
   349        end
   351    assign dram_data_m = dram_bypass_en ? dram_bypass_data : dram_data_out;
   352 `endif
   354 `ifdef CFG_DCACHE_ENABLED
   355 // Data cache
   356 lm32_dcache #(
   357     .associativity          (associativity),
   358     .sets                   (sets),
   359     .bytes_per_line         (bytes_per_line),
   360     .base_address           (base_address),
   361     .limit                  (limit)
   362     ) dcache ( 
   363     // ----- Inputs -----
   364     .clk_i                  (clk_i),
   365     .rst_i                  (rst_i),      
   366     .stall_a                (stall_a),
   367     .stall_x                (stall_x),
   368     .stall_m                (stall_m),
   369     .address_x              (load_store_address_x),
   370     .address_m              (load_store_address_m),
   371     .load_q_m               (load_q_m & dcache_select_m),
   372     .store_q_m              (store_q_m & dcache_select_m),
   373     .store_data             (store_data_m),
   374     .store_byte_select      (byte_enable_m & {4{dcache_select_m}}),
   375     .refill_ready           (dcache_refill_ready),
   376     .refill_data            (wb_data_m),
   377     .dflush                 (dflush),
   378     // ----- Outputs -----
   379     .stall_request          (dcache_stall_request),
   380     .restart_request        (dcache_restart_request),
   381     .refill_request         (dcache_refill_request),
   382     .refill_address         (dcache_refill_address),
   383     .refilling              (dcache_refilling),
   384     .load_data              (dcache_data_m)
   385     );
   386 `endif
   388 /////////////////////////////////////////////////////
   389 // Combinational Logic
   390 /////////////////////////////////////////////////////
   392 // Select where data should be loaded from / stored to
   393 `ifdef CFG_DRAM_ENABLED
   394    assign dram_select_x =    (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS) 
   395                           && (load_store_address_x <= `CFG_DRAM_LIMIT);
   396 `endif
   398 `ifdef CFG_IROM_ENABLED
   399    assign irom_select_x =    (load_store_address_x >= `CFG_IROM_BASE_ADDRESS) 
   400                           && (load_store_address_x <= `CFG_IROM_LIMIT);
   401 `endif
   403 `ifdef CFG_DCACHE_ENABLED
   404    assign dcache_select_x =    (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) 
   405                             && (load_store_address_x <= `CFG_DCACHE_LIMIT)
   406 `ifdef CFG_DRAM_ENABLED
   407                             && (dram_select_x == `FALSE)
   408 `endif
   409 `ifdef CFG_IROM_ENABLED
   410                             && (irom_select_x == `FALSE)
   411 `endif
   412                      ;
   413 `endif
   415    assign wb_select_x =    `TRUE
   416 `ifdef CFG_DCACHE_ENABLED
   417                         && !dcache_select_x 
   418 `endif
   419 `ifdef CFG_DRAM_ENABLED
   420                         && !dram_select_x
   421 `endif
   422 `ifdef CFG_IROM_ENABLED
   423                         && !irom_select_x
   424 `endif
   425                      ;
   427 // Make sure data to store is in correct byte lane
   428 always @(*)
   429 begin
   430     case (size_x)
   431     `LM32_SIZE_BYTE:  store_data_x = {4{store_operand_x[7:0]}};
   432     `LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
   433     `LM32_SIZE_WORD:  store_data_x = store_operand_x;    
   434     default:          store_data_x = {`LM32_WORD_WIDTH{1'bx}};
   435     endcase
   436 end
   438 // Generate byte enable accoring to size of load or store and address being accessed
   439 always @(*)
   440 begin
   441     casez ({size_x, load_store_address_x[1:0]})
   442     {`LM32_SIZE_BYTE, 2'b11}:  byte_enable_x = 4'b0001;
   443     {`LM32_SIZE_BYTE, 2'b10}:  byte_enable_x = 4'b0010;
   444     {`LM32_SIZE_BYTE, 2'b01}:  byte_enable_x = 4'b0100;
   445     {`LM32_SIZE_BYTE, 2'b00}:  byte_enable_x = 4'b1000;
   446     {`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
   447     {`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
   448     {`LM32_SIZE_WORD, 2'b??}:  byte_enable_x = 4'b1111;
   449     default:                   byte_enable_x = 4'bxxxx;
   450     endcase
   451 end
   453 `ifdef CFG_DRAM_ENABLED
   454 // Only replace selected bytes
   455 assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
   456 assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
   457 assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
   458 assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
   459 `endif
   461 `ifdef CFG_IROM_ENABLED
   462 // Only replace selected bytes
   463 assign irom_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : irom_data_m[`LM32_BYTE_0_RNG];
   464 assign irom_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : irom_data_m[`LM32_BYTE_1_RNG];
   465 assign irom_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : irom_data_m[`LM32_BYTE_2_RNG];
   466 assign irom_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : irom_data_m[`LM32_BYTE_3_RNG];
   467 `endif
   469 `ifdef CFG_IROM_ENABLED
   470    // Instead of implementing a byte-addressable instruction ROM (for store byte instruction),
   471    // a load-and-store architecture is used wherein a 32-bit value is loaded, the requisite
   472    // byte is replaced, and the whole 32-bit value is written back
   474    assign irom_address_xm = ((irom_select_m == `TRUE) && (store_q_m == `TRUE))
   475 	                    ? load_store_address_m
   476 	                    : load_store_address_x;
   478    // All store instructions perform a write operation in the M stage
   479    assign irom_we_xm =    (irom_select_m == `TRUE)
   480 	               && (store_q_m == `TRUE);
   482    // A single port in instruction ROM is available to load-store unit for doing loads/stores.
   483    // Since every store requires a load (in X stage) and then a store (in M stage), we cannot
   484    // allow load (or store) instructions sequentially after the store instructions to proceed 
   485    // until the store instruction has vacated M stage (i.e., completed the store operation)
   486    assign irom_stall_request_x =    (irom_select_x == `TRUE)
   487 	                         && (store_q_x == `TRUE);
   488 `endif
   490 `ifdef CFG_DCACHE_ENABLED
   491  `ifdef CFG_DRAM_ENABLED
   492   `ifdef CFG_IROM_ENABLED
   493    // WB + DC + DRAM + IROM
   494    assign data_m = wb_select_m == `TRUE 
   495                    ? wb_data_m
   496                    : dram_select_m == `TRUE 
   497                      ? dram_data_m
   498                      : irom_select_m == `TRUE
   499                        ? irom_data_m 
   500                        : dcache_data_m;
   501   `else
   502    // WB + DC + DRAM
   503    assign data_m = wb_select_m == `TRUE 
   504                    ? wb_data_m
   505                    : dram_select_m == `TRUE 
   506                      ? dram_data_m
   507                      : dcache_data_m;
   508   `endif
   509  `else
   510   `ifdef CFG_IROM_ENABLED
   511    // WB + DC + IROM
   512    assign data_m = wb_select_m == `TRUE 
   513                    ? wb_data_m
   514                    : irom_select_m == `TRUE 
   515                      ? irom_data_m
   516                      : dcache_data_m;
   517   `else
   518    // WB + DC
   519    assign data_m = wb_select_m == `TRUE 
   520                    ? wb_data_m 
   521                    : dcache_data_m;
   522   `endif
   523  `endif
   524 `else
   525  `ifdef CFG_DRAM_ENABLED
   526   `ifdef CFG_IROM_ENABLED
   527    // WB + DRAM + IROM
   528    assign data_m = wb_select_m == `TRUE 
   529                    ? wb_data_m 
   530                    : dram_select_m == `TRUE
   531                      ? dram_data_m
   532                      : irom_data_m;
   533   `else
   534    // WB + DRAM
   535    assign data_m = wb_select_m == `TRUE 
   536                    ? wb_data_m 
   537                    : dram_data_m;
   538   `endif
   539  `else
   540   `ifdef CFG_IROM_ENABLED
   541    // WB + IROM
   542    assign data_m = wb_select_m == `TRUE 
   543                    ? wb_data_m 
   544                    : irom_data_m;
   545   `else
   546    // WB
   547    assign data_m = wb_data_m;
   548   `endif
   549  `endif
   550 `endif
   552 // Sub-word selection and sign/zero-extension for loads
   553 always @(*)
   554 begin
   555     casez ({size_w, load_store_address_w[1:0]})
   556     {`LM32_SIZE_BYTE, 2'b11}:  load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
   557     {`LM32_SIZE_BYTE, 2'b10}:  load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
   558     {`LM32_SIZE_BYTE, 2'b01}:  load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
   559     {`LM32_SIZE_BYTE, 2'b00}:  load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
   560     {`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
   561     {`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
   562     {`LM32_SIZE_WORD, 2'b??}:  load_data_w = data_w;
   563     default:                   load_data_w = {`LM32_WORD_WIDTH{1'bx}};
   564     endcase
   565 end
   567 // Unused/constant Wishbone signals
   568 assign d_bte_o = `LM32_BTYPE_LINEAR;
   570 `ifdef CFG_DCACHE_ENABLED                
   571 // Generate signal to indicate last word in cache line
   572 generate 
   573     case (bytes_per_line)
   574     4:
   575     begin
   576 assign first_cycle_type = `LM32_CTYPE_END;
   577 assign next_cycle_type = `LM32_CTYPE_END;
   578 assign last_word = `TRUE;
   579 assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
   580     end
   581     8:
   582     begin
   583 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
   584 assign next_cycle_type = `LM32_CTYPE_END;
   585 assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
   586 assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
   587     end
   588     16:
   589     begin
   590 assign first_cycle_type = `LM32_CTYPE_INCREMENTING;
   591 assign next_cycle_type = d_adr_o[addr_offset_msb] == 1'b1 ? `LM32_CTYPE_END : `LM32_CTYPE_INCREMENTING;
   592 assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
   593 assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
   594     end
   595     endcase
   596 endgenerate
   597 `endif
   599 /////////////////////////////////////////////////////
   600 // Sequential Logic
   601 /////////////////////////////////////////////////////
   603 // Data Wishbone interface
   604 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   605 begin
   606     if (rst_i == `TRUE)
   607     begin
   608         d_cyc_o <= `FALSE;
   609         d_stb_o <= `FALSE;
   610         d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
   611         d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
   612         d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
   613         d_we_o <= `FALSE;
   614         d_cti_o <= `LM32_CTYPE_END;
   615         d_lock_o <= `FALSE;
   616         wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
   617         wb_load_complete <= `FALSE;
   618         stall_wb_load <= `FALSE;
   619 `ifdef CFG_DCACHE_ENABLED                
   620         dcache_refill_ready <= `FALSE;
   621 `endif                
   622     end
   623     else
   624     begin
   625 `ifdef CFG_DCACHE_ENABLED 
   626         // Refill ready should only be asserted for a single cycle               
   627         dcache_refill_ready <= `FALSE;
   628 `endif                
   629         // Is a Wishbone cycle already in progress?
   630         if (d_cyc_o == `TRUE)
   631         begin
   632             // Is the cycle complete?
   633             if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
   634             begin
   635 `ifdef CFG_DCACHE_ENABLED                
   636                 if ((dcache_refilling == `TRUE) && (!last_word))
   637                 begin
   638                     // Fetch next word of cache line    
   639                     d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
   640                 end
   641                 else
   642 `endif                
   643                 begin
   644                     // Refill/access complete
   645                     d_cyc_o <= `FALSE;
   646                     d_stb_o <= `FALSE;
   647                     d_lock_o <= `FALSE;
   648                 end
   649 `ifdef CFG_DCACHE_ENABLED    
   650                 d_cti_o <= next_cycle_type;
   651                 // If we are performing a refill, indicate to cache next word of data is ready            
   652                 dcache_refill_ready <= dcache_refilling;
   653 `endif
   654                 // Register data read from Wishbone interface
   655                 wb_data_m <= d_dat_i;
   656                 // Don't set when stores complete - otherwise we'll deadlock if load in m stage
   657                 wb_load_complete <= !d_we_o;
   658             end
   659             // synthesis translate_off            
   660             if (d_err_i == `TRUE)
   661                 $display ("Data bus error. Address: %x", d_adr_o);
   662             // synthesis translate_on
   663         end
   664         else
   665         begin
   666 `ifdef CFG_DCACHE_ENABLED                
   667             if (dcache_refill_request == `TRUE)
   668             begin
   669                 // Start cache refill
   670                 d_adr_o <= first_address;
   671                 d_cyc_o <= `TRUE;
   672                 d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
   673                 d_stb_o <= `TRUE;                
   674                 d_we_o <= `FALSE;
   675                 d_cti_o <= first_cycle_type;
   676                 //d_lock_o <= `TRUE;
   677             end
   678             else 
   679 `endif            
   680                  if (   (store_q_m == `TRUE)
   681                      && (stall_m == `FALSE)
   682 `ifdef CFG_DRAM_ENABLED
   683                      && (dram_select_m == `FALSE)
   684 `endif
   685 `ifdef CFG_IROM_ENABLED
   686 		     && (irom_select_m == `FALSE)
   687 `endif			
   688                     )
   689             begin
   690                 // Data cache is write through, so all stores go to memory
   691                 d_dat_o <= store_data_m;
   692                 d_adr_o <= load_store_address_m;
   693                 d_cyc_o <= `TRUE;
   694                 d_sel_o <= byte_enable_m;
   695                 d_stb_o <= `TRUE;
   696                 d_we_o <= `TRUE;
   697                 d_cti_o <= `LM32_CTYPE_END;
   698             end        
   699             else if (   (load_q_m == `TRUE) 
   700                      && (wb_select_m == `TRUE) 
   701                      && (wb_load_complete == `FALSE)
   702                      // stall_m will be TRUE, because stall_wb_load will be TRUE 
   703                     )
   704             begin
   705                 // Read requested address
   706                 stall_wb_load <= `FALSE;
   707                 d_adr_o <= load_store_address_m;
   708                 d_cyc_o <= `TRUE;
   709                 d_sel_o <= byte_enable_m;
   710                 d_stb_o <= `TRUE;
   711                 d_we_o <= `FALSE;
   712                 d_cti_o <= `LM32_CTYPE_END;
   713             end
   714         end
   715         // Clear load/store complete flag when instruction leaves M stage
   716         if (stall_m == `FALSE)
   717             wb_load_complete <= `FALSE;
   718         // When a Wishbone load first enters the M stage, we need to stall it
   719         if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
   720             stall_wb_load <= `TRUE;
   721         // Clear stall request if load instruction is killed
   722         if ((kill_m == `TRUE) || (exception_m == `TRUE))
   723             stall_wb_load <= `FALSE;
   724     end
   725 end
   727 // Pipeline registers  
   729 // X/M stage pipeline registers
   730 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   731 begin
   732     if (rst_i == `TRUE)
   733     begin
   734         sign_extend_m <= `FALSE;
   735         size_m <= 2'b00;
   736         byte_enable_m <= `FALSE;
   737         store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
   738 `ifdef CFG_DCACHE_ENABLED
   739         dcache_select_m <= `FALSE;
   740 `endif
   741 `ifdef CFG_DRAM_ENABLED
   742         dram_select_m <= `FALSE;
   743 `endif
   744 `ifdef CFG_IROM_ENABLED
   745         irom_select_m <= `FALSE;
   746 `endif
   747         wb_select_m <= `FALSE;        
   748     end
   749     else
   750     begin
   751         if (stall_m == `FALSE)
   752         begin
   753             sign_extend_m <= sign_extend_x;
   754             size_m <= size_x;
   755             byte_enable_m <= byte_enable_x;    
   756             store_data_m <= store_data_x;
   757 `ifdef CFG_DCACHE_ENABLED
   758             dcache_select_m <= dcache_select_x;
   759 `endif
   760 `ifdef CFG_DRAM_ENABLED
   761             dram_select_m <= dram_select_x;
   762 `endif
   763 `ifdef CFG_IROM_ENABLED
   764             irom_select_m <= irom_select_x;
   765 `endif
   766             wb_select_m <= wb_select_x;
   767         end
   768     end
   769 end
   771 // M/W stage pipeline registers
   772 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   773 begin
   774     if (rst_i == `TRUE)
   775     begin
   776         size_w <= 2'b00;
   777         data_w <= {`LM32_WORD_WIDTH{1'b0}};
   778         sign_extend_w <= `FALSE;
   779     end
   780     else
   781     begin
   782         size_w <= size_m;
   783         data_w <= data_m;
   784         sign_extend_w <= sign_extend_m;
   785     end
   786 end
   788 /////////////////////////////////////////////////////
   789 // Behavioural Logic
   790 /////////////////////////////////////////////////////
   792 // synthesis translate_off
   794 // Check for non-aligned loads or stores
   795 always @(posedge clk_i)
   796 begin
   797     if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE)) 
   798     begin
   799         if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
   800             $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
   801         if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
   802             $display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
   803     end
   804 end
   806 // synthesis translate_on
   808 endmodule