Sun, 04 Apr 2010 20:42:58 +0100
remove need for system_conf.v
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_include.v
19 // Title : CPU global macros
20 // Version : 6.1.17
21 // : Initial Release
22 // Version : 7.0SP2, 3.0
23 // : No Change
24 // Version : 3.1
25 // : No Change
26 // Version : 3.2
27 // : No Change
28 // Version : 3.3
29 // : Support for extended configuration register
30 // =============================================================================
32 `ifdef LM32_INCLUDE_V
33 `else
34 `define LM32_INCLUDE_V
36 // (config opts from http://www.reflextor.org/trac/a51/browser/fpga/main/cores/lm32/rtl/lm32_include.v?rev=20)
37 //
38 // Common configuration options
39 //
41 `define CFG_EBA_RESET 32'h0
42 `define CFG_DEBA_RESET 32'h0
44 `define CFG_PL_MULTIPLY_ENABLED
45 `define CFG_PL_BARREL_SHIFT_ENABLED
46 `define CFG_SIGN_EXTEND_ENABLED
47 `define CFG_MC_DIVIDE_ENABLED
49 // Bug in Mico32/Xst ?
50 // CFG_ICACHE_ASSOCIATIVITY=2 => works fine
51 // CFG_ICACHE_ASSOCIATIVITY=1 => disaster
52 // TODO: try with the expensive synthesizers
53 `define CFG_ICACHE_ENABLED
54 `define CFG_ICACHE_ASSOCIATIVITY 2
55 `define CFG_ICACHE_SETS 512
56 `define CFG_ICACHE_BYTES_PER_LINE 16
57 `define CFG_ICACHE_BASE_ADDRESS 32'h0
58 `define CFG_ICACHE_LIMIT 32'h7fffffff
60 `define CFG_DCACHE_ENABLED
61 `define CFG_DCACHE_ASSOCIATIVITY 2
62 `define CFG_DCACHE_SETS 512
63 `define CFG_DCACHE_BYTES_PER_LINE 16
64 `define CFG_DCACHE_BASE_ADDRESS 32'h0
65 `define CFG_DCACHE_LIMIT 32'h7fffffff
67 //
68 // End of common configuration options
69 //
71 `ifdef TRUE
72 `else
73 `define TRUE 1'b1
74 `define FALSE 1'b0
75 `define TRUE_N 1'b0
76 `define FALSE_N 1'b1
77 `endif
79 // Wishbone configuration
80 `define CFG_IWB_ENABLED
81 `define CFG_DWB_ENABLED
83 // Data-path width
84 `define LM32_WORD_WIDTH 32
85 `define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0
86 `define LM32_SHIFT_WIDTH 5
87 `define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0
88 `define LM32_BYTE_SELECT_WIDTH 4
89 `define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0
91 // Register file size
92 `define LM32_REGISTERS 32
93 `define LM32_REG_IDX_WIDTH 5
94 `define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0
96 // Standard register numbers
97 `define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29
98 `define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30
99 `define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31
101 // Range of Program Counter. Two LSBs are always 0.
102 // `ifdef CFG_ICACHE_ENABLED
103 // `define LM32_PC_WIDTH (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
104 // `else
105 // `ifdef CFG_IWB_ENABLED
106 `define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2)
107 // `else
108 // `define LM32_PC_WIDTH `LM32_IROM_ADDRESS_WIDTH
109 // `endif
110 // `endif
111 `define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2
113 // Range of an instruction
114 `define LM32_INSTRUCTION_WIDTH 32
115 `define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0
117 // Adder operation
118 `define LM32_ADDER_OP_ADD 1'b0
119 `define LM32_ADDER_OP_SUBTRACT 1'b1
121 // Shift direction
122 `define LM32_SHIFT_OP_RIGHT 1'b0
123 `define LM32_SHIFT_OP_LEFT 1'b1
125 // Currently always enabled
126 `define CFG_BUS_ERRORS_ENABLED
128 // Derive macro that indicates whether we have single-stepping or not
129 `ifdef CFG_ROM_DEBUG_ENABLED
130 `define LM32_SINGLE_STEP_ENABLED
131 `else
132 `ifdef CFG_HW_DEBUG_ENABLED
133 `define LM32_SINGLE_STEP_ENABLED
134 `endif
135 `endif
137 // Derive macro that indicates whether JTAG interface is required
138 `ifdef CFG_JTAG_UART_ENABLED
139 `define LM32_JTAG_ENABLED
140 `else
141 `ifdef CFG_DEBUG_ENABLED
142 `define LM32_JTAG_ENABLED
143 `else
144 `endif
145 `endif
147 // Derive macro that indicates whether we have a barrel-shifter or not
148 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
149 `define LM32_BARREL_SHIFT_ENABLED
150 `else // CFG_PL_BARREL_SHIFT_ENABLED
151 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
152 `define LM32_BARREL_SHIFT_ENABLED
153 `else
154 `define LM32_NO_BARREL_SHIFT
155 `endif
156 `endif // CFG_PL_BARREL_SHIFT_ENABLED
158 // Derive macro that indicates whether we have a multiplier or not
159 `ifdef CFG_PL_MULTIPLY_ENABLED
160 `define LM32_MULTIPLY_ENABLED
161 `else
162 `ifdef CFG_MC_MULTIPLY_ENABLED
163 `define LM32_MULTIPLY_ENABLED
164 `endif
165 `endif
167 // Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
168 `ifdef CFG_MC_DIVIDE_ENABLED
169 `define LM32_MC_ARITHMETIC_ENABLED
170 `endif
171 `ifdef CFG_MC_MULTIPLY_ENABLED
172 `define LM32_MC_ARITHMETIC_ENABLED
173 `endif
174 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
175 `define LM32_MC_ARITHMETIC_ENABLED
176 `endif
178 // Derive macro that indicates if we are using an EBR register file
179 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
180 `define LM32_EBR_REGISTER_FILE
181 `endif
182 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
183 `define LM32_EBR_REGISTER_FILE
184 `endif
186 // Revision number
187 `define LM32_REVISION 6'h02
189 // Logical operations - Function encoded directly in instruction
190 `define LM32_LOGIC_OP_RNG 3:0
192 // Conditions for conditional branches
193 `define LM32_CONDITION_WIDTH 3
194 `define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0
195 `define LM32_CONDITION_E 3'b001
196 `define LM32_CONDITION_G 3'b010
197 `define LM32_CONDITION_GE 3'b011
198 `define LM32_CONDITION_GEU 3'b100
199 `define LM32_CONDITION_GU 3'b101
200 `define LM32_CONDITION_NE 3'b111
201 `define LM32_CONDITION_U1 3'b000
202 `define LM32_CONDITION_U2 3'b110
204 // Size of load or store instruction - Encoding corresponds to opcode
205 `define LM32_SIZE_WIDTH 2
206 `define LM32_SIZE_RNG 1:0
207 `define LM32_SIZE_BYTE 2'b00
208 `define LM32_SIZE_HWORD 2'b11
209 `define LM32_SIZE_WORD 2'b10
210 `define LM32_ADDRESS_LSBS_WIDTH 2
212 // Width and range of a CSR index
213 `ifdef CFG_DEBUG_ENABLED
214 `define LM32_CSR_WIDTH 5
215 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
216 `else
217 `ifdef CFG_JTAG_ENABLED
218 `define LM32_CSR_WIDTH 4
219 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
220 `else
221 `define LM32_CSR_WIDTH 3
222 `define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
223 `endif
224 `endif
226 // CSR indices
227 `define LM32_CSR_IE `LM32_CSR_WIDTH'h0
228 `define LM32_CSR_IM `LM32_CSR_WIDTH'h1
229 `define LM32_CSR_IP `LM32_CSR_WIDTH'h2
230 `define LM32_CSR_ICC `LM32_CSR_WIDTH'h3
231 `define LM32_CSR_DCC `LM32_CSR_WIDTH'h4
232 `define LM32_CSR_CC `LM32_CSR_WIDTH'h5
233 `define LM32_CSR_CFG `LM32_CSR_WIDTH'h6
234 `define LM32_CSR_EBA `LM32_CSR_WIDTH'h7
235 `ifdef CFG_DEBUG_ENABLED
236 `define LM32_CSR_DC `LM32_CSR_WIDTH'h8
237 `define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9
238 `endif
239 `define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha
240 `ifdef CFG_JTAG_ENABLED
241 `define LM32_CSR_JTX `LM32_CSR_WIDTH'he
242 `define LM32_CSR_JRX `LM32_CSR_WIDTH'hf
243 `endif
244 `ifdef CFG_DEBUG_ENABLED
245 `define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10
246 `define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11
247 `define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12
248 `define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13
249 `define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18
250 `define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19
251 `define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a
252 `define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
253 `endif
255 // Values for WPC CSR
256 `define LM32_WPC_C_RNG 1:0
257 `define LM32_WPC_C_DISABLED 2'b00
258 `define LM32_WPC_C_READ 2'b01
259 `define LM32_WPC_C_WRITE 2'b10
260 `define LM32_WPC_C_READ_WRITE 2'b11
262 // Exception IDs
263 `define LM32_EID_WIDTH 3
264 `define LM32_EID_RNG (`LM32_EID_WIDTH-1):0
265 `define LM32_EID_RESET 3'h0
266 `define LM32_EID_BREAKPOINT 3'd1
267 `define LM32_EID_INST_BUS_ERROR 3'h2
268 `define LM32_EID_WATCHPOINT 3'd3
269 `define LM32_EID_DATA_BUS_ERROR 3'h4
270 `define LM32_EID_DIVIDE_BY_ZERO 3'h5
271 `define LM32_EID_INTERRUPT 3'h6
272 `define LM32_EID_SCALL 3'h7
274 // Pipeline result selection mux controls
276 `define LM32_D_RESULT_SEL_0_RNG 0:0
277 `define LM32_D_RESULT_SEL_0_REG_0 1'b0
278 `define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1
280 `define LM32_D_RESULT_SEL_1_RNG 1:0
281 `define LM32_D_RESULT_SEL_1_ZERO 2'b00
282 `define LM32_D_RESULT_SEL_1_REG_1 2'b01
283 `define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10
285 `define LM32_USER_OPCODE_WIDTH 11
286 `define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0
288 // Derive a macro to indicate if either of the caches are implemented
289 `ifdef CFG_ICACHE_ENABLED
290 `define LM32_CACHE_ENABLED
291 `else
292 `ifdef CFG_DCACHE_ENABLED
293 `define LM32_CACHE_ENABLED
294 `endif
295 `endif
297 /////////////////////////////////////////////////////
298 // Interrupts
299 /////////////////////////////////////////////////////
301 // Always enable interrupts
302 `define CFG_INTERRUPTS_ENABLED
304 // Currently this is fixed to 32 and should not be changed
305 `define CFG_INTERRUPTS 32
306 `define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS
307 `define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0
309 /////////////////////////////////////////////////////
310 // General
311 /////////////////////////////////////////////////////
313 // Sub-word range types
314 `define LM32_BYTE_WIDTH 8
315 `define LM32_BYTE_RNG 7:0
316 `define LM32_HWORD_WIDTH 16
317 `define LM32_HWORD_RNG 15:0
319 // Word sub-byte indicies
320 `define LM32_BYTE_0_RNG 7:0
321 `define LM32_BYTE_1_RNG 15:8
322 `define LM32_BYTE_2_RNG 23:16
323 `define LM32_BYTE_3_RNG 31:24
325 // Word sub-halfword indices
326 `define LM32_HWORD_0_RNG 15:0
327 `define LM32_HWORD_1_RNG 31:16
329 // Use an asynchronous reset
330 // To use a synchronous reset, define this macro as nothing
331 `define CFG_RESET_SENSITIVITY
333 // V.T. Srce
334 `define SRCE
336 // Whether to include context registers for debug exceptions
337 // in addition to standard exception handling registers
338 // Bizarre - Removing this increases LUT count!
339 `define CFG_DEBUG_EXCEPTIONS_ENABLED
341 // Wishbone defines
342 // Refer to Wishbone System-on-Chip Interconnection Architecture
343 // These should probably be moved to a Wishbone common file
345 // Wishbone cycle types
346 `define LM32_CTYPE_WIDTH 3
347 `define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0
348 `define LM32_CTYPE_CLASSIC 3'b000
349 `define LM32_CTYPE_CONSTANT 3'b001
350 `define LM32_CTYPE_INCREMENTING 3'b010
351 `define LM32_CTYPE_END 3'b111
353 // Wishbone burst types
354 `define LM32_BTYPE_WIDTH 2
355 `define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0
356 `define LM32_BTYPE_LINEAR 2'b00
357 `define LM32_BTYPE_4_BEAT 2'b01
358 `define LM32_BTYPE_8_BEAT 2'b10
359 `define LM32_BTYPE_16_BEAT 2'b11
361 `endif