jtag_lm32.v

Sun, 04 Apr 2010 22:05:07 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 04 Apr 2010 22:05:07 +0100
changeset 3
b153470d41c5
parent 0
cd0b58aa6f83
child 26
73de224304c1
permissions
-rw-r--r--

remove more Lattice-specific fluff

Code now synthesizes properly on Altera Quartus 9.0 build 235

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : jtag_lm32.v
    19 // Title            : JTAG data register for LM32 CPU debug interface
    20 // Version          : 6.0.13
    21 //                  : Initial Release
    22 // Version          : 7.0SP2, 3.0
    23 //                  : No Change
    24 // Version          : 3.1
    25 //                  : No Change
    26 // =============================================================================
    28 /////////////////////////////////////////////////////
    29 // Module interface
    30 /////////////////////////////////////////////////////
    32 module jtag_lm32 (
    33 	input JTCK,
    34 	input JTDI,
    35 	output JTDO2,
    36 	input JSHIFT,
    37 	input JUPDATE,
    38 	input JRSTN,
    39 	input JCE2,
    40 	input JTAGREG_ENABLE,
    41 	input CONTROL_DATAN,
    42 	output REG_UPDATE,
    43 	input [7:0] REG_D,
    44 	input [2:0] REG_ADDR_D,
    45 	output [7:0] REG_Q,
    46 	output [2:0] REG_ADDR_Q
    47 	);
    49 /////////////////////////////////////////////////////
    50 // Internal nets and registers 
    51 /////////////////////////////////////////////////////
    53 wire [9:0] tdibus;
    55 /////////////////////////////////////////////////////
    56 // Instantiations
    57 /////////////////////////////////////////////////////
    59 TYPEA DATA_BIT0 (
    60     .CLK(JTCK),
    61     .RESET_N(JRSTN),
    62     .CLKEN(clk_enable),
    63     .TDI(JTDI),
    64     .TDO(tdibus[0]),
    65     .DATA_OUT(REG_Q[0]),
    66     .DATA_IN(REG_D[0]),
    67     .CAPTURE_DR(captureDr),
    68     .UPDATE_DR(JUPDATE)
    69     );
    71 TYPEA DATA_BIT1 (
    72     .CLK(JTCK),
    73     .RESET_N(JRSTN),
    74     .CLKEN(clk_enable),
    75     .TDI(tdibus[0]),
    76     .TDO(tdibus[1]),
    77     .DATA_OUT(REG_Q[1]),
    78     .DATA_IN(REG_D[1]),
    79     .CAPTURE_DR(captureDr),
    80     .UPDATE_DR(JUPDATE)
    81     );
    83 TYPEA DATA_BIT2 (
    84     .CLK(JTCK),
    85     .RESET_N(JRSTN),
    86     .CLKEN(clk_enable),
    87     .TDI(tdibus[1]),
    88     .TDO(tdibus[2]),
    89     .DATA_OUT(REG_Q[2]),
    90     .DATA_IN(REG_D[2]),
    91     .CAPTURE_DR(captureDr),
    92     .UPDATE_DR(JUPDATE)
    93     );
    95 TYPEA DATA_BIT3 (
    96     .CLK(JTCK),
    97     .RESET_N(JRSTN),
    98     .CLKEN(clk_enable),
    99     .TDI(tdibus[2]),
   100     .TDO(tdibus[3]),
   101     .DATA_OUT(REG_Q[3]),
   102     .DATA_IN(REG_D[3]),
   103     .CAPTURE_DR(captureDr),
   104     .UPDATE_DR(JUPDATE)
   105     );
   107 TYPEA DATA_BIT4 (
   108     .CLK(JTCK),
   109     .RESET_N(JRSTN),
   110     .CLKEN(clk_enable),
   111     .TDI(tdibus[3]),
   112     .TDO(tdibus[4]),
   113     .DATA_OUT(REG_Q[4]),
   114     .DATA_IN(REG_D[4]),
   115     .CAPTURE_DR(captureDr),
   116     .UPDATE_DR(JUPDATE)
   117     );
   119 TYPEA DATA_BIT5 (
   120     .CLK(JTCK),
   121     .RESET_N(JRSTN),
   122     .CLKEN(clk_enable),
   123     .TDI(tdibus[4]),
   124     .TDO(tdibus[5]),
   125     .DATA_OUT(REG_Q[5]),
   126     .DATA_IN(REG_D[5]),
   127     .CAPTURE_DR(captureDr),
   128     .UPDATE_DR(JUPDATE)
   129     );
   131 TYPEA DATA_BIT6 (
   132     .CLK(JTCK),
   133     .RESET_N(JRSTN),
   134     .CLKEN(clk_enable),
   135     .TDI(tdibus[5]),
   136     .TDO(tdibus[6]),
   137     .DATA_OUT(REG_Q[6]),
   138     .DATA_IN(REG_D[6]),
   139     .CAPTURE_DR(captureDr),
   140     .UPDATE_DR(JUPDATE)
   141     );
   143 TYPEA DATA_BIT7 (
   144     .CLK(JTCK),
   145     .RESET_N(JRSTN),
   146     .CLKEN(clk_enable),
   147     .TDI(tdibus[6]),
   148     .TDO(tdibus[7]),
   149     .DATA_OUT(REG_Q[7]),
   150     .DATA_IN(REG_D[7]),
   151     .CAPTURE_DR(captureDr),
   152     .UPDATE_DR(JUPDATE)
   153     );
   155 TYPEA ADDR_BIT0 (
   156     .CLK(JTCK),
   157     .RESET_N(JRSTN),
   158     .CLKEN(clk_enable),
   159     .TDI(tdibus[7]),
   160     .TDO(tdibus[8]),
   161     .DATA_OUT(REG_ADDR_Q[0]),
   162     .DATA_IN(REG_ADDR_D[0]),
   163     .CAPTURE_DR(captureDr),
   164     .UPDATE_DR(JUPDATE)
   165     );
   167 TYPEA ADDR_BIT1 (
   168     .CLK(JTCK),
   169     .RESET_N(JRSTN),
   170     .CLKEN(clk_enable),
   171     .TDI(tdibus[8]),
   172     .TDO(tdibus[9]),
   173     .DATA_OUT(REG_ADDR_Q[1]),
   174     .DATA_IN(REG_ADDR_D[1]),
   175     .CAPTURE_DR(captureDr),
   176     .UPDATE_DR(JUPDATE)
   177     );
   179 TYPEA ADDR_BIT2 (
   180     .CLK(JTCK),
   181     .RESET_N(JRSTN),
   182     .CLKEN(clk_enable),
   183     .TDI(tdibus[9]),
   184     .TDO(JTDO2),
   185     .DATA_OUT(REG_ADDR_Q[2]),
   186     .DATA_IN(REG_ADDR_D[2]),
   187     .CAPTURE_DR(captureDr),
   188     .UPDATE_DR(JUPDATE)
   189     );
   191 /////////////////////////////////////////////////////
   192 // Combinational logic
   193 /////////////////////////////////////////////////////
   195 assign clk_enable = JTAGREG_ENABLE & JCE2;
   196 assign captureDr = !JSHIFT & JCE2;
   197 // JCE2 is only active during shift
   198 assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
   200 endmodule