lm32_debug.v

Sun, 04 Apr 2010 22:05:07 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 04 Apr 2010 22:05:07 +0100
changeset 3
b153470d41c5
parent 0
cd0b58aa6f83
child 26
73de224304c1
permissions
-rw-r--r--

remove more Lattice-specific fluff

Code now synthesizes properly on Altera Quartus 9.0 build 235

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : lm32_debug.v
    19 // Title            : Hardware debug registers and associated logic.
    20 // Dependencies     : lm32_include.v
    21 // Version          : 6.1.17
    22 //                  : Initial Release
    23 // Version          : 7.0SP2, 3.0
    24 //                  : No Change
    25 // Version          : 3.1
    26 //                  : No Change
    27 // Version          : 3.2
    28 //                  : Fixed simulation bug which flares up when number of 
    29 //                  : watchpoints is zero.
    30 // =============================================================================
    32 `include "lm32_include.v"
    34 `ifdef CFG_DEBUG_ENABLED
    36 // States for single-step FSM
    37 `define LM32_DEBUG_SS_STATE_RNG                 2:0
    38 `define LM32_DEBUG_SS_STATE_IDLE                3'b000
    39 `define LM32_DEBUG_SS_STATE_WAIT_FOR_RET        3'b001
    40 `define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN    3'b010
    41 `define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT    3'b011
    42 `define LM32_DEBUG_SS_STATE_RESTART             3'b100
    44 /////////////////////////////////////////////////////
    45 // Module interface
    46 /////////////////////////////////////////////////////
    48 module lm32_debug (
    49     // ----- Inputs -------
    50     clk_i, 
    51     rst_i,
    52     pc_x,
    53     load_x,
    54     store_x,
    55     load_store_address_x,
    56     csr_write_enable_x,
    57     csr_write_data,
    58     csr_x,
    59 `ifdef CFG_HW_DEBUG_ENABLED
    60     jtag_csr_write_enable,
    61     jtag_csr_write_data,
    62     jtag_csr,
    63 `endif
    64 `ifdef LM32_SINGLE_STEP_ENABLED
    65     eret_q_x,
    66     bret_q_x,
    67     stall_x,
    68     exception_x,
    69     q_x,
    70 `ifdef CFG_DCACHE_ENABLED
    71     dcache_refill_request,
    72 `endif
    73 `endif
    74     // ----- Outputs -------
    75 `ifdef LM32_SINGLE_STEP_ENABLED
    76     dc_ss,
    77 `endif
    78     dc_re,
    79     bp_match,
    80     wp_match
    81     );
    83 /////////////////////////////////////////////////////
    84 // Parameters
    85 /////////////////////////////////////////////////////
    87 parameter breakpoints = 0;                      // Number of breakpoint CSRs
    88 parameter watchpoints = 0;                      // Number of watchpoint CSRs
    90 /////////////////////////////////////////////////////
    91 // Inputs
    92 /////////////////////////////////////////////////////
    94 input clk_i;                                    // Clock
    95 input rst_i;                                    // Reset
    97 input [`LM32_PC_RNG] pc_x;                      // X stage PC
    98 input load_x;                                   // Load instruction in X stage
    99 input store_x;                                  // Store instruction in X stage
   100 input [`LM32_WORD_RNG] load_store_address_x;    // Load or store effective address
   101 input csr_write_enable_x;                       // wcsr instruction in X stage
   102 input [`LM32_WORD_RNG] csr_write_data;          // Data to write to CSR
   103 input [`LM32_CSR_RNG] csr_x;                    // Which CSR to write
   104 `ifdef CFG_HW_DEBUG_ENABLED
   105 input jtag_csr_write_enable;                    // JTAG interface CSR write enable
   106 input [`LM32_WORD_RNG] jtag_csr_write_data;     // Data to write to CSR
   107 input [`LM32_CSR_RNG] jtag_csr;                 // Which CSR to write
   108 `endif
   109 `ifdef LM32_SINGLE_STEP_ENABLED
   110 input eret_q_x;                                 // eret instruction in X stage
   111 input bret_q_x;                                 // bret instruction in X stage
   112 input stall_x;                                  // Instruction in X stage is stalled
   113 input exception_x;                              // An exception has occured in X stage 
   114 input q_x;                                      // Indicates the instruction in the X stage is qualified
   115 `ifdef CFG_DCACHE_ENABLED
   116 input dcache_refill_request;                    // Indicates data cache wants to be refilled 
   117 `endif
   118 `endif
   120 /////////////////////////////////////////////////////
   121 // Outputs
   122 /////////////////////////////////////////////////////
   124 `ifdef LM32_SINGLE_STEP_ENABLED
   125 output dc_ss;                                   // Single-step enable
   126 reg    dc_ss;
   127 `endif
   128 output dc_re;                                   // Remap exceptions
   129 reg    dc_re;
   130 output bp_match;                                // Indicates a breakpoint has matched
   131 wire   bp_match;        
   132 output wp_match;                                // Indicates a watchpoint has matched
   133 wire   wp_match;
   135 /////////////////////////////////////////////////////
   136 // Internal nets and registers 
   137 /////////////////////////////////////////////////////
   139 genvar i;                                       // Loop index for generate statements
   141 // Debug CSRs
   143 reg [`LM32_PC_RNG] bp_a[0:breakpoints-1];       // Instruction breakpoint address
   144 reg bp_e[0:breakpoints-1];                      // Instruction breakpoint enable
   145 wire [0:breakpoints-1]bp_match_n;               // Indicates if a h/w instruction breakpoint matched
   147 reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1];   // Watchpoint enable
   148 reg [`LM32_WORD_RNG] wp[0:watchpoints-1];       // Watchpoint address
   149 wire [0:watchpoints]wp_match_n;               // Indicates if a h/w data watchpoint matched
   151 wire debug_csr_write_enable;                    // Debug CSR write enable (from either a wcsr instruction of external debugger)
   152 wire [`LM32_WORD_RNG] debug_csr_write_data;     // Data to write to debug CSR
   153 wire [`LM32_CSR_RNG] debug_csr;                 // Debug CSR to write to
   155 `ifdef LM32_SINGLE_STEP_ENABLED
   156 // FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
   157 //reg [`LM32_DEBUG_SS_STATE_RNG] state;           // State of single-step FSM
   158 integer state;                                  // State of single-step FSM
   159 `endif
   161 /////////////////////////////////////////////////////
   162 // Functions
   163 /////////////////////////////////////////////////////
   165 `include "lm32_functions.v"
   167 /////////////////////////////////////////////////////
   168 // Combinational Logic
   169 /////////////////////////////////////////////////////
   171 // Check for breakpoints
   172 generate
   173     for (i = 0; i < breakpoints; i = i + 1)
   174     begin : bp_comb
   175 assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
   176     end
   177 endgenerate
   178 generate 
   179 `ifdef LM32_SINGLE_STEP_ENABLED
   180     if (breakpoints > 0) 
   181 assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
   182     else
   183 assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
   184 `else
   185     if (breakpoints > 0) 
   186 assign bp_match = |bp_match_n;
   187     else
   188 assign bp_match = `FALSE;
   189 `endif
   190 endgenerate    
   192 // Check for watchpoints
   193 generate 
   194     for (i = 0; i < watchpoints; i = i + 1)
   195     begin : wp_comb
   196 assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
   197     end               
   198 endgenerate
   199 generate
   200     if (watchpoints > 0) 
   201 assign wp_match = |wp_match_n;                
   202     else
   203 assign wp_match = `FALSE;
   204 endgenerate
   206 `ifdef CFG_HW_DEBUG_ENABLED                
   207 // Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
   208 assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
   209 assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
   210 assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
   211 `else
   212 assign debug_csr_write_enable = csr_write_enable_x;
   213 assign debug_csr_write_data = csr_write_data;
   214 assign debug_csr = csr_x;
   215 `endif
   217 /////////////////////////////////////////////////////
   218 // Sequential Logic
   219 /////////////////////////////////////////////////////
   221 // Breakpoint address and enable CSRs
   222 generate
   223     for (i = 0; i < breakpoints; i = i + 1)
   224     begin : bp_seq
   225 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   226 begin
   227     if (rst_i == `TRUE)
   228     begin
   229         bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
   230         bp_e[i] <= `FALSE;
   231     end
   232     else
   233     begin
   234         if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
   235         begin
   236             bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
   237             bp_e[i] <= debug_csr_write_data[0];
   238         end
   239     end
   240 end    
   241     end
   242 endgenerate
   244 // Watchpoint address and control flags CSRs
   245 generate
   246     for (i = 0; i < watchpoints; i = i + 1)
   247     begin : wp_seq
   248 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   249 begin
   250     if (rst_i == `TRUE)
   251     begin
   252         wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
   253         wpc_c[i] <= `LM32_WPC_C_DISABLED;
   254     end
   255     else
   256     begin
   257         if (debug_csr_write_enable == `TRUE)
   258         begin
   259             if (debug_csr == `LM32_CSR_DC)
   260                 wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
   261             if (debug_csr == `LM32_CSR_WP0 + i)
   262                 wp[i] <= debug_csr_write_data;
   263         end
   264     end  
   265 end
   266     end
   267 endgenerate
   269 // Remap exceptions control bit
   270 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   271 begin
   272     if (rst_i == `TRUE)
   273         dc_re <= `FALSE;
   274     else
   275     begin
   276         if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
   277             dc_re <= debug_csr_write_data[1];
   278     end
   279 end    
   281 `ifdef LM32_SINGLE_STEP_ENABLED
   282 // Single-step control flag
   283 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   284 begin
   285     if (rst_i == `TRUE)
   286     begin
   287         state <= `LM32_DEBUG_SS_STATE_IDLE;
   288         dc_ss <= `FALSE;
   289     end
   290     else
   291     begin
   292         if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
   293         begin
   294             dc_ss <= debug_csr_write_data[0];
   295             if (debug_csr_write_data[0] == `FALSE) 
   296                 state <= `LM32_DEBUG_SS_STATE_IDLE;
   297             else 
   298                 state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
   299         end
   300         case (state)
   301         `LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
   302         begin
   303             // Wait for eret or bret instruction to be executed
   304             if (   (   (eret_q_x == `TRUE)
   305                     || (bret_q_x == `TRUE)
   306                     )
   307                 && (stall_x == `FALSE)
   308                )
   309                 state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN; 
   310         end
   311         `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
   312         begin
   313             // Wait for an instruction to be executed
   314             if ((q_x == `TRUE) && (stall_x == `FALSE))
   315                 state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
   316         end
   317         `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
   318         begin
   319             // Wait for exception to be raised
   320 `ifdef CFG_DCACHE_ENABLED
   321             if (dcache_refill_request == `TRUE)
   322                 state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
   323             else 
   324 `endif
   325                  if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
   326             begin
   327                 dc_ss <= `FALSE;
   328                 state <= `LM32_DEBUG_SS_STATE_RESTART;
   329             end
   330         end
   331         `LM32_DEBUG_SS_STATE_RESTART:
   332         begin
   333             // Watch to see if stepped instruction is restarted due to a cache miss
   334 `ifdef CFG_DCACHE_ENABLED
   335             if (dcache_refill_request == `TRUE)
   336                 state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
   337             else 
   338 `endif
   339                 state <= `LM32_DEBUG_SS_STATE_IDLE;
   340         end
   341         endcase
   342     end
   343 end
   344 `endif
   346 endmodule
   348 `endif