Sun, 06 Mar 2011 21:03:32 +0000
Commit GSI patches from Wesley Terpstra
- Add JTAG capture pin
==> allows removing sensitivity to reg_update which caused clocking problems making JTAG unstable
- Use register file backed by RAM blocks
==> saves quite some area and speed on altera
... be sure to enable it using `define CFG_EBR_POSEDGE_REGISTER_FILE
- Fix a minor problem where compilation fails when interrupts are not supported
- Add support to flush icache and dcache per JTAG
- Fix wrong width assignments for PC
Multiplier patch has been left out for now; don't the design synthesizers (Quartus / Xst) split the multiply automatically?
Original-Author: Wesley Terpstra <w.terpsta gsi.de>
Original-Source: Milkymist mailing list postings, 2011-02-28 (11:19 and 13:32) and 2011-03-01
Original-Message-Ids: <4D6B84B5.9040604@gsi.de> <4D6BA3E4.3020609@gsi.de> <4D6CFFF2.6030703@gsi.de>
1 // Modified by GSI to use simple positive edge clocking and the JTAG capture state
3 module jtag_cores (
4 input [7:0] reg_d,
5 input [2:0] reg_addr_d,
6 output reg_update,
7 output [7:0] reg_q,
8 output [2:0] reg_addr_q,
9 output jtck,
10 output jrstn
11 );
13 wire tck;
14 wire tdi;
15 wire tdo;
16 wire capture;
17 wire shift;
18 wire update;
19 wire e1dr;
20 wire reset;
22 jtag_tap jtag_tap (
23 .tck(tck),
24 .tdi(tdi),
25 .tdo(tdo),
26 .capture(capture),
27 .shift(shift),
28 .e1dr(e1dr),
29 .update(update),
30 .reset(reset)
31 );
33 reg [10:0] jtag_shift;
34 reg [10:0] jtag_latched;
36 always @(posedge tck)
37 begin
38 if(reset)
39 jtag_shift <= 11'b0;
40 else begin
41 if (shift)
42 jtag_shift <= {tdi, jtag_shift[10:1]};
43 else if (capture)
44 jtag_shift <= {reg_d, reg_addr_d};
45 end
46 end
48 assign tdo = jtag_shift[0];
50 always @(posedge tck)
51 begin
52 if(reset)
53 jtag_latched <= 11'b0;
54 else begin
55 if (e1dr)
56 jtag_latched <= jtag_shift;
57 end
58 end
60 assign reg_update = update;
61 assign reg_q = jtag_latched[10:3];
62 assign reg_addr_q = jtag_latched[2:0];
63 assign jtck = tck;
64 assign jrstn = ~reset;
66 endmodule