Sun, 06 Mar 2011 21:03:32 +0000
Commit GSI patches from Wesley Terpstra
- Add JTAG capture pin
==> allows removing sensitivity to reg_update which caused clocking problems making JTAG unstable
- Use register file backed by RAM blocks
==> saves quite some area and speed on altera
... be sure to enable it using `define CFG_EBR_POSEDGE_REGISTER_FILE
- Fix a minor problem where compilation fails when interrupts are not supported
- Add support to flush icache and dcache per JTAG
- Fix wrong width assignments for PC
Multiplier patch has been left out for now; don't the design synthesizers (Quartus / Xst) split the multiply automatically?
Original-Author: Wesley Terpstra <w.terpsta gsi.de>
Original-Source: Milkymist mailing list postings, 2011-02-28 (11:19 and 13:32) and 2011-03-01
Original-Message-Ids: <4D6B84B5.9040604@gsi.de> <4D6BA3E4.3020609@gsi.de> <4D6CFFF2.6030703@gsi.de>
1 module jtag_tap(
2 output tck,
3 output tdi,
4 input tdo,
5 output capture,
6 output shift,
7 output e1dr,
8 output update,
9 output reset
10 );
12 assign reset = 0;
13 wire nil1, nil2, nil3, nil4;
15 sld_virtual_jtag altera_jtag(
16 .ir_in (),
17 .ir_out (),
18 .tck (tck),
19 .tdo (tdo),
20 .tdi (tdi),
21 .virtual_state_cdr (capture),
22 .virtual_state_sdr (shift),
23 .virtual_state_e1dr (e1dr),
24 .virtual_state_pdr (nil1),
25 .virtual_state_e2dr (nil2),
26 .virtual_state_udr (update),
27 .virtual_state_cir (nil3),
28 .virtual_state_uir (nil4)
29 // synopsys translate_off
30 ,
31 .jtag_state_cdr (),
32 .jtag_state_cir (),
33 .jtag_state_e1dr (),
34 .jtag_state_e1ir (),
35 .jtag_state_e2dr (),
36 .jtag_state_e2ir (),
37 .jtag_state_pdr (),
38 .jtag_state_pir (),
39 .jtag_state_rti (),
40 .jtag_state_sdr (),
41 .jtag_state_sdrs (),
42 .jtag_state_sir (),
43 .jtag_state_sirs (),
44 .jtag_state_tlr (),
45 .jtag_state_udr (),
46 .jtag_state_uir (),
47 .tms ()
48 // synopsys translate_on
49 );
51 defparam
52 altera_jtag.sld_auto_instance_index = "YES",
53 altera_jtag.sld_instance_index = 0,
54 altera_jtag.sld_ir_width = 1,
55 altera_jtag.sld_sim_action = "",
56 altera_jtag.sld_sim_n_scan = 0,
57 altera_jtag.sld_sim_total_length = 0;
59 endmodule