Sun, 06 Mar 2011 21:03:32 +0000
Commit GSI patches from Wesley Terpstra
- Add JTAG capture pin
==> allows removing sensitivity to reg_update which caused clocking problems making JTAG unstable
- Use register file backed by RAM blocks
==> saves quite some area and speed on altera
... be sure to enable it using `define CFG_EBR_POSEDGE_REGISTER_FILE
- Fix a minor problem where compilation fails when interrupts are not supported
- Add support to flush icache and dcache per JTAG
- Fix wrong width assignments for PC
Multiplier patch has been left out for now; don't the design synthesizers (Quartus / Xst) split the multiply automatically?
Original-Author: Wesley Terpstra <w.terpsta gsi.de>
Original-Source: Milkymist mailing list postings, 2011-02-28 (11:19 and 13:32) and 2011-03-01
Original-Message-Ids: <4D6B84B5.9040604@gsi.de> <4D6BA3E4.3020609@gsi.de> <4D6CFFF2.6030703@gsi.de>
2 module jtag_tap(
3 output tck,
4 output tdi,
5 input tdo,
6 output capture,
7 output shift,
8 output e1dr,
9 output update,
10 output reset
11 );
13 // Unfortunately the exit1 state for DR (e1dr) is mising
14 // We can simulate it by interpretting 'update' as e1dr and delaying 'update'
15 wire g_capture;
16 wire g_shift;
17 wire g_update;
18 reg update_delay;
20 assign capture = g_capture & sel;
21 assign shift = g_shift & sel;
22 assign e1dr = g_update & sel;
23 assign update = update_delay;
25 BSCAN_SPARTAN6 #(
26 .JTAG_CHAIN(1)
27 ) bscan (
28 .CAPTURE(g_capture),
29 .DRCK(tck),
30 .RESET(reset),
31 .RUNTEST(),
32 .SEL(sel),
33 .SHIFT(g_shift),
34 .TCK(),
35 .TDI(tdi),
36 .TMS(),
37 .UPDATE(g_update),
38 .TDO(tdo)
39 );
41 update_delay <= g_update;
43 endmodule