lm32_cpu.v

Sun, 06 Mar 2011 21:03:32 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 21:03:32 +0000
changeset 18
cc945f778cd7
parent 14
54dd95f89113
child 23
252df75c8f67
permissions
-rwxr-xr-x

Commit GSI patches from Wesley Terpstra

- Add JTAG capture pin
==> allows removing sensitivity to reg_update which caused clocking problems making JTAG unstable
- Use register file backed by RAM blocks
==> saves quite some area and speed on altera
... be sure to enable it using `define CFG_EBR_POSEDGE_REGISTER_FILE
- Fix a minor problem where compilation fails when interrupts are not supported
- Add support to flush icache and dcache per JTAG
- Fix wrong width assignments for PC

Multiplier patch has been left out for now; don't the design synthesizers (Quartus / Xst) split the multiply automatically?

Original-Author: Wesley Terpstra <w.terpsta gsi.de>
Original-Source: Milkymist mailing list postings, 2011-02-28 (11:19 and 13:32) and 2011-03-01
Original-Message-Ids: <4D6B84B5.9040604@gsi.de> <4D6BA3E4.3020609@gsi.de> <4D6CFFF2.6030703@gsi.de>

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : lm32_cpu.v
    19 // Title            : Top-level of CPU.
    20 // Dependencies     : lm32_include.v
    21 //
    22 // Version 3.4
    23 // 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were 
    24 //    never serviced.
    25 //    
    26 // Version 3.3
    27 // 1. Feature: Support for memory that is tightly coupled to processor core, and 
    28 //    has a single-cycle access latency (same as caches). Instruction port has
    29 //    access to a dedicated physically-mapped memory. Data port has access to
    30 //    a dedicated physically-mapped memory. In order to be able to manipulate
    31 //    values in both these memories via the debugger, these memories also
    32 //    interface with the data port of LM32.
    33 // 2. Feature: Extended Configuration Register
    34 // 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
    35 //    Verilog.
    36 //
    37 // Version 3.2
    38 // 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
    39 //    hang. At the same time CPU fails to register data bus error exception. Bug
    40 //    is caused because (a) data bus error exception occurs after load/store has
    41 //    passed X stage and next sequential instruction (e.g., brk) is already in X
    42 //    stage, and (b) data bus error exception had lower priority than, say, brk
    43 //    exception.
    44 // 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
    45 //    invalid location, CPU will fail to register data bus error exception. The
    46 //    solution is to stall scall/eret/bret/brk instructions in D pipeline stage
    47 //    until load/store has completed.
    48 // 3. Feature: Enable precise identification of load/store that causes seg fault.
    49 // 4. SYNC resets used for register file when implemented in EBRs.
    50 //
    51 // Version 3.1
    52 // 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
    53 //    instead of distributed memory by enabling the option in LM32 GUI. 
    54 // 2. Feature: LM32 also adds a static branch predictor to improve branch 
    55 //    performance. All immediate-based forward-pointing branches are predicted 
    56 //    not-taken. All immediate-based backward-pointing branches are predicted taken.
    57 // 
    58 // Version 7.0SP2, 3.0
    59 // No Change
    60 //
    61 // Version 6.1.17
    62 // Initial Release
    63 // =============================================================================
    65 `include "lm32_include.v"
    67 /////////////////////////////////////////////////////
    68 // Module interface
    69 /////////////////////////////////////////////////////
    71 module lm32_cpu (
    72     // ----- Inputs -------
    73     clk_i,
    74 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
    75     clk_n_i,
    76 `endif    
    77     rst_i,
    78     // From external devices
    79 `ifdef CFG_INTERRUPTS_ENABLED
    80     interrupt,
    81 `endif
    82     // From user logic
    83 `ifdef CFG_USER_ENABLED
    84     user_result,
    85     user_complete,
    86 `endif     
    87 `ifdef CFG_JTAG_ENABLED
    88     // From JTAG
    89     jtag_clk,
    90     jtag_update, 
    91     jtag_reg_q,
    92     jtag_reg_addr_q,
    93 `endif
    94 `ifdef CFG_IWB_ENABLED
    95     // Instruction Wishbone master
    96     I_DAT_I,
    97     I_ACK_I,
    98     I_ERR_I,
    99     I_RTY_I,
   100 `endif
   101     // Data Wishbone master
   102     D_DAT_I,
   103     D_ACK_I,
   104     D_ERR_I,
   105     D_RTY_I,
   106     // ----- Outputs -------
   107 `ifdef CFG_TRACE_ENABLED
   108     trace_pc,
   109     trace_pc_valid,
   110     trace_exception,
   111     trace_eid,
   112     trace_eret,
   113 `ifdef CFG_DEBUG_ENABLED
   114     trace_bret,
   115 `endif
   116 `endif
   117 `ifdef CFG_JTAG_ENABLED
   118     jtag_reg_d,
   119     jtag_reg_addr_d,
   120 `endif
   121 `ifdef CFG_USER_ENABLED    
   122     user_valid,
   123     user_opcode,
   124     user_operand_0,
   125     user_operand_1,
   126 `endif    
   127 `ifdef CFG_IWB_ENABLED
   128     // Instruction Wishbone master
   129     I_DAT_O,
   130     I_ADR_O,
   131     I_CYC_O,
   132     I_SEL_O,
   133     I_STB_O,
   134     I_WE_O,
   135     I_CTI_O,
   136     I_LOCK_O,
   137     I_BTE_O,
   138 `endif
   139     // Data Wishbone master
   140     D_DAT_O,
   141     D_ADR_O,
   142     D_CYC_O,
   143     D_SEL_O,
   144     D_STB_O,
   145     D_WE_O,
   146     D_CTI_O,
   147     D_LOCK_O,
   148     D_BTE_O
   149     );
   151 /////////////////////////////////////////////////////
   152 // Parameters
   153 /////////////////////////////////////////////////////
   155 parameter eba_reset = `CFG_EBA_RESET;                           // Reset value for EBA CSR
   156 `ifdef CFG_DEBUG_ENABLED
   157 parameter deba_reset = `CFG_DEBA_RESET;                         // Reset value for DEBA CSR
   158 `endif
   160 `ifdef CFG_ICACHE_ENABLED
   161 parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
   162 parameter icache_sets = `CFG_ICACHE_SETS;                       // Number of sets
   163 parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE;   // Number of bytes per cache line
   164 parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS;       // Base address of cachable memory
   165 parameter icache_limit = `CFG_ICACHE_LIMIT;                     // Limit (highest address) of cachable memory
   166 `else
   167 parameter icache_associativity = 1;    
   168 parameter icache_sets = 512;                      
   169 parameter icache_bytes_per_line = 16;  
   170 parameter icache_base_address = 0;      
   171 parameter icache_limit = 0;                    
   172 `endif
   174 `ifdef CFG_DCACHE_ENABLED
   175 parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY;     // Associativity of the cache (Number of ways)
   176 parameter dcache_sets = `CFG_DCACHE_SETS;                       // Number of sets
   177 parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE;   // Number of bytes per cache line
   178 parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS;       // Base address of cachable memory
   179 parameter dcache_limit = `CFG_DCACHE_LIMIT;                     // Limit (highest address) of cachable memory
   180 `else
   181 parameter dcache_associativity = 1;    
   182 parameter dcache_sets = 512;                      
   183 parameter dcache_bytes_per_line = 16;  
   184 parameter dcache_base_address = 0;      
   185 parameter dcache_limit = 0;                    
   186 `endif
   188 `ifdef CFG_DEBUG_ENABLED
   189 parameter watchpoints = `CFG_WATCHPOINTS;                       // Number of h/w watchpoint CSRs
   190 `else
   191 parameter watchpoints = 0;
   192 `endif
   193 `ifdef CFG_ROM_DEBUG_ENABLED
   194 parameter breakpoints = `CFG_BREAKPOINTS;                       // Number of h/w breakpoint CSRs
   195 `else
   196 parameter breakpoints = 0;
   197 `endif
   199 `ifdef CFG_INTERRUPTS_ENABLED
   200 parameter interrupts = `CFG_INTERRUPTS;                         // Number of interrupts
   201 `else
   202 parameter interrupts = 0;
   203 `endif
   205 /////////////////////////////////////////////////////
   206 // Inputs
   207 /////////////////////////////////////////////////////
   209 input clk_i;                                    // Clock
   210 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
   211 input clk_n_i;                                  // Inverted clock
   212 `endif    
   213 input rst_i;                                    // Reset
   215 `ifdef CFG_INTERRUPTS_ENABLED
   216 input [`LM32_INTERRUPT_RNG] interrupt;          // Interrupt pins
   217 `endif
   219 `ifdef CFG_USER_ENABLED
   220 input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
   221 input user_complete;                            // User-defined instruction execution is complete
   222 `endif    
   224 `ifdef CFG_JTAG_ENABLED
   225 input jtag_clk;                                 // JTAG clock
   226 input jtag_update;                              // JTAG state machine is in data register update state
   227 input [`LM32_BYTE_RNG] jtag_reg_q;              
   228 input [2:0] jtag_reg_addr_q;
   229 `endif
   231 `ifdef CFG_IWB_ENABLED
   232 input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
   233 input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
   234 input I_ERR_I;                                  // Instruction Wishbone interface error
   235 input I_RTY_I;                                  // Instruction Wishbone interface retry
   236 `endif
   238 input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
   239 input D_ACK_I;                                  // Data Wishbone interface acknowledgement
   240 input D_ERR_I;                                  // Data Wishbone interface error
   241 input D_RTY_I;                                  // Data Wishbone interface retry
   243 /////////////////////////////////////////////////////
   244 // Outputs
   245 /////////////////////////////////////////////////////
   247 `ifdef CFG_TRACE_ENABLED
   248 output [`LM32_PC_RNG] trace_pc;                 // PC to trace
   249 reg    [`LM32_PC_RNG] trace_pc;
   250 output trace_pc_valid;                          // Indicates that a new trace PC is valid
   251 reg    trace_pc_valid;
   252 output trace_exception;                         // Indicates an exception has occured
   253 reg    trace_exception;
   254 output [`LM32_EID_RNG] trace_eid;               // Indicates what type of exception has occured
   255 reg    [`LM32_EID_RNG] trace_eid;
   256 output trace_eret;                              // Indicates an eret instruction has been executed
   257 reg    trace_eret;
   258 `ifdef CFG_DEBUG_ENABLED
   259 output trace_bret;                              // Indicates a bret instruction has been executed
   260 reg    trace_bret;
   261 `endif
   262 `endif
   264 `ifdef CFG_JTAG_ENABLED
   265 output [`LM32_BYTE_RNG] jtag_reg_d;
   266 wire   [`LM32_BYTE_RNG] jtag_reg_d;
   267 output [2:0] jtag_reg_addr_d;
   268 wire   [2:0] jtag_reg_addr_d;
   269 `endif
   271 `ifdef CFG_USER_ENABLED
   272 output user_valid;                              // Indicates if user_opcode is valid
   273 wire   user_valid;
   274 output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
   275 reg    [`LM32_USER_OPCODE_RNG] user_opcode;
   276 output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
   277 wire   [`LM32_WORD_RNG] user_operand_0;
   278 output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
   279 wire   [`LM32_WORD_RNG] user_operand_1;
   280 `endif
   282 `ifdef CFG_IWB_ENABLED
   283 output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
   284 wire   [`LM32_WORD_RNG] I_DAT_O;
   285 output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
   286 wire   [`LM32_WORD_RNG] I_ADR_O;
   287 output I_CYC_O;                                 // Instruction Wishbone interface cycle
   288 wire   I_CYC_O;
   289 output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
   290 wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
   291 output I_STB_O;                                 // Instruction Wishbone interface strobe
   292 wire   I_STB_O;
   293 output I_WE_O;                                  // Instruction Wishbone interface write enable
   294 wire   I_WE_O;
   295 output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type 
   296 wire   [`LM32_CTYPE_RNG] I_CTI_O;
   297 output I_LOCK_O;                                // Instruction Wishbone interface lock bus
   298 wire   I_LOCK_O;
   299 output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type 
   300 wire   [`LM32_BTYPE_RNG] I_BTE_O;
   301 `endif
   303 output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
   304 wire   [`LM32_WORD_RNG] D_DAT_O;
   305 output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
   306 wire   [`LM32_WORD_RNG] D_ADR_O;
   307 output D_CYC_O;                                 // Data Wishbone interface cycle
   308 wire   D_CYC_O;
   309 output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
   310 wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
   311 output D_STB_O;                                 // Data Wishbone interface strobe
   312 wire   D_STB_O;
   313 output D_WE_O;                                  // Data Wishbone interface write enable
   314 wire   D_WE_O;
   315 output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type 
   316 wire   [`LM32_CTYPE_RNG] D_CTI_O;
   317 output D_LOCK_O;                                // Date Wishbone interface lock bus
   318 wire   D_LOCK_O;
   319 output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type 
   320 wire   [`LM32_BTYPE_RNG] D_BTE_O;
   322 /////////////////////////////////////////////////////
   323 // Internal nets and registers 
   324 /////////////////////////////////////////////////////
   326 // Pipeline registers
   328 `ifdef LM32_CACHE_ENABLED
   329 reg valid_a;                                    // Instruction in A stage is valid
   330 `endif
   331 reg valid_f;                                    // Instruction in F stage is valid
   332 reg valid_d;                                    // Instruction in D stage is valid
   333 reg valid_x;                                    // Instruction in X stage is valid
   334 reg valid_m;                                    // Instruction in M stage is valid
   335 reg valid_w;                                    // Instruction in W stage is valid
   337 wire q_x;
   338 wire [`LM32_WORD_RNG] immediate_d;              // Immediate operand
   339 wire load_d;                                    // Indicates a load instruction
   340 reg load_x;                                     
   341 reg load_m;
   342 wire load_q_x;
   343 wire store_q_x;
   344 wire store_d;                                   // Indicates a store instruction
   345 reg store_x;
   346 reg store_m;
   347 wire [`LM32_SIZE_RNG] size_d;                   // Size of load/store (byte, hword, word)
   348 reg [`LM32_SIZE_RNG] size_x;
   349 wire branch_d;                                  // Indicates a branch instruction
   350 wire branch_predict_d;                          // Indicates a branch is predicted
   351 wire branch_predict_taken_d;                    // Indicates a branch is predicted taken
   352 wire [`LM32_PC_RNG] branch_predict_address_d;   // Address to which predicted branch jumps
   353 wire [`LM32_PC_RNG] branch_target_d;
   354 wire bi_unconditional;
   355 wire bi_conditional;
   356 reg branch_x;                                   
   357 reg branch_predict_x;
   358 reg branch_predict_taken_x;
   359 reg branch_m;
   360 reg branch_predict_m;
   361 reg branch_predict_taken_m;
   362 wire branch_mispredict_taken_m;                 // Indicates a branch was mispredicted as taken
   363 wire branch_flushX_m;                           // Indicates that instruction in X stage must be squashed
   364 wire branch_reg_d;                              // Branch to register or immediate
   365 wire [`LM32_PC_RNG] branch_offset_d;            // Branch offset for immediate branches
   366 reg [`LM32_PC_RNG] branch_target_x;             // Address to branch to
   367 reg [`LM32_PC_RNG] branch_target_m;
   368 wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
   369 wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
   371 wire x_result_sel_csr_d;                        // Select X stage result from CSRs
   372 reg x_result_sel_csr_x;
   373 `ifdef LM32_MC_ARITHMETIC_ENABLED
   374 wire x_result_sel_mc_arith_d;                   // Select X stage result from multi-cycle arithmetic unit
   375 reg x_result_sel_mc_arith_x;
   376 `endif
   377 `ifdef LM32_NO_BARREL_SHIFT    
   378 wire x_result_sel_shift_d;                      // Select X stage result from shifter
   379 reg x_result_sel_shift_x;
   380 `endif
   381 `ifdef CFG_SIGN_EXTEND_ENABLED
   382 wire x_result_sel_sext_d;                       // Select X stage result from sign-extend logic
   383 reg x_result_sel_sext_x;
   384 `endif
   385 wire x_result_sel_logic_d;                      // Select X stage result from logic op unit
   386 reg x_result_sel_logic_x;
   387 `ifdef CFG_USER_ENABLED
   388 wire x_result_sel_user_d;                       // Select X stage result from user-defined logic
   389 reg x_result_sel_user_x;
   390 `endif
   391 wire x_result_sel_add_d;                        // Select X stage result from adder
   392 reg x_result_sel_add_x;
   393 wire m_result_sel_compare_d;                    // Select M stage result from comparison logic
   394 reg m_result_sel_compare_x;
   395 reg m_result_sel_compare_m;
   396 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   397 wire m_result_sel_shift_d;                      // Select M stage result from shifter
   398 reg m_result_sel_shift_x;
   399 reg m_result_sel_shift_m;
   400 `endif
   401 wire w_result_sel_load_d;                       // Select W stage result from load/store unit
   402 reg w_result_sel_load_x;
   403 reg w_result_sel_load_m;
   404 reg w_result_sel_load_w;
   405 `ifdef CFG_PL_MULTIPLY_ENABLED
   406 wire w_result_sel_mul_d;                        // Select W stage result from multiplier
   407 reg w_result_sel_mul_x;
   408 reg w_result_sel_mul_m;
   409 reg w_result_sel_mul_w;
   410 `endif
   411 wire x_bypass_enable_d;                         // Whether result is bypassable in X stage
   412 reg x_bypass_enable_x;                          
   413 wire m_bypass_enable_d;                         // Whether result is bypassable in M stage
   414 reg m_bypass_enable_x;                          
   415 reg m_bypass_enable_m;
   416 wire sign_extend_d;                             // Whether to sign-extend or zero-extend
   417 reg sign_extend_x;
   418 wire write_enable_d;                            // Register file write enable
   419 reg write_enable_x;
   420 wire write_enable_q_x;
   421 reg write_enable_m;
   422 wire write_enable_q_m;
   423 reg write_enable_w;
   424 wire write_enable_q_w;
   425 wire read_enable_0_d;                           // Register file read enable 0
   426 wire [`LM32_REG_IDX_RNG] read_idx_0_d;          // Register file read index 0
   427 wire read_enable_1_d;                           // Register file read enable 1
   428 wire [`LM32_REG_IDX_RNG] read_idx_1_d;          // Register file read index 1
   429 wire [`LM32_REG_IDX_RNG] write_idx_d;           // Register file write index
   430 reg [`LM32_REG_IDX_RNG] write_idx_x;            
   431 reg [`LM32_REG_IDX_RNG] write_idx_m;
   432 reg [`LM32_REG_IDX_RNG] write_idx_w;
   433 wire [`LM32_CSR_RNG] csr_d;                     // CSR read/write index
   434 reg  [`LM32_CSR_RNG] csr_x;                  
   435 wire [`LM32_CONDITION_RNG] condition_d;         // Branch condition
   436 reg [`LM32_CONDITION_RNG] condition_x;          
   437 `ifdef CFG_DEBUG_ENABLED
   438 wire break_d;                                   // Indicates a break instruction
   439 reg break_x;                                    
   440 `endif
   441 wire scall_d;                                   // Indicates a scall instruction
   442 reg scall_x;    
   443 wire eret_d;                                    // Indicates an eret instruction
   444 reg eret_x;
   445 wire eret_q_x;
   446 reg eret_m;
   447 `ifdef CFG_TRACE_ENABLED
   448 reg eret_w;
   449 `endif
   450 `ifdef CFG_DEBUG_ENABLED
   451 wire bret_d;                                    // Indicates a bret instruction
   452 reg bret_x;
   453 wire bret_q_x;
   454 reg bret_m;
   455 `ifdef CFG_TRACE_ENABLED
   456 reg bret_w;
   457 `endif
   458 `endif
   459 wire csr_write_enable_d;                        // CSR write enable
   460 reg csr_write_enable_x;
   461 wire csr_write_enable_q_x;
   462 `ifdef CFG_USER_ENABLED
   463 wire [`LM32_USER_OPCODE_RNG] user_opcode_d;     // User-defined instruction opcode
   464 `endif
   466 `ifdef CFG_BUS_ERRORS_ENABLED
   467 wire bus_error_d;                               // Indicates an bus error occured while fetching the instruction in this pipeline stage
   468 reg bus_error_x;
   469 reg data_bus_error_exception_m;
   470 reg [`LM32_PC_RNG] memop_pc_w;
   471 `endif
   473 reg [`LM32_WORD_RNG] d_result_0;                // Result of instruction in D stage (operand 0)
   474 reg [`LM32_WORD_RNG] d_result_1;                // Result of instruction in D stage (operand 1)
   475 reg [`LM32_WORD_RNG] x_result;                  // Result of instruction in X stage
   476 reg [`LM32_WORD_RNG] m_result;                  // Result of instruction in M stage
   477 reg [`LM32_WORD_RNG] w_result;                  // Result of instruction in W stage
   479 reg [`LM32_WORD_RNG] operand_0_x;               // Operand 0 for X stage instruction
   480 reg [`LM32_WORD_RNG] operand_1_x;               // Operand 1 for X stage instruction
   481 reg [`LM32_WORD_RNG] store_operand_x;           // Data read from register to store
   482 reg [`LM32_WORD_RNG] operand_m;                 // Operand for M stage instruction
   483 reg [`LM32_WORD_RNG] operand_w;                 // Operand for W stage instruction
   485 // To/from register file
   486 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   487 reg [`LM32_WORD_RNG] reg_data_live_0;          
   488 reg [`LM32_WORD_RNG] reg_data_live_1;  
   489 reg use_buf;                                    // Whether to use reg_data_live or reg_data_buf
   490 reg [`LM32_WORD_RNG] reg_data_buf_0;
   491 reg [`LM32_WORD_RNG] reg_data_buf_1;
   492 `endif
   493 `ifdef LM32_EBR_REGISTER_FILE
   494 `else
   495 reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1];   // Register file
   496 `endif
   497 wire [`LM32_WORD_RNG] reg_data_0;               // Register file read port 0 data         
   498 wire [`LM32_WORD_RNG] reg_data_1;               // Register file read port 1 data
   499 reg [`LM32_WORD_RNG] bypass_data_0;             // Register value 0 after bypassing
   500 reg [`LM32_WORD_RNG] bypass_data_1;             // Register value 1 after bypassing
   501 wire reg_write_enable_q_w;
   503 reg interlock;                                  // Indicates pipeline should be stalled because of a read-after-write hazzard
   505 wire stall_a;                                   // Stall instruction in A pipeline stage
   506 wire stall_f;                                   // Stall instruction in F pipeline stage
   507 wire stall_d;                                   // Stall instruction in D pipeline stage
   508 wire stall_x;                                   // Stall instruction in X pipeline stage
   509 wire stall_m;                                   // Stall instruction in M pipeline stage
   511 // To/from adder
   512 wire adder_op_d;                                // Whether to add or subtract
   513 reg adder_op_x;                                 
   514 reg adder_op_x_n;                               // Inverted version of adder_op_x
   515 wire [`LM32_WORD_RNG] adder_result_x;           // Result from adder
   516 wire adder_overflow_x;                          // Whether a signed overflow occured
   517 wire adder_carry_n_x;                           // Whether a carry was generated
   519 // To/from logical operations unit
   520 wire [`LM32_LOGIC_OP_RNG] logic_op_d;           // Which operation to perform
   521 reg [`LM32_LOGIC_OP_RNG] logic_op_x;            
   522 wire [`LM32_WORD_RNG] logic_result_x;           // Result of logical operation
   524 `ifdef CFG_SIGN_EXTEND_ENABLED
   525 // From sign-extension unit
   526 wire [`LM32_WORD_RNG] sextb_result_x;           // Result of byte sign-extension
   527 wire [`LM32_WORD_RNG] sexth_result_x;           // Result of half-word sign-extenstion
   528 wire [`LM32_WORD_RNG] sext_result_x;            // Result of sign-extension specified by instruction
   529 `endif
   531 // To/from shifter
   532 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   533 `ifdef CFG_ROTATE_ENABLED
   534 wire rotate_d;                                  // Whether we should rotate or shift
   535 reg rotate_x;                                    
   536 `endif
   537 wire direction_d;                               // Which direction to shift in
   538 reg direction_x;                                        
   539 wire [`LM32_WORD_RNG] shifter_result_m;         // Result of shifter
   540 `endif
   541 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   542 wire shift_left_d;                              // Indicates whether to perform a left shift or not
   543 wire shift_left_q_d;
   544 wire shift_right_d;                             // Indicates whether to perform a right shift or not
   545 wire shift_right_q_d;
   546 `endif
   547 `ifdef LM32_NO_BARREL_SHIFT
   548 wire [`LM32_WORD_RNG] shifter_result_x;         // Result of single-bit right shifter
   549 `endif
   551 // To/from multiplier
   552 `ifdef LM32_MULTIPLY_ENABLED
   553 wire [`LM32_WORD_RNG] multiplier_result_w;      // Result from multiplier
   554 `endif
   555 `ifdef CFG_MC_MULTIPLY_ENABLED
   556 wire multiply_d;                                // Indicates whether to perform a multiply or not
   557 wire multiply_q_d;
   558 `endif
   560 // To/from divider
   561 `ifdef CFG_MC_DIVIDE_ENABLED
   562 wire divide_d;                                  // Indicates whether to perform a divider or not
   563 wire divide_q_d;
   564 wire modulus_d;
   565 wire modulus_q_d;
   566 wire divide_by_zero_x;                          // Indicates an attempt was made to divide by zero
   567 `endif
   569 // To from multi-cycle arithmetic unit
   570 `ifdef LM32_MC_ARITHMETIC_ENABLED
   571 wire mc_stall_request_x;                        // Multi-cycle arithmetic unit stall request
   572 wire [`LM32_WORD_RNG] mc_result_x;
   573 `endif
   575 // From CSRs
   576 `ifdef CFG_INTERRUPTS_ENABLED
   577 wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
   578 `endif
   579 wire [`LM32_WORD_RNG] cfg;                      // Configuration CSR
   580 wire [`LM32_WORD_RNG] cfg2;                     // Extended Configuration CSR
   581 `ifdef CFG_CYCLE_COUNTER_ENABLED
   582 reg [`LM32_WORD_RNG] cc;                        // Cycle counter CSR
   583 `endif
   584 reg [`LM32_WORD_RNG] csr_read_data_x;           // Data read from CSRs
   586 // To/from instruction unit
   587 wire [`LM32_PC_RNG] pc_f;                       // PC of instruction in F stage
   588 wire [`LM32_PC_RNG] pc_d;                       // PC of instruction in D stage
   589 wire [`LM32_PC_RNG] pc_x;                       // PC of instruction in X stage
   590 wire [`LM32_PC_RNG] pc_m;                       // PC of instruction in M stage
   591 wire [`LM32_PC_RNG] pc_w;                       // PC of instruction in W stage
   592 `ifdef CFG_TRACE_ENABLED
   593 reg [`LM32_PC_RNG] pc_c;                        // PC of last commited instruction
   594 `endif
   595 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   596 wire [`LM32_INSTRUCTION_RNG] instruction_f;     // Instruction in F stage
   597 `endif
   598 //pragma attribute instruction_d preserve_signal true
   599 //pragma attribute instruction_d preserve_driver true
   600 wire [`LM32_INSTRUCTION_RNG] instruction_d;     // Instruction in D stage
   601 `ifdef CFG_ICACHE_ENABLED
   602 wire iflush;                                    // Flush instruction cache
   603 wire icache_stall_request;                      // Stall pipeline because instruction cache is busy
   604 wire icache_restart_request;                    // Restart instruction that caused an instruction cache miss
   605 wire icache_refill_request;                     // Request to refill instruction cache
   606 wire icache_refilling;                          // Indicates the instruction cache is being refilled
   607 `endif
   608 `ifdef CFG_IROM_ENABLED
   609 wire [`LM32_WORD_RNG] irom_store_data_m;        // Store data to instruction ROM
   610 wire [`LM32_WORD_RNG] irom_address_xm;          // Address to instruction ROM from load-store unit
   611 wire [`LM32_WORD_RNG] irom_data_m;              // Load data from instruction ROM
   612 wire irom_we_xm;                                // Indicates data needs to be written to instruction ROM
   613 wire irom_stall_request_x;                      // Indicates D stage needs to be stalled on a store to instruction ROM
   614 `endif
   616 // To/from load/store unit
   617 `ifdef CFG_DCACHE_ENABLED
   618 wire dflush_x;                                  // Flush data cache    
   619 reg dflush_m;                                    
   620 wire dcache_stall_request;                      // Stall pipeline because data cache is busy
   621 wire dcache_restart_request;                    // Restart instruction that caused a data cache miss
   622 wire dcache_refill_request;                     // Request to refill data cache
   623 wire dcache_refilling;                          // Indicates the data cache is being refilled
   624 `endif
   625 wire [`LM32_WORD_RNG] load_data_w;              // Result of a load instruction
   626 wire stall_wb_load;                             // Stall pipeline because of a load via the data Wishbone interface
   628 // To/from JTAG interface
   629 `ifdef CFG_JTAG_ENABLED
   630 `ifdef CFG_JTAG_UART_ENABLED
   631 wire [`LM32_WORD_RNG] jtx_csr_read_data;        // Read data for JTX CSR
   632 wire [`LM32_WORD_RNG] jrx_csr_read_data;        // Read data for JRX CSR
   633 `endif
   634 `ifdef CFG_HW_DEBUG_ENABLED
   635 wire jtag_csr_write_enable;                     // Debugger CSR write enable
   636 wire [`LM32_WORD_RNG] jtag_csr_write_data;      // Data to write to specified CSR
   637 wire [`LM32_CSR_RNG] jtag_csr;                  // Which CSR to write
   638 wire jtag_read_enable;                          
   639 wire [`LM32_BYTE_RNG] jtag_read_data;
   640 wire jtag_write_enable;
   641 wire [`LM32_BYTE_RNG] jtag_write_data;
   642 wire [`LM32_WORD_RNG] jtag_address;
   643 wire jtag_access_complete;
   644 `endif
   645 `ifdef CFG_DEBUG_ENABLED
   646 wire jtag_break;                                // Request from debugger to raise a breakpoint
   647 `endif
   648 `endif
   650 // Hazzard detection
   651 wire raw_x_0;                                   // RAW hazzard between instruction in X stage and read port 0
   652 wire raw_x_1;                                   // RAW hazzard between instruction in X stage and read port 1
   653 wire raw_m_0;                                   // RAW hazzard between instruction in M stage and read port 0
   654 wire raw_m_1;                                   // RAW hazzard between instruction in M stage and read port 1
   655 wire raw_w_0;                                   // RAW hazzard between instruction in W stage and read port 0
   656 wire raw_w_1;                                   // RAW hazzard between instruction in W stage and read port 1
   658 // Control flow
   659 wire cmp_zero;                                  // Result of comparison is zero
   660 wire cmp_negative;                              // Result of comparison is negative
   661 wire cmp_overflow;                              // Comparison produced an overflow
   662 wire cmp_carry_n;                               // Comparison produced a carry, inverted
   663 reg condition_met_x;                            // Condition of branch instruction is met
   664 reg condition_met_m;
   665 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   666 wire branch_taken_x;                            // Branch is taken in X stage
   667 `endif
   668 wire branch_taken_m;                            // Branch is taken in M stage
   670 wire kill_f;                                    // Kill instruction in F stage
   671 wire kill_d;                                    // Kill instruction in D stage
   672 wire kill_x;                                    // Kill instruction in X stage
   673 wire kill_m;                                    // Kill instruction in M stage
   674 wire kill_w;                                    // Kill instruction in W stage
   676 reg [`LM32_PC_WIDTH+2-1:8] eba;                 // Exception Base Address (EBA) CSR
   677 `ifdef CFG_DEBUG_ENABLED
   678 reg [`LM32_PC_WIDTH+2-1:8] deba;                // Debug Exception Base Address (DEBA) CSR
   679 `endif
   680 reg [`LM32_EID_RNG] eid_x;                      // Exception ID in X stage
   681 `ifdef CFG_TRACE_ENABLED
   682 reg [`LM32_EID_RNG] eid_m;                      // Exception ID in M stage
   683 reg [`LM32_EID_RNG] eid_w;                      // Exception ID in W stage
   684 `endif
   686 `ifdef CFG_DEBUG_ENABLED
   687 `ifdef LM32_SINGLE_STEP_ENABLED
   688 wire dc_ss;                                     // Is single-step enabled
   689 `endif
   690 wire dc_re;                                     // Remap all exceptions
   691 wire exception_x;                               // An exception occured in the X stage
   692 reg exception_m;                                // An instruction that caused an exception is in the M stage
   693 wire debug_exception_x;                         // Indicates if a debug exception has occured
   694 reg debug_exception_m;
   695 reg debug_exception_w;
   696 wire debug_exception_q_w;
   697 wire non_debug_exception_x;                     // Indicates if a non debug exception has occured
   698 reg non_debug_exception_m;
   699 reg non_debug_exception_w;
   700 wire non_debug_exception_q_w;
   701 `else
   702 wire exception_x;                               // Indicates if a debug exception has occured
   703 reg exception_m;
   704 reg exception_w;
   705 wire exception_q_w;
   706 `endif
   708 `ifdef CFG_DEBUG_ENABLED
   709 `ifdef CFG_JTAG_ENABLED
   710 wire reset_exception;                           // Indicates if a reset exception has occured
   711 `endif
   712 `endif
   713 `ifdef CFG_INTERRUPTS_ENABLED
   714 wire interrupt_exception;                       // Indicates if an interrupt exception has occured
   715 `endif
   716 `ifdef CFG_DEBUG_ENABLED
   717 wire breakpoint_exception;                      // Indicates if a breakpoint exception has occured
   718 wire watchpoint_exception;                      // Indicates if a watchpoint exception has occured
   719 `endif
   720 `ifdef CFG_BUS_ERRORS_ENABLED
   721 wire instruction_bus_error_exception;           // Indicates if an instruction bus error exception has occured
   722 wire data_bus_error_exception;                  // Indicates if a data bus error exception has occured
   723 `endif
   724 `ifdef CFG_MC_DIVIDE_ENABLED
   725 wire divide_by_zero_exception;                  // Indicates if a divide by zero exception has occured
   726 `endif
   727 wire system_call_exception;                     // Indicates if a system call exception has occured
   729 `ifdef CFG_BUS_ERRORS_ENABLED
   730 reg data_bus_error_seen;                        // Indicates if a data bus error was seen
   731 `endif
   733 /////////////////////////////////////////////////////
   734 // Functions
   735 /////////////////////////////////////////////////////
   737 `include "lm32_functions.v"
   739 /////////////////////////////////////////////////////
   740 // Instantiations
   741 ///////////////////////////////////////////////////// 
   743 // Instruction unit
   744 lm32_instruction_unit #(
   745     .associativity          (icache_associativity),
   746     .sets                   (icache_sets),
   747     .bytes_per_line         (icache_bytes_per_line),
   748     .base_address           (icache_base_address),
   749     .limit                  (icache_limit)
   750   ) instruction_unit (
   751     // ----- Inputs -------
   752     .clk_i                  (clk_i),
   753     .rst_i                  (rst_i),
   754     // From pipeline
   755     .stall_a                (stall_a),
   756     .stall_f                (stall_f),
   757     .stall_d                (stall_d),
   758     .stall_x                (stall_x),
   759     .stall_m                (stall_m),
   760     .valid_f                (valid_f),
   761     .valid_d                (valid_d),
   762     .kill_f                 (kill_f),
   763     .branch_predict_taken_d (branch_predict_taken_d),
   764     .branch_predict_address_d (branch_predict_address_d),
   765 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
   766     .branch_taken_x         (branch_taken_x),
   767     .branch_target_x        (branch_target_x),
   768 `endif
   769     .exception_m            (exception_m),
   770     .branch_taken_m         (branch_taken_m),
   771     .branch_mispredict_taken_m (branch_mispredict_taken_m),
   772     .branch_target_m        (branch_target_m),
   773 `ifdef CFG_ICACHE_ENABLED
   774     .iflush                 (iflush),
   775 `endif
   776 `ifdef CFG_IROM_ENABLED
   777     .irom_store_data_m      (irom_store_data_m),
   778     .irom_address_xm        (irom_address_xm),
   779     .irom_we_xm             (irom_we_xm),
   780 `endif
   781 `ifdef CFG_DCACHE_ENABLED
   782     .dcache_restart_request (dcache_restart_request),
   783     .dcache_refill_request  (dcache_refill_request),
   784     .dcache_refilling       (dcache_refilling),
   785 `endif        
   786 `ifdef CFG_IWB_ENABLED
   787     // From Wishbone
   788     .i_dat_i                (I_DAT_I),
   789     .i_ack_i                (I_ACK_I),
   790     .i_err_i                (I_ERR_I),
   791 `endif
   792 `ifdef CFG_HW_DEBUG_ENABLED
   793     .jtag_read_enable       (jtag_read_enable),
   794     .jtag_write_enable      (jtag_write_enable),
   795     .jtag_write_data        (jtag_write_data),
   796     .jtag_address           (jtag_address),
   797 `endif
   798     // ----- Outputs -------
   799     // To pipeline
   800     .pc_f                   (pc_f),
   801     .pc_d                   (pc_d),
   802     .pc_x                   (pc_x),
   803     .pc_m                   (pc_m),
   804     .pc_w                   (pc_w),
   805 `ifdef CFG_ICACHE_ENABLED
   806     .icache_stall_request   (icache_stall_request),
   807     .icache_restart_request (icache_restart_request),
   808     .icache_refill_request  (icache_refill_request),
   809     .icache_refilling       (icache_refilling),
   810 `endif
   811 `ifdef CFG_IROM_ENABLED
   812     .irom_data_m            (irom_data_m),
   813 `endif
   814 `ifdef CFG_IWB_ENABLED
   815     // To Wishbone
   816     .i_dat_o                (I_DAT_O),
   817     .i_adr_o                (I_ADR_O),
   818     .i_cyc_o                (I_CYC_O),
   819     .i_sel_o                (I_SEL_O),
   820     .i_stb_o                (I_STB_O),
   821     .i_we_o                 (I_WE_O),
   822     .i_cti_o                (I_CTI_O),
   823     .i_lock_o               (I_LOCK_O),
   824     .i_bte_o                (I_BTE_O),
   825 `endif
   826 `ifdef CFG_HW_DEBUG_ENABLED
   827     .jtag_read_data         (jtag_read_data),
   828     .jtag_access_complete   (jtag_access_complete),
   829 `endif
   830 `ifdef CFG_BUS_ERRORS_ENABLED
   831     .bus_error_d            (bus_error_d),
   832 `endif
   833 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
   834     .instruction_f          (instruction_f),
   835 `endif
   836     .instruction_d          (instruction_d)
   837     );
   839 // Instruction decoder
   840 lm32_decoder decoder (
   841     // ----- Inputs -------
   842     .instruction            (instruction_d),
   843     // ----- Outputs -------
   844     .d_result_sel_0         (d_result_sel_0_d),
   845     .d_result_sel_1         (d_result_sel_1_d),
   846     .x_result_sel_csr       (x_result_sel_csr_d),
   847 `ifdef LM32_MC_ARITHMETIC_ENABLED
   848     .x_result_sel_mc_arith  (x_result_sel_mc_arith_d),
   849 `endif
   850 `ifdef LM32_NO_BARREL_SHIFT    
   851     .x_result_sel_shift     (x_result_sel_shift_d),
   852 `endif
   853 `ifdef CFG_SIGN_EXTEND_ENABLED
   854     .x_result_sel_sext      (x_result_sel_sext_d),
   855 `endif    
   856     .x_result_sel_logic     (x_result_sel_logic_d),
   857 `ifdef CFG_USER_ENABLED
   858     .x_result_sel_user      (x_result_sel_user_d),
   859 `endif
   860     .x_result_sel_add       (x_result_sel_add_d),
   861     .m_result_sel_compare   (m_result_sel_compare_d),
   862 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   863     .m_result_sel_shift     (m_result_sel_shift_d),  
   864 `endif    
   865     .w_result_sel_load      (w_result_sel_load_d),
   866 `ifdef CFG_PL_MULTIPLY_ENABLED
   867     .w_result_sel_mul       (w_result_sel_mul_d),
   868 `endif
   869     .x_bypass_enable        (x_bypass_enable_d),
   870     .m_bypass_enable        (m_bypass_enable_d),
   871     .read_enable_0          (read_enable_0_d),
   872     .read_idx_0             (read_idx_0_d),
   873     .read_enable_1          (read_enable_1_d),
   874     .read_idx_1             (read_idx_1_d),
   875     .write_enable           (write_enable_d),
   876     .write_idx              (write_idx_d),
   877     .immediate              (immediate_d),
   878     .branch_offset          (branch_offset_d),
   879     .load                   (load_d),
   880     .store                  (store_d),
   881     .size                   (size_d),
   882     .sign_extend            (sign_extend_d),
   883     .adder_op               (adder_op_d),
   884     .logic_op               (logic_op_d),
   885 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
   886     .direction              (direction_d),
   887 `endif
   888 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
   889     .shift_left             (shift_left_d),
   890     .shift_right            (shift_right_d),
   891 `endif
   892 `ifdef CFG_MC_MULTIPLY_ENABLED
   893     .multiply               (multiply_d),
   894 `endif
   895 `ifdef CFG_MC_DIVIDE_ENABLED
   896     .divide                 (divide_d),
   897     .modulus                (modulus_d),
   898 `endif
   899     .branch                 (branch_d),
   900     .bi_unconditional       (bi_unconditional),
   901     .bi_conditional         (bi_conditional),
   902     .branch_reg             (branch_reg_d),
   903     .condition              (condition_d),
   904 `ifdef CFG_DEBUG_ENABLED
   905     .break_opcode           (break_d),
   906 `endif
   907     .scall                  (scall_d),
   908     .eret                   (eret_d),
   909 `ifdef CFG_DEBUG_ENABLED
   910     .bret                   (bret_d),
   911 `endif
   912 `ifdef CFG_USER_ENABLED
   913     .user_opcode            (user_opcode_d),
   914 `endif
   915     .csr_write_enable       (csr_write_enable_d)
   916     ); 
   918 // Load/store unit       
   919 lm32_load_store_unit #(
   920     .associativity          (dcache_associativity),
   921     .sets                   (dcache_sets),
   922     .bytes_per_line         (dcache_bytes_per_line),
   923     .base_address           (dcache_base_address),
   924     .limit                  (dcache_limit)
   925   ) load_store_unit (
   926     // ----- Inputs -------
   927     .clk_i                  (clk_i),
   928     .rst_i                  (rst_i),
   929     // From pipeline
   930     .stall_a                (stall_a),
   931     .stall_x                (stall_x),
   932     .stall_m                (stall_m),
   933     .kill_m                 (kill_m),
   934     .exception_m            (exception_m),
   935     .store_operand_x        (store_operand_x),
   936     .load_store_address_x   (adder_result_x),
   937     .load_store_address_m   (operand_m),
   938     .load_store_address_w   (operand_w[1:0]),
   939     .load_x                 (load_x),
   940     .store_x                (store_x),
   941     .load_q_x               (load_q_x),
   942     .store_q_x              (store_q_x),
   943     .load_q_m               (load_q_m),
   944     .store_q_m              (store_q_m),
   945     .sign_extend_x          (sign_extend_x),
   946     .size_x                 (size_x),
   947 `ifdef CFG_DCACHE_ENABLED
   948     .dflush                 (dflush_m),
   949 `endif
   950 `ifdef CFG_IROM_ENABLED
   951     .irom_data_m            (irom_data_m),
   952 `endif
   953     // From Wishbone
   954     .d_dat_i                (D_DAT_I),
   955     .d_ack_i                (D_ACK_I),
   956     .d_err_i                (D_ERR_I),
   957     // ----- Outputs -------
   958     // To pipeline
   959 `ifdef CFG_DCACHE_ENABLED
   960     .dcache_refill_request  (dcache_refill_request),
   961     .dcache_restart_request (dcache_restart_request),
   962     .dcache_stall_request   (dcache_stall_request),
   963     .dcache_refilling       (dcache_refilling),
   964 `endif    
   965 `ifdef CFG_IROM_ENABLED
   966     .irom_store_data_m      (irom_store_data_m),
   967     .irom_address_xm        (irom_address_xm),
   968     .irom_we_xm             (irom_we_xm),
   969     .irom_stall_request_x   (irom_stall_request_x),
   970 `endif
   971     .load_data_w            (load_data_w),
   972     .stall_wb_load          (stall_wb_load),
   973     // To Wishbone
   974     .d_dat_o                (D_DAT_O),
   975     .d_adr_o                (D_ADR_O),
   976     .d_cyc_o                (D_CYC_O),
   977     .d_sel_o                (D_SEL_O),
   978     .d_stb_o                (D_STB_O),
   979     .d_we_o                 (D_WE_O),
   980     .d_cti_o                (D_CTI_O),
   981     .d_lock_o               (D_LOCK_O),
   982     .d_bte_o                (D_BTE_O)
   983     );      
   985 // Adder       
   986 lm32_adder adder (
   987     // ----- Inputs -------
   988     .adder_op_x             (adder_op_x),
   989     .adder_op_x_n           (adder_op_x_n),
   990     .operand_0_x            (operand_0_x),
   991     .operand_1_x            (operand_1_x),
   992     // ----- Outputs -------
   993     .adder_result_x         (adder_result_x),
   994     .adder_carry_n_x        (adder_carry_n_x),
   995     .adder_overflow_x       (adder_overflow_x)
   996     );
   998 // Logic operations
   999 lm32_logic_op logic_op (
  1000     // ----- Inputs -------
  1001     .logic_op_x             (logic_op_x),
  1002     .operand_0_x            (operand_0_x),
  1004     .operand_1_x            (operand_1_x),
  1005     // ----- Outputs -------
  1006     .logic_result_x         (logic_result_x)
  1007     );
  1009 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1010 // Pipelined barrel-shifter
  1011 lm32_shifter shifter (
  1012     // ----- Inputs -------
  1013     .clk_i                  (clk_i),
  1014     .rst_i                  (rst_i),
  1015     .stall_x                (stall_x),
  1016     .direction_x            (direction_x),
  1017     .sign_extend_x          (sign_extend_x),
  1018     .operand_0_x            (operand_0_x),
  1019     .operand_1_x            (operand_1_x),
  1020     // ----- Outputs -------
  1021     .shifter_result_m       (shifter_result_m)
  1022     );
  1023 `endif
  1025 `ifdef CFG_PL_MULTIPLY_ENABLED
  1026 // Pipeline fixed-point multiplier
  1027 lm32_multiplier multiplier (
  1028     // ----- Inputs -------
  1029     .clk_i                  (clk_i),
  1030     .rst_i                  (rst_i),
  1031     .stall_x                (stall_x),
  1032     .stall_m                (stall_m),
  1033     .operand_0              (d_result_0),
  1034     .operand_1              (d_result_1),
  1035     // ----- Outputs -------
  1036     .result                 (multiplier_result_w)    
  1037     );
  1038 `endif
  1040 `ifdef LM32_MC_ARITHMETIC_ENABLED
  1041 // Multi-cycle arithmetic
  1042 lm32_mc_arithmetic mc_arithmetic (
  1043     // ----- Inputs -------
  1044     .clk_i                  (clk_i),
  1045     .rst_i                  (rst_i),
  1046     .stall_d                (stall_d),
  1047     .kill_x                 (kill_x),
  1048 `ifdef CFG_MC_DIVIDE_ENABLED                  
  1049     .divide_d               (divide_q_d),
  1050     .modulus_d              (modulus_q_d),
  1051 `endif
  1052 `ifdef CFG_MC_MULTIPLY_ENABLED        
  1053     .multiply_d             (multiply_q_d),
  1054 `endif
  1055 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
  1056     .shift_left_d           (shift_left_q_d),
  1057     .shift_right_d          (shift_right_q_d),
  1058     .sign_extend_d          (sign_extend_d),
  1059 `endif    
  1060     .operand_0_d            (d_result_0),
  1061     .operand_1_d            (d_result_1),
  1062     // ----- Outputs -------
  1063     .result_x               (mc_result_x),
  1064 `ifdef CFG_MC_DIVIDE_ENABLED                  
  1065     .divide_by_zero_x       (divide_by_zero_x),
  1066 `endif
  1067     .stall_request_x        (mc_stall_request_x)
  1068     );
  1069 `endif
  1071 `ifdef CFG_INTERRUPTS_ENABLED
  1072 // Interrupt unit
  1073 lm32_interrupt interrupt_unit (
  1074     // ----- Inputs -------
  1075     .clk_i                  (clk_i),
  1076     .rst_i                  (rst_i),
  1077     // From external devices
  1078     .interrupt              (interrupt),
  1079     // From pipeline
  1080     .stall_x                (stall_x),
  1081 `ifdef CFG_DEBUG_ENABLED
  1082     .non_debug_exception    (non_debug_exception_q_w),
  1083     .debug_exception        (debug_exception_q_w),
  1084 `else
  1085     .exception              (exception_q_w),
  1086 `endif
  1087     .eret_q_x               (eret_q_x),
  1088 `ifdef CFG_DEBUG_ENABLED
  1089     .bret_q_x               (bret_q_x),
  1090 `endif
  1091     .csr                    (csr_x),
  1092     .csr_write_data         (operand_1_x),
  1093     .csr_write_enable       (csr_write_enable_q_x),
  1094     // ----- Outputs -------
  1095     .interrupt_exception    (interrupt_exception),
  1096     // To pipeline
  1097     .csr_read_data          (interrupt_csr_read_data_x)
  1098     );
  1099 `endif
  1101 `ifdef CFG_JTAG_ENABLED
  1102 // JTAG interface
  1103 lm32_jtag jtag (
  1104     // ----- Inputs -------
  1105     .clk_i                  (clk_i),
  1106     .rst_i                  (rst_i),
  1107     // From JTAG
  1108     .jtag_clk               (jtag_clk),
  1109     .jtag_update            (jtag_update),
  1110     .jtag_reg_q             (jtag_reg_q),
  1111     .jtag_reg_addr_q        (jtag_reg_addr_q),
  1112     // From pipeline
  1113 `ifdef CFG_JTAG_UART_ENABLED
  1114     .csr                    (csr_x),
  1115     .csr_write_data         (operand_1_x),
  1116     .csr_write_enable       (csr_write_enable_q_x),
  1117     .stall_x                (stall_x),
  1118 `endif
  1119 `ifdef CFG_HW_DEBUG_ENABLED
  1120     .jtag_read_data         (jtag_read_data),
  1121     .jtag_access_complete   (jtag_access_complete),
  1122 `endif
  1123 `ifdef CFG_DEBUG_ENABLED
  1124     .exception_q_w          (debug_exception_q_w || non_debug_exception_q_w),
  1125 `endif    
  1126     // ----- Outputs -------
  1127     // To pipeline
  1128 `ifdef CFG_JTAG_UART_ENABLED
  1129     .jtx_csr_read_data      (jtx_csr_read_data),
  1130     .jrx_csr_read_data      (jrx_csr_read_data),
  1131 `endif
  1132 `ifdef CFG_HW_DEBUG_ENABLED
  1133     .jtag_csr_write_enable  (jtag_csr_write_enable),
  1134     .jtag_csr_write_data    (jtag_csr_write_data),
  1135     .jtag_csr               (jtag_csr),
  1136     .jtag_read_enable       (jtag_read_enable),
  1137     .jtag_write_enable      (jtag_write_enable),
  1138     .jtag_write_data        (jtag_write_data),
  1139     .jtag_address           (jtag_address),
  1140 `endif
  1141 `ifdef CFG_DEBUG_ENABLED
  1142     .jtag_break             (jtag_break),
  1143     .jtag_reset             (reset_exception),
  1144 `endif
  1145     // To JTAG 
  1146     .jtag_reg_d             (jtag_reg_d),
  1147     .jtag_reg_addr_d        (jtag_reg_addr_d)
  1148     );
  1149 `endif
  1151 `ifdef CFG_DEBUG_ENABLED
  1152 // Debug unit
  1153 lm32_debug #(
  1154     .breakpoints            (breakpoints),
  1155     .watchpoints            (watchpoints)
  1156   ) hw_debug (
  1157     // ----- Inputs -------
  1158     .clk_i                  (clk_i), 
  1159     .rst_i                  (rst_i),
  1160     .pc_x                   (pc_x),
  1161     .load_x                 (load_x),
  1162     .store_x                (store_x),
  1163     .load_store_address_x   (adder_result_x),
  1164     .csr_write_enable_x     (csr_write_enable_q_x),
  1165     .csr_write_data         (operand_1_x),
  1166     .csr_x                  (csr_x),
  1167 `ifdef CFG_HW_DEBUG_ENABLED
  1168     .jtag_csr_write_enable  (jtag_csr_write_enable),
  1169     .jtag_csr_write_data    (jtag_csr_write_data),
  1170     .jtag_csr               (jtag_csr),
  1171 `endif
  1172 `ifdef LM32_SINGLE_STEP_ENABLED
  1173     .eret_q_x               (eret_q_x),
  1174     .bret_q_x               (bret_q_x),
  1175     .stall_x                (stall_x),
  1176     .exception_x            (exception_x),
  1177     .q_x                    (q_x),
  1178 `ifdef CFG_DCACHE_ENABLED
  1179     .dcache_refill_request  (dcache_refill_request),
  1180 `endif
  1181 `endif
  1182     // ----- Outputs -------
  1183 `ifdef LM32_SINGLE_STEP_ENABLED
  1184     .dc_ss                  (dc_ss),
  1185 `endif
  1186     .dc_re                  (dc_re),
  1187     .bp_match               (bp_match),
  1188     .wp_match               (wp_match)
  1189     );
  1190 `endif
  1192 // Register file
  1194 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  1195    /*----------------------------------------------------------------------
  1196     Register File is implemented using EBRs. There can be three accesses to
  1197     the register file in each cycle: two reads and one write. On-chip block
  1198     RAM has two read/write ports. To accomodate three accesses, two on-chip
  1199     block RAMs are used (each register file "write" is made to both block
  1200     RAMs).
  1202     One limitation of the on-chip block RAMs is that one cannot perform a 
  1203     read and write to same location in a cycle (if this is done, then the
  1204     data read out is indeterminate).
  1205     ----------------------------------------------------------------------*/
  1206    wire [31:0] regfile_data_0, regfile_data_1;
  1207    reg [31:0]  w_result_d;
  1208    reg 	       regfile_raw_0, regfile_raw_0_nxt;
  1209    reg 	       regfile_raw_1, regfile_raw_1_nxt;
  1211    /*----------------------------------------------------------------------
  1212     Check if read and write is being performed to same register in current 
  1213     cycle? This is done by comparing the read and write IDXs.
  1214     ----------------------------------------------------------------------*/
  1215    always @(reg_write_enable_q_w or write_idx_w or instruction_f)
  1216      begin
  1217 	if (reg_write_enable_q_w
  1218 	    && (write_idx_w == instruction_f[25:21]))
  1219 	  regfile_raw_0_nxt = 1'b1;
  1220 	else
  1221 	  regfile_raw_0_nxt = 1'b0;
  1223 	if (reg_write_enable_q_w
  1224 	    && (write_idx_w == instruction_f[20:16]))
  1225 	  regfile_raw_1_nxt = 1'b1;
  1226 	else
  1227 	  regfile_raw_1_nxt = 1'b0;
  1228      end
  1230    /*----------------------------------------------------------------------
  1231     Select latched (delayed) write value or data from register file. If 
  1232     read in previous cycle was performed to register written to in same
  1233     cycle, then latched (delayed) write value is selected.
  1234     ----------------------------------------------------------------------*/
  1235    always @(regfile_raw_0 or w_result_d or regfile_data_0)
  1236      if (regfile_raw_0)
  1237        reg_data_live_0 = w_result_d;
  1238      else
  1239        reg_data_live_0 = regfile_data_0;
  1241    /*----------------------------------------------------------------------
  1242     Select latched (delayed) write value or data from register file. If 
  1243     read in previous cycle was performed to register written to in same
  1244     cycle, then latched (delayed) write value is selected.
  1245     ----------------------------------------------------------------------*/
  1246    always @(regfile_raw_1 or w_result_d or regfile_data_1)
  1247      if (regfile_raw_1)
  1248        reg_data_live_1 = w_result_d;
  1249      else
  1250        reg_data_live_1 = regfile_data_1;
  1252    /*----------------------------------------------------------------------
  1253     Latch value written to register file
  1254     ----------------------------------------------------------------------*/
  1255    always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  1256      if (rst_i == `TRUE)
  1257        begin
  1258 	  regfile_raw_0 <= 1'b0;
  1259 	  regfile_raw_1 <= 1'b0;
  1260 	  w_result_d <= 32'b0;
  1261        end
  1262      else
  1263        begin
  1264 	  regfile_raw_0 <= regfile_raw_0_nxt;
  1265 	  regfile_raw_1 <= regfile_raw_1_nxt;
  1266 	  w_result_d <= w_result;
  1267        end
  1269    /*----------------------------------------------------------------------
  1270     Register file instantiation as Pseudo-Dual Port EBRs.
  1271     ----------------------------------------------------------------------*/
  1272    // Modified by GSI: removed non-portable RAM instantiation
  1273    lm32_dp_ram
  1274      #(
  1275        // ----- Parameters -----
  1276        .addr_depth(1<<5),
  1277        .addr_width(5),
  1278        .data_width(32)
  1280    reg_0
  1282       // ----- Inputs -----
  1283       .clk_i	(clk_i),
  1284       .rst_i	(rst_i), 
  1285       .we_i	(reg_write_enable_q_w),
  1286       .wdata_i	(w_result),
  1287       .waddr_i	(write_idx_w),
  1288       .raddr_i	(instruction_f[25:21]),
  1289       // ----- Outputs -----
  1290       .rdata_o	(regfile_data_0)
  1291       );
  1293    lm32_dp_ram
  1294      #(
  1295        .addr_depth(1<<5),
  1296        .addr_width(5),
  1297        .data_width(32)
  1299    reg_1
  1301       // ----- Inputs -----
  1302       .clk_i	(clk_i),
  1303       .rst_i	(rst_i), 
  1304       .we_i	(reg_write_enable_q_w),
  1305       .wdata_i	(w_result),
  1306       .waddr_i	(write_idx_w),
  1307       .raddr_i	(instruction_f[20:16]),
  1308       // ----- Outputs -----
  1309       .rdata_o	(regfile_data_1)
  1310       );
  1311 `endif
  1313 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
  1314    pmi_ram_dp
  1315      #(
  1316        // ----- Parameters -----
  1317        .pmi_wr_addr_depth(1<<5),
  1318        .pmi_wr_addr_width(5),
  1319        .pmi_wr_data_width(32),
  1320        .pmi_rd_addr_depth(1<<5),
  1321        .pmi_rd_addr_width(5),
  1322        .pmi_rd_data_width(32),
  1323        .pmi_regmode("noreg"),
  1324        .pmi_gsr("enable"),
  1325        .pmi_resetmode("sync"),
  1326        .pmi_init_file("none"),
  1327        .pmi_init_file_format("binary"),
  1328        .pmi_family(`LATTICE_FAMILY),
  1329        .module_type("pmi_ram_dp")
  1331    reg_0
  1333       // ----- Inputs -----
  1334       .Data(w_result),
  1335       .WrAddress(write_idx_w),
  1336       .RdAddress(read_idx_0_d),
  1337       .WrClock(clk_i),
  1338       .RdClock(clk_n_i),
  1339       .WrClockEn(`TRUE),
  1340       .RdClockEn(stall_f == `FALSE),
  1341       .WE(reg_write_enable_q_w),
  1342       .Reset(rst_i), 
  1343       // ----- Outputs -----
  1344       .Q(reg_data_0)
  1345       );
  1347    pmi_ram_dp
  1348      #(
  1349        // ----- Parameters -----
  1350        .pmi_wr_addr_depth(1<<5),
  1351        .pmi_wr_addr_width(5),
  1352        .pmi_wr_data_width(32),
  1353        .pmi_rd_addr_depth(1<<5),
  1354        .pmi_rd_addr_width(5),
  1355        .pmi_rd_data_width(32),
  1356        .pmi_regmode("noreg"),
  1357        .pmi_gsr("enable"),
  1358        .pmi_resetmode("sync"),
  1359        .pmi_init_file("none"),
  1360        .pmi_init_file_format("binary"),
  1361        .pmi_family(`LATTICE_FAMILY),
  1362        .module_type("pmi_ram_dp")
  1364    reg_1
  1366       // ----- Inputs -----
  1367       .Data(w_result),
  1368       .WrAddress(write_idx_w),
  1369       .RdAddress(read_idx_1_d),
  1370       .WrClock(clk_i),
  1371       .RdClock(clk_n_i),
  1372       .WrClockEn(`TRUE),
  1373       .RdClockEn(stall_f == `FALSE),
  1374       .WE(reg_write_enable_q_w),
  1375       .Reset(rst_i), 
  1376       // ----- Outputs -----
  1377       .Q(reg_data_1)
  1378       );
  1379 `endif
  1382 /////////////////////////////////////////////////////
  1383 // Combinational Logic
  1384 /////////////////////////////////////////////////////
  1386 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  1387 // Select between buffered and live data from register file
  1388 assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
  1389 assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
  1390 `endif
  1391 `ifdef LM32_EBR_REGISTER_FILE
  1392 `else
  1393 // Register file read ports
  1394 assign reg_data_0 = registers[read_idx_0_d];
  1395 assign reg_data_1 = registers[read_idx_1_d];
  1396 `endif
  1398 // Detect read-after-write hazzards
  1399 assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
  1400 assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
  1401 assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
  1402 assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
  1403 assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
  1404 assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
  1406 // Interlock detection - Raise an interlock for RAW hazzards 
  1407 always @(*)
  1408 begin
  1409     if (   (   (x_bypass_enable_x == `FALSE)
  1410             && (   ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
  1411                 || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
  1414         || (   (m_bypass_enable_m == `FALSE)
  1415             && (   ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
  1416                 || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
  1420         interlock = `TRUE;
  1421     else
  1422         interlock = `FALSE;
  1423 end
  1425 // Bypass for reg port 0
  1426 always @(*)
  1427 begin
  1428     if (raw_x_0 == `TRUE)        
  1429         bypass_data_0 = x_result;
  1430     else if (raw_m_0 == `TRUE)
  1431         bypass_data_0 = m_result;
  1432     else if (raw_w_0 == `TRUE)
  1433         bypass_data_0 = w_result;
  1434     else
  1435         bypass_data_0 = reg_data_0;
  1436 end
  1438 // Bypass for reg port 1
  1439 always @(*)
  1440 begin
  1441     if (raw_x_1 == `TRUE)
  1442         bypass_data_1 = x_result;
  1443     else if (raw_m_1 == `TRUE)
  1444         bypass_data_1 = m_result;
  1445     else if (raw_w_1 == `TRUE)
  1446         bypass_data_1 = w_result;
  1447     else
  1448         bypass_data_1 = reg_data_1;
  1449 end
  1451    /*----------------------------------------------------------------------
  1452     Branch prediction is performed in D stage of pipeline. Only PC-relative
  1453     branches are predicted: forward-pointing conditional branches are not-
  1454     taken, while backward-pointing conditional branches are taken. 
  1455     Unconditional branches are always predicted taken!
  1456     ----------------------------------------------------------------------*/
  1457    assign branch_predict_d = bi_unconditional | bi_conditional;
  1458    assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
  1460    // Compute branch target address: Branch PC PLUS Offset
  1461    assign branch_target_d = pc_d + branch_offset_d;
  1463    // Compute fetch address. Address of instruction sequentially after the
  1464    // branch if branch is not taken. Target address of branch is branch is
  1465    // taken
  1466    assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
  1468 // D stage result selection
  1469 always @(*)
  1470 begin
  1471     d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0; 
  1472     case (d_result_sel_1_d)
  1473     `LM32_D_RESULT_SEL_1_ZERO:      d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
  1474     `LM32_D_RESULT_SEL_1_REG_1:     d_result_1 = bypass_data_1;
  1475     `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
  1476     default:                        d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
  1477     endcase
  1478 end
  1480 `ifdef CFG_USER_ENABLED    
  1481 // Operands for user-defined instructions
  1482 assign user_operand_0 = operand_0_x;
  1483 assign user_operand_1 = operand_1_x;
  1484 `endif
  1486 `ifdef CFG_SIGN_EXTEND_ENABLED
  1487 // Sign-extension
  1488 assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
  1489 assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
  1490 assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
  1491 `endif
  1493 `ifdef LM32_NO_BARREL_SHIFT
  1494 // Only single bit shift operations are supported when barrel-shifter isn't implemented
  1495 assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
  1496 `endif
  1498 // Condition evaluation
  1499 assign cmp_zero = operand_0_x == operand_1_x;
  1500 assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
  1501 assign cmp_overflow = adder_overflow_x;
  1502 assign cmp_carry_n = adder_carry_n_x;
  1503 always @(*)
  1504 begin
  1505     case (condition_x)
  1506     `LM32_CONDITION_U1:   condition_met_x = `TRUE;
  1507     `LM32_CONDITION_U2:   condition_met_x = `TRUE;
  1508     `LM32_CONDITION_E:    condition_met_x = cmp_zero;
  1509     `LM32_CONDITION_NE:   condition_met_x = !cmp_zero;
  1510     `LM32_CONDITION_G:    condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
  1511     `LM32_CONDITION_GU:   condition_met_x = cmp_carry_n && !cmp_zero;
  1512     `LM32_CONDITION_GE:   condition_met_x = cmp_negative == cmp_overflow;
  1513     `LM32_CONDITION_GEU:  condition_met_x = cmp_carry_n;
  1514     default:              condition_met_x = 1'bx;
  1515     endcase 
  1516 end
  1518 // X stage result selection
  1519 always @(*)
  1520 begin
  1521     x_result =   x_result_sel_add_x ? adder_result_x 
  1522                : x_result_sel_csr_x ? csr_read_data_x
  1523 `ifdef CFG_SIGN_EXTEND_ENABLED
  1524                : x_result_sel_sext_x ? sext_result_x
  1525 `endif
  1526 `ifdef CFG_USER_ENABLED
  1527                : x_result_sel_user_x ? user_result
  1528 `endif
  1529 `ifdef LM32_NO_BARREL_SHIFT
  1530                : x_result_sel_shift_x ? shifter_result_x
  1531 `endif
  1532 `ifdef LM32_MC_ARITHMETIC_ENABLED
  1533                : x_result_sel_mc_arith_x ? mc_result_x
  1534 `endif
  1535                : logic_result_x;
  1536 end
  1538 // M stage result selection
  1539 always @(*)
  1540 begin
  1541     m_result =   m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
  1542 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  1543                : m_result_sel_shift_m ? shifter_result_m
  1544 `endif
  1545                : operand_m; 
  1546 end
  1548 // W stage result selection
  1549 always @(*)
  1550 begin
  1551     w_result =    w_result_sel_load_w ? load_data_w
  1552 `ifdef CFG_PL_MULTIPLY_ENABLED
  1553                 : w_result_sel_mul_w ? multiplier_result_w
  1554 `endif
  1555                 : operand_w;
  1556 end
  1558 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  1559 // Indicate when a branch should be taken in X stage
  1560 assign branch_taken_x =      (stall_x == `FALSE)
  1561                           && (   (branch_x == `TRUE)
  1562                               && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
  1563                               && (valid_x == `TRUE)
  1564                               && (branch_predict_x == `FALSE)
  1565                              ); 
  1566 `endif
  1568 // Indicate when a branch should be taken in M stage (exceptions are a type of branch)
  1569 assign branch_taken_m =      (stall_m == `FALSE) 
  1570                           && (   (   (branch_m == `TRUE) 
  1571                                   && (valid_m == `TRUE)
  1572                                   && (   (   (condition_met_m == `TRUE)
  1573 					  && (branch_predict_taken_m == `FALSE)
  1575 				      || (   (condition_met_m == `FALSE)
  1576 					  && (branch_predict_m == `TRUE)
  1577 					  && (branch_predict_taken_m == `TRUE)
  1581                               || (exception_m == `TRUE)
  1582                              );
  1584 // Indicate when a branch in M stage is mispredicted as being taken
  1585 assign branch_mispredict_taken_m =    (condition_met_m == `FALSE)
  1586                                    && (branch_predict_m == `TRUE)
  1587 	   			   && (branch_predict_taken_m == `TRUE);
  1589 // Indicate when a branch in M stage will cause flush in X stage
  1590 assign branch_flushX_m =    (stall_m == `FALSE)
  1591                          && (   (   (branch_m == `TRUE) 
  1592                                  && (valid_m == `TRUE)
  1593 			         && (   (condition_met_m == `TRUE)
  1594 				     || (   (condition_met_m == `FALSE)
  1595 					 && (branch_predict_m == `TRUE)
  1596 					 && (branch_predict_taken_m == `TRUE)
  1600 			     || (exception_m == `TRUE)
  1601 			    );
  1603 // Generate signal that will kill instructions in each pipeline stage when necessary
  1604 assign kill_f =    (   (valid_d == `TRUE)
  1605                     && (branch_predict_taken_d == `TRUE)
  1607                 || (branch_taken_m == `TRUE) 
  1608 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  1609                 || (branch_taken_x == `TRUE)
  1610 `endif
  1611 `ifdef CFG_ICACHE_ENABLED
  1612                 || (icache_refill_request == `TRUE) 
  1613 `endif
  1614 `ifdef CFG_DCACHE_ENABLED                
  1615                 || (dcache_refill_request == `TRUE)
  1616 `endif
  1618 assign kill_d =    (branch_taken_m == `TRUE) 
  1619 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  1620                 || (branch_taken_x == `TRUE)
  1621 `endif
  1622 `ifdef CFG_ICACHE_ENABLED
  1623                 || (icache_refill_request == `TRUE)     
  1624 `endif                
  1625 `ifdef CFG_DCACHE_ENABLED                
  1626                 || (dcache_refill_request == `TRUE)
  1627 `endif
  1629 assign kill_x =    (branch_flushX_m == `TRUE) 
  1630 `ifdef CFG_DCACHE_ENABLED                
  1631                 || (dcache_refill_request == `TRUE)
  1632 `endif
  1634 assign kill_m =    `FALSE
  1635 `ifdef CFG_DCACHE_ENABLED                
  1636                 || (dcache_refill_request == `TRUE)
  1637 `endif
  1639 assign kill_w =    `FALSE
  1640 `ifdef CFG_DCACHE_ENABLED                
  1641                 || (dcache_refill_request == `TRUE)
  1642 `endif                
  1645 // Exceptions
  1647 `ifdef CFG_DEBUG_ENABLED
  1648 assign breakpoint_exception =    (   (   (break_x == `TRUE)
  1649 				      || (bp_match == `TRUE)
  1651 				  && (valid_x == `TRUE)
  1653 `ifdef CFG_JTAG_ENABLED
  1654                               || (jtag_break == `TRUE)
  1655 `endif
  1657 `endif
  1659 `ifdef CFG_DEBUG_ENABLED
  1660 assign watchpoint_exception = wp_match == `TRUE;
  1661 `endif
  1663 `ifdef CFG_BUS_ERRORS_ENABLED
  1664 assign instruction_bus_error_exception = (   (bus_error_x == `TRUE)
  1665                                           && (valid_x == `TRUE)
  1666                                          );
  1667 assign data_bus_error_exception = data_bus_error_seen == `TRUE;
  1668 `endif
  1670 `ifdef CFG_MC_DIVIDE_ENABLED
  1671 assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
  1672 `endif
  1674 assign system_call_exception = (   (scall_x == `TRUE)
  1675 `ifdef CFG_BUS_ERRORS_ENABLED
  1676                                 && (valid_x == `TRUE)
  1677 `endif
  1678 			       );
  1680 `ifdef CFG_DEBUG_ENABLED
  1681 assign debug_exception_x =  (breakpoint_exception == `TRUE)
  1682                          || (watchpoint_exception == `TRUE)
  1685 assign non_debug_exception_x = (system_call_exception == `TRUE)
  1686 `ifdef CFG_JTAG_ENABLED
  1687                             || (reset_exception == `TRUE)
  1688 `endif
  1689 `ifdef CFG_BUS_ERRORS_ENABLED
  1690                             || (instruction_bus_error_exception == `TRUE)
  1691                             || (data_bus_error_exception == `TRUE)
  1692 `endif
  1693 `ifdef CFG_MC_DIVIDE_ENABLED
  1694                             || (divide_by_zero_exception == `TRUE)
  1695 `endif
  1696 `ifdef CFG_INTERRUPTS_ENABLED
  1697                             || (   (interrupt_exception == `TRUE)
  1698 `ifdef LM32_SINGLE_STEP_ENABLED
  1699                                 && (dc_ss == `FALSE)
  1700 `endif                            
  1701 `ifdef CFG_BUS_ERRORS_ENABLED
  1702  				&& (store_q_m == `FALSE)
  1703 				&& (D_CYC_O == `FALSE)
  1704 `endif
  1706 `endif
  1709 assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
  1710 `else
  1711 assign exception_x =           (system_call_exception == `TRUE)
  1712 `ifdef CFG_BUS_ERRORS_ENABLED
  1713                             || (instruction_bus_error_exception == `TRUE)
  1714                             || (data_bus_error_exception == `TRUE)
  1715 `endif
  1716 `ifdef CFG_MC_DIVIDE_ENABLED
  1717                             || (divide_by_zero_exception == `TRUE)
  1718 `endif
  1719 `ifdef CFG_INTERRUPTS_ENABLED
  1720                             || (   (interrupt_exception == `TRUE)
  1721 `ifdef LM32_SINGLE_STEP_ENABLED
  1722                                 && (dc_ss == `FALSE)
  1723 `endif                            
  1724 `ifdef CFG_BUS_ERRORS_ENABLED
  1725  				&& (store_q_m == `FALSE)
  1726 				&& (D_CYC_O == `FALSE)
  1727 `endif
  1729 `endif
  1731 `endif
  1733 // Exception ID
  1734 always @(*)
  1735 begin
  1736 `ifdef CFG_DEBUG_ENABLED
  1737 `ifdef CFG_JTAG_ENABLED
  1738     if (reset_exception == `TRUE)
  1739         eid_x = `LM32_EID_RESET;
  1740     else
  1741 `endif     
  1742 `ifdef CFG_BUS_ERRORS_ENABLED
  1743          if (data_bus_error_exception == `TRUE)
  1744         eid_x = `LM32_EID_DATA_BUS_ERROR;
  1745     else
  1746 `endif
  1747          if (breakpoint_exception == `TRUE)
  1748         eid_x = `LM32_EID_BREAKPOINT;
  1749     else
  1750 `endif
  1751 `ifdef CFG_BUS_ERRORS_ENABLED
  1752          if (data_bus_error_exception == `TRUE)
  1753         eid_x = `LM32_EID_DATA_BUS_ERROR;
  1754     else
  1755          if (instruction_bus_error_exception == `TRUE)
  1756         eid_x = `LM32_EID_INST_BUS_ERROR;
  1757     else
  1758 `endif
  1759 `ifdef CFG_DEBUG_ENABLED
  1760          if (watchpoint_exception == `TRUE)
  1761         eid_x = `LM32_EID_WATCHPOINT;
  1762     else 
  1763 `endif
  1764 `ifdef CFG_MC_DIVIDE_ENABLED
  1765          if (divide_by_zero_exception == `TRUE)
  1766         eid_x = `LM32_EID_DIVIDE_BY_ZERO;
  1767     else
  1768 `endif
  1769 `ifdef CFG_INTERRUPTS_ENABLED
  1770          if (   (interrupt_exception == `TRUE)
  1771 `ifdef LM32_SINGLE_STEP_ENABLED
  1772              && (dc_ss == `FALSE)
  1773 `endif                            
  1775         eid_x = `LM32_EID_INTERRUPT;
  1776     else
  1777 `endif
  1778         eid_x = `LM32_EID_SCALL;
  1779 end
  1781 // Stall generation
  1783 assign stall_a = (stall_f == `TRUE);
  1785 assign stall_f = (stall_d == `TRUE);
  1787 assign stall_d =   (stall_x == `TRUE) 
  1788                 || (   (interlock == `TRUE)
  1789                     && (kill_d == `FALSE)
  1791 		|| (   (   (eret_d == `TRUE)
  1792 			|| (scall_d == `TRUE)
  1793 `ifdef CFG_BUS_ERRORS_ENABLED
  1794 			|| (bus_error_d == `TRUE)
  1795 `endif
  1797 		    && (   (load_q_x == `TRUE)
  1798 			|| (load_q_m == `TRUE)
  1799 			|| (store_q_x == `TRUE)
  1800 			|| (store_q_m == `TRUE)
  1801 			|| (D_CYC_O == `TRUE)
  1803                     && (kill_d == `FALSE)
  1805 `ifdef CFG_DEBUG_ENABLED
  1806 		|| (   (   (break_d == `TRUE)
  1807 			|| (bret_d == `TRUE)
  1809 		    && (   (load_q_x == `TRUE)
  1810 			|| (store_q_x == `TRUE)
  1811 			|| (load_q_m == `TRUE)
  1812 			|| (store_q_m == `TRUE)
  1813 			|| (D_CYC_O == `TRUE)
  1815                     && (kill_d == `FALSE)
  1817 `endif                   
  1818                 || (   (csr_write_enable_d == `TRUE)
  1819                     && (load_q_x == `TRUE)
  1823 assign stall_x =    (stall_m == `TRUE)
  1824 `ifdef LM32_MC_ARITHMETIC_ENABLED
  1825                  || (   (mc_stall_request_x == `TRUE)
  1826                      && (kill_x == `FALSE)
  1828 `endif
  1829 `ifdef CFG_IROM_ENABLED
  1830                  // Stall load/store instruction in D stage if there is an ongoing store
  1831                  // operation to instruction ROM in M stage
  1832                  || (   (irom_stall_request_x == `TRUE)
  1833 		     && (   (load_d == `TRUE)
  1834 			 || (store_d == `TRUE)
  1837 `endif
  1840 assign stall_m =    (stall_wb_load == `TRUE)
  1841 `ifdef CFG_SIZE_OVER_SPEED
  1842                  || (D_CYC_O == `TRUE)
  1843 `else
  1844                  || (   (D_CYC_O == `TRUE)
  1845                      && (   (store_m == `TRUE)
  1846 		         /*
  1847 			  Bug: Following loop does not allow interrupts to be services since
  1848 			  either D_CYC_O or store_m is always high during entire duration of
  1849 			  loop.
  1850 		          L1:	addi	r1, r1, 1
  1851 			  	sw	(r2,0), r1
  1852 			  	bi	L1
  1854 			  Introduce a single-cycle stall when a wishbone cycle is in progress
  1855 			  and a new store instruction is in Execute stage and a interrupt
  1856 			  exception has occured. This stall will ensure that D_CYC_O and 
  1857 			  store_m will both be low for one cycle.
  1858 			  */
  1859 `ifdef CFG_INTERRUPTS_ENABLED
  1860 		         || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
  1861 `endif
  1862                          || (load_m == `TRUE)
  1863                          || (load_x == `TRUE)
  1866 `endif                 
  1867 `ifdef CFG_DCACHE_ENABLED
  1868                  || (dcache_stall_request == `TRUE)     // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
  1869 `endif                                    
  1870 `ifdef CFG_ICACHE_ENABLED
  1871                  || (icache_stall_request == `TRUE)     // Pipeline needs to be stalled otherwise branches may be lost
  1872                  || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE))) 
  1873 `else
  1874 `ifdef CFG_IWB_ENABLED
  1875                  || (I_CYC_O == `TRUE)            
  1876 `endif
  1877 `endif                               
  1878 `ifdef CFG_USER_ENABLED
  1879                  || (   (user_valid == `TRUE)           // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
  1880                      && (user_complete == `FALSE)
  1882 `endif
  1885 // Qualify state changing control signals
  1886 `ifdef LM32_MC_ARITHMETIC_ENABLED
  1887 assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
  1888 `endif
  1889 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
  1890 assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
  1891 assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
  1892 `endif
  1893 `ifdef CFG_MC_MULTIPLY_ENABLED
  1894 assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
  1895 `endif
  1896 `ifdef CFG_MC_DIVIDE_ENABLED
  1897 assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
  1898 assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
  1899 `endif
  1900 assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
  1901 assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
  1902 assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
  1903 `ifdef CFG_DEBUG_ENABLED
  1904 assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
  1905 `endif
  1906 assign load_q_x = (load_x == `TRUE) 
  1907                && (q_x == `TRUE)
  1908 `ifdef CFG_DEBUG_ENABLED
  1909                && (bp_match == `FALSE)
  1910 `endif
  1912 assign store_q_x = (store_x == `TRUE) 
  1913                && (q_x == `TRUE)
  1914 `ifdef CFG_DEBUG_ENABLED
  1915                && (bp_match == `FALSE)
  1916 `endif
  1918 `ifdef CFG_USER_ENABLED
  1919 assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
  1920 `endif                              
  1921 assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
  1922 assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
  1923 assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
  1924 `ifdef CFG_DEBUG_ENABLED
  1925 assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
  1926 assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));        
  1927 `else
  1928 assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));        
  1929 `endif
  1930 // Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
  1931 assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
  1932 assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
  1933 assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
  1934 // The enable that actually does write the registers needs to be qualified with kill
  1935 assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
  1937 // Configuration (CFG) CSR
  1938 assign cfg = {
  1939               `LM32_REVISION,
  1940               watchpoints[3:0],
  1941               breakpoints[3:0],
  1942               interrupts[5:0],
  1943 `ifdef CFG_JTAG_UART_ENABLED
  1944               `TRUE,
  1945 `else
  1946               `FALSE,
  1947 `endif
  1948 `ifdef CFG_ROM_DEBUG_ENABLED
  1949               `TRUE,
  1950 `else
  1951               `FALSE,
  1952 `endif
  1953 `ifdef CFG_HW_DEBUG_ENABLED
  1954               `TRUE,
  1955 `else
  1956               `FALSE,
  1957 `endif
  1958 `ifdef CFG_DEBUG_ENABLED
  1959               `TRUE,
  1960 `else
  1961               `FALSE,
  1962 `endif
  1963 `ifdef CFG_ICACHE_ENABLED
  1964               `TRUE,
  1965 `else
  1966               `FALSE,
  1967 `endif
  1968 `ifdef CFG_DCACHE_ENABLED
  1969               `TRUE,
  1970 `else
  1971               `FALSE,
  1972 `endif
  1973 `ifdef CFG_CYCLE_COUNTER_ENABLED
  1974               `TRUE,
  1975 `else
  1976               `FALSE,
  1977 `endif
  1978 `ifdef CFG_USER_ENABLED
  1979               `TRUE,
  1980 `else
  1981               `FALSE,
  1982 `endif
  1983 `ifdef CFG_SIGN_EXTEND_ENABLED
  1984               `TRUE,
  1985 `else
  1986               `FALSE,
  1987 `endif
  1988 `ifdef LM32_BARREL_SHIFT_ENABLED
  1989               `TRUE,
  1990 `else
  1991               `FALSE,
  1992 `endif
  1993 `ifdef CFG_MC_DIVIDE_ENABLED
  1994               `TRUE,
  1995 `else
  1996               `FALSE,
  1997 `endif
  1998 `ifdef LM32_MULTIPLY_ENABLED 
  1999               `TRUE
  2000 `else
  2001               `FALSE
  2002 `endif
  2003               };
  2005 assign cfg2 = {
  2006 		     30'b0,
  2007 `ifdef CFG_IROM_ENABLED
  2008 		     `TRUE,
  2009 `else
  2010 		     `FALSE,
  2011 `endif
  2012 `ifdef CFG_DRAM_ENABLED
  2013 		     `TRUE
  2014 `else
  2015 		     `FALSE
  2016 `endif
  2017 		     };
  2019 // Cache flush
  2020 `ifdef CFG_ICACHE_ENABLED
  2021 assign iflush = (   (csr_write_enable_d == `TRUE) 
  2022                  && (csr_d == `LM32_CSR_ICC)
  2023                  && (stall_d == `FALSE)
  2024                  && (kill_d == `FALSE)
  2025                  && (valid_d == `TRUE))
  2026 // Added by GSI: needed to flush cache after loading firmware per JTAG
  2027 `ifdef CFG_HW_DEBUG_ENABLED
  2028              ||
  2029                 (   (jtag_csr_write_enable == `TRUE)
  2030 		 && (jtag_csr == `LM32_CSR_ICC))
  2031 `endif
  2033 `endif 
  2034 `ifdef CFG_DCACHE_ENABLED
  2035 assign dflush_x = (   (csr_write_enable_q_x == `TRUE) 
  2036                    && (csr_x == `LM32_CSR_DCC))
  2037 // Added by GSI: needed to flush cache after loading firmware per JTAG
  2038 `ifdef CFG_HW_DEBUG_ENABLED
  2039                ||
  2040                   (   (jtag_csr_write_enable == `TRUE)
  2041 		   && (jtag_csr == `LM32_CSR_DCC))
  2042 `endif
  2044 `endif 
  2046 // Extract CSR index
  2047 assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
  2049 // CSR reads
  2050 always @(*)
  2051 begin
  2052     case (csr_x)
  2053 `ifdef CFG_INTERRUPTS_ENABLED
  2054     `LM32_CSR_IE,
  2055     `LM32_CSR_IM,
  2056     `LM32_CSR_IP:   csr_read_data_x = interrupt_csr_read_data_x;  
  2057 `endif
  2058 `ifdef CFG_CYCLE_COUNTER_ENABLED
  2059     `LM32_CSR_CC:   csr_read_data_x = cc;
  2060 `endif
  2061     `LM32_CSR_CFG:  csr_read_data_x = cfg;
  2062     `LM32_CSR_EBA:  csr_read_data_x = {eba, 8'h00};
  2063 `ifdef CFG_DEBUG_ENABLED
  2064     `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
  2065 `endif
  2066 `ifdef CFG_JTAG_UART_ENABLED
  2067     `LM32_CSR_JTX:  csr_read_data_x = jtx_csr_read_data;  
  2068     `LM32_CSR_JRX:  csr_read_data_x = jrx_csr_read_data;
  2069 `endif
  2070     `LM32_CSR_CFG2: csr_read_data_x = cfg2;
  2072     default:        csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
  2073     endcase
  2074 end
  2076 /////////////////////////////////////////////////////
  2077 // Sequential Logic
  2078 /////////////////////////////////////////////////////
  2080 // Exception Base Address (EBA) CSR
  2081 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2082 begin
  2083     if (rst_i == `TRUE)
  2084         eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
  2085     else
  2086     begin
  2087         if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
  2088             eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
  2089 `ifdef CFG_HW_DEBUG_ENABLED
  2090         if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
  2091             eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
  2092 `endif
  2093     end
  2094 end
  2096 `ifdef CFG_DEBUG_ENABLED
  2097 // Debug Exception Base Address (DEBA) CSR
  2098 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2099 begin
  2100     if (rst_i == `TRUE)
  2101         deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
  2102     else
  2103     begin
  2104         if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
  2105             deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
  2106 `ifdef CFG_HW_DEBUG_ENABLED
  2107         if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
  2108             deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
  2109 `endif
  2110     end
  2111 end
  2112 `endif
  2114 // Cycle Counter (CC) CSR
  2115 `ifdef CFG_CYCLE_COUNTER_ENABLED
  2116 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2117 begin
  2118     if (rst_i == `TRUE)
  2119         cc <= {`LM32_WORD_WIDTH{1'b0}};
  2120     else
  2121         cc <= cc + 1'b1;
  2122 end
  2123 `endif
  2125 `ifdef CFG_BUS_ERRORS_ENABLED
  2126 // Watch for data bus errors
  2127 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2128 begin
  2129     if (rst_i == `TRUE)
  2130         data_bus_error_seen <= `FALSE;
  2131     else
  2132     begin
  2133         // Set flag when bus error is detected
  2134         if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
  2135             data_bus_error_seen <= `TRUE;
  2136         // Clear flag when exception is taken
  2137         if ((exception_m == `TRUE) && (kill_m == `FALSE))
  2138             data_bus_error_seen <= `FALSE;
  2139     end
  2140 end
  2141 `endif
  2143 // Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not  
  2145 `ifdef CFG_ICACHE_ENABLED
  2146 `ifdef CFG_DCACHE_ENABLED
  2147 always @(*)
  2148 begin
  2149     if (   (icache_refill_request == `TRUE) 
  2150         || (dcache_refill_request == `TRUE)
  2152         valid_a = `FALSE;
  2153     else if (   (icache_restart_request == `TRUE) 
  2154              || (dcache_restart_request == `TRUE) 
  2156         valid_a = `TRUE;
  2157     else 
  2158         valid_a = !icache_refilling && !dcache_refilling;
  2159 end 
  2160 `else
  2161 always @(*)
  2162 begin
  2163     if (icache_refill_request == `TRUE) 
  2164         valid_a = `FALSE;
  2165     else if (icache_restart_request == `TRUE) 
  2166         valid_a = `TRUE;
  2167     else 
  2168         valid_a = !icache_refilling;
  2169 end 
  2170 `endif
  2171 `else
  2172 `ifdef CFG_DCACHE_ENABLED
  2173 always @(*)
  2174 begin
  2175     if (dcache_refill_request == `TRUE) 
  2176         valid_a = `FALSE;
  2177     else if (dcache_restart_request == `TRUE) 
  2178         valid_a = `TRUE;
  2179     else 
  2180         valid_a = !dcache_refilling;
  2181 end 
  2182 `endif
  2183 `endif
  2185 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2186 begin
  2187     if (rst_i == `TRUE)
  2188     begin
  2189         valid_f <= `FALSE;
  2190         valid_d <= `FALSE;
  2191         valid_x <= `FALSE;
  2192         valid_m <= `FALSE;
  2193         valid_w <= `FALSE;
  2194     end
  2195     else
  2196     begin    
  2197         if ((kill_f == `TRUE) || (stall_a == `FALSE))
  2198 `ifdef LM32_CACHE_ENABLED
  2199             valid_f <= valid_a;    
  2200 `else
  2201             valid_f <= `TRUE;
  2202 `endif            
  2203         else if (stall_f == `FALSE)
  2204             valid_f <= `FALSE;            
  2206         if (kill_d == `TRUE)
  2207             valid_d <= `FALSE;
  2208         else if (stall_f == `FALSE)
  2209             valid_d <= valid_f & !kill_f;
  2210         else if (stall_d == `FALSE)
  2211             valid_d <= `FALSE;
  2213         if (stall_d == `FALSE)
  2214             valid_x <= valid_d & !kill_d;
  2215         else if (kill_x == `TRUE)
  2216             valid_x <= `FALSE;
  2217         else if (stall_x == `FALSE)
  2218             valid_x <= `FALSE;
  2220         if (kill_m == `TRUE)
  2221             valid_m <= `FALSE;
  2222         else if (stall_x == `FALSE)
  2223             valid_m <= valid_x & !kill_x;
  2224         else if (stall_m == `FALSE)
  2225             valid_m <= `FALSE;
  2227         if (stall_m == `FALSE)
  2228             valid_w <= valid_m & !kill_m;
  2229         else 
  2230             valid_w <= `FALSE;        
  2231     end
  2232 end
  2234 // Microcode pipeline registers
  2235 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2236 begin
  2237     if (rst_i == `TRUE)
  2238     begin
  2239 `ifdef CFG_USER_ENABLED
  2240         user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};       
  2241 `endif        
  2242         operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
  2243         operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
  2244         store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
  2245         branch_target_x <= {`LM32_PC_WIDTH{1'b0}};        
  2246         x_result_sel_csr_x <= `FALSE;
  2247 `ifdef LM32_MC_ARITHMETIC_ENABLED
  2248         x_result_sel_mc_arith_x <= `FALSE;
  2249 `endif
  2250 `ifdef LM32_NO_BARREL_SHIFT    
  2251         x_result_sel_shift_x <= `FALSE;
  2252 `endif
  2253 `ifdef CFG_SIGN_EXTEND_ENABLED
  2254         x_result_sel_sext_x <= `FALSE;
  2255 `endif  
  2256 	x_result_sel_logic_x <= `FALSE;
  2257 `ifdef CFG_USER_ENABLED
  2258         x_result_sel_user_x <= `FALSE;
  2259 `endif
  2260         x_result_sel_add_x <= `FALSE;
  2261         m_result_sel_compare_x <= `FALSE;
  2262 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2263         m_result_sel_shift_x <= `FALSE;
  2264 `endif    
  2265         w_result_sel_load_x <= `FALSE;
  2266 `ifdef CFG_PL_MULTIPLY_ENABLED
  2267         w_result_sel_mul_x <= `FALSE;
  2268 `endif
  2269         x_bypass_enable_x <= `FALSE;
  2270         m_bypass_enable_x <= `FALSE;
  2271         write_enable_x <= `FALSE;
  2272         write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
  2273         csr_x <= {`LM32_CSR_WIDTH{1'b0}};
  2274         load_x <= `FALSE;
  2275         store_x <= `FALSE;
  2276         size_x <= {`LM32_SIZE_WIDTH{1'b0}};
  2277         sign_extend_x <= `FALSE;
  2278         adder_op_x <= `FALSE;
  2279         adder_op_x_n <= `FALSE;
  2280         logic_op_x <= 4'h0;
  2281 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2282         direction_x <= `FALSE;
  2283 `endif
  2284 `ifdef CFG_ROTATE_ENABLED
  2285         rotate_x <= `FALSE;
  2287 `endif
  2288         branch_x <= `FALSE;
  2289         branch_predict_x <= `FALSE;
  2290         branch_predict_taken_x <= `FALSE;
  2291         condition_x <= `LM32_CONDITION_U1;
  2292 `ifdef CFG_DEBUG_ENABLED
  2293         break_x <= `FALSE;
  2294 `endif
  2295         scall_x <= `FALSE;
  2296         eret_x <= `FALSE;
  2297 `ifdef CFG_DEBUG_ENABLED
  2298         bret_x <= `FALSE;
  2299 `endif
  2300 `ifdef CFG_BUS_ERRORS_ENABLED
  2301         bus_error_x <= `FALSE;
  2302         data_bus_error_exception_m <= `FALSE;
  2303 `endif
  2304         csr_write_enable_x <= `FALSE;
  2305         operand_m <= {`LM32_WORD_WIDTH{1'b0}};
  2306         branch_target_m <= {`LM32_PC_WIDTH{1'b0}};
  2307         m_result_sel_compare_m <= `FALSE;
  2308 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2309         m_result_sel_shift_m <= `FALSE;
  2310 `endif    
  2311         w_result_sel_load_m <= `FALSE;
  2312 `ifdef CFG_PL_MULTIPLY_ENABLED
  2313         w_result_sel_mul_m <= `FALSE;
  2314 `endif
  2315         m_bypass_enable_m <= `FALSE;
  2316         branch_m <= `FALSE;
  2317         branch_predict_m <= `FALSE;
  2318 	branch_predict_taken_m <= `FALSE;
  2319         exception_m <= `FALSE;
  2320         load_m <= `FALSE;
  2321         store_m <= `FALSE;
  2322         write_enable_m <= `FALSE;            
  2323         write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
  2324         condition_met_m <= `FALSE;
  2325 `ifdef CFG_DCACHE_ENABLED
  2326         dflush_m <= `FALSE;
  2327 `endif
  2328 `ifdef CFG_DEBUG_ENABLED
  2329         debug_exception_m <= `FALSE;
  2330         non_debug_exception_m <= `FALSE;        
  2331 `endif
  2332         operand_w <= {`LM32_WORD_WIDTH{1'b0}};        
  2333         w_result_sel_load_w <= `FALSE;
  2334 `ifdef CFG_PL_MULTIPLY_ENABLED
  2335         w_result_sel_mul_w <= `FALSE;
  2336 `endif
  2337         write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};        
  2338         write_enable_w <= `FALSE;
  2339 `ifdef CFG_DEBUG_ENABLED
  2340         debug_exception_w <= `FALSE;
  2341         non_debug_exception_w <= `FALSE;        
  2342 `else
  2343         exception_w <= `FALSE;
  2344 `endif
  2345 `ifdef CFG_BUS_ERRORS_ENABLED
  2346         memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
  2347 `endif
  2348     end
  2349     else
  2350     begin
  2351         // D/X stage registers
  2353         if (stall_x == `FALSE)
  2354         begin
  2355 `ifdef CFG_USER_ENABLED
  2356             user_opcode <= user_opcode_d;       
  2357 `endif        
  2358             operand_0_x <= d_result_0;
  2359             operand_1_x <= d_result_1;
  2360             store_operand_x <= bypass_data_1;
  2361             branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;            
  2362             x_result_sel_csr_x <= x_result_sel_csr_d;
  2363 `ifdef LM32_MC_ARITHMETIC_ENABLED
  2364             x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
  2365 `endif
  2366 `ifdef LM32_NO_BARREL_SHIFT    
  2367             x_result_sel_shift_x <= x_result_sel_shift_d;
  2368 `endif
  2369 `ifdef CFG_SIGN_EXTEND_ENABLED
  2370             x_result_sel_sext_x <= x_result_sel_sext_d;
  2371 `endif    
  2372 	    x_result_sel_logic_x <= x_result_sel_logic_d;
  2373 `ifdef CFG_USER_ENABLED
  2374             x_result_sel_user_x <= x_result_sel_user_d;
  2375 `endif
  2376             x_result_sel_add_x <= x_result_sel_add_d;
  2377             m_result_sel_compare_x <= m_result_sel_compare_d;
  2378 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2379             m_result_sel_shift_x <= m_result_sel_shift_d;
  2380 `endif    
  2381             w_result_sel_load_x <= w_result_sel_load_d;
  2382 `ifdef CFG_PL_MULTIPLY_ENABLED
  2383             w_result_sel_mul_x <= w_result_sel_mul_d;
  2384 `endif
  2385             x_bypass_enable_x <= x_bypass_enable_d;
  2386             m_bypass_enable_x <= m_bypass_enable_d;
  2387             load_x <= load_d;
  2388             store_x <= store_d;
  2389             branch_x <= branch_d;
  2390 	    branch_predict_x <= branch_predict_d;
  2391 	    branch_predict_taken_x <= branch_predict_taken_d;
  2392 	    write_idx_x <= write_idx_d;
  2393             csr_x <= csr_d;
  2394             size_x <= size_d;
  2395             sign_extend_x <= sign_extend_d;
  2396             adder_op_x <= adder_op_d;
  2397             adder_op_x_n <= ~adder_op_d;
  2398             logic_op_x <= logic_op_d;
  2399 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2400             direction_x <= direction_d;
  2401 `endif
  2402 `ifdef CFG_ROTATE_ENABLED
  2403             rotate_x <= rotate_d;
  2404 `endif
  2405             condition_x <= condition_d;
  2406             csr_write_enable_x <= csr_write_enable_d;
  2407 `ifdef CFG_DEBUG_ENABLED
  2408             break_x <= break_d;
  2409 `endif
  2410             scall_x <= scall_d;
  2411 `ifdef CFG_BUS_ERRORS_ENABLED
  2412             bus_error_x <= bus_error_d;
  2413 `endif
  2414             eret_x <= eret_d;
  2415 `ifdef CFG_DEBUG_ENABLED
  2416             bret_x <= bret_d; 
  2417 `endif
  2418             write_enable_x <= write_enable_d;
  2419         end
  2421         // X/M stage registers
  2423         if (stall_m == `FALSE)
  2424         begin
  2425             operand_m <= x_result;
  2426             m_result_sel_compare_m <= m_result_sel_compare_x;
  2427 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2428             m_result_sel_shift_m <= m_result_sel_shift_x;
  2429 `endif    
  2430             if (exception_x == `TRUE)
  2431             begin
  2432                 w_result_sel_load_m <= `FALSE;
  2433 `ifdef CFG_PL_MULTIPLY_ENABLED
  2434                 w_result_sel_mul_m <= `FALSE;
  2435 `endif
  2436             end
  2437             else
  2438             begin
  2439                 w_result_sel_load_m <= w_result_sel_load_x;
  2440 `ifdef CFG_PL_MULTIPLY_ENABLED
  2441                 w_result_sel_mul_m <= w_result_sel_mul_x;
  2442 `endif
  2443             end
  2444             m_bypass_enable_m <= m_bypass_enable_x;
  2445 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
  2446 `endif
  2447             load_m <= load_x;
  2448             store_m <= store_x;
  2449 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH    
  2450             branch_m <= branch_x && !branch_taken_x;
  2451 `else
  2452             branch_m <= branch_x;
  2453 	    branch_predict_m <= branch_predict_x;
  2454 	    branch_predict_taken_m <= branch_predict_taken_x;
  2455 `endif
  2456 `ifdef CFG_DEBUG_ENABLED
  2457 	   // Data bus errors are generated by the wishbone and are
  2458 	   // made known to the processor only in next cycle (as a
  2459 	   // non-debug exception). A break instruction can be seen
  2460 	   // in same cycle (causing a debug exception). Handle non
  2461 	   // -debug exception first!
  2462             if (non_debug_exception_x == `TRUE) 
  2463                 write_idx_m <= `LM32_EA_REG;
  2464             else if (debug_exception_x == `TRUE)
  2465                 write_idx_m <= `LM32_BA_REG;
  2466             else 
  2467                 write_idx_m <= write_idx_x;
  2468 `else
  2469             if (exception_x == `TRUE)
  2470                 write_idx_m <= `LM32_EA_REG;
  2471             else 
  2472                 write_idx_m <= write_idx_x;
  2473 `endif
  2474             condition_met_m <= condition_met_x;
  2475 `ifdef CFG_DEBUG_ENABLED
  2476 	   if (exception_x == `TRUE)
  2477 	     if ((dc_re == `TRUE)
  2478 		 || ((debug_exception_x == `TRUE) 
  2479 		     && (non_debug_exception_x == `FALSE)))
  2480 	       branch_target_m <= {deba, eid_x, {3{1'b0}}};
  2481 	     else
  2482 	       branch_target_m <= {eba, eid_x, {3{1'b0}}};
  2483 	   else
  2484 	     branch_target_m <= branch_target_x;
  2485 `else
  2486             branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
  2487 `endif
  2488 `ifdef CFG_TRACE_ENABLED
  2489             eid_m <= eid_x;
  2490 `endif
  2491 `ifdef CFG_DCACHE_ENABLED
  2492             dflush_m <= dflush_x;
  2493 `endif
  2494             eret_m <= eret_q_x;
  2495 `ifdef CFG_DEBUG_ENABLED
  2496             bret_m <= bret_q_x; 
  2497 `endif
  2498             write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;            
  2499 `ifdef CFG_DEBUG_ENABLED
  2500             debug_exception_m <= debug_exception_x;
  2501             non_debug_exception_m <= non_debug_exception_x;        
  2502 `endif
  2503         end
  2505         // State changing regs
  2506         if (stall_m == `FALSE)
  2507         begin
  2508             if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
  2509                 exception_m <= `TRUE;
  2510             else 
  2511                 exception_m <= `FALSE;
  2512 `ifdef CFG_BUS_ERRORS_ENABLED
  2513 	   data_bus_error_exception_m <=    (data_bus_error_exception == `TRUE) 
  2514 `ifdef CFG_DEBUG_ENABLED
  2515 					 && (reset_exception == `FALSE)
  2516 `endif
  2518 `endif
  2519 	end
  2521         // M/W stage registers
  2522 `ifdef CFG_BUS_ERRORS_ENABLED
  2523         operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
  2524 `else
  2525         operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
  2526 `endif
  2527         w_result_sel_load_w <= w_result_sel_load_m;
  2528 `ifdef CFG_PL_MULTIPLY_ENABLED
  2529         w_result_sel_mul_w <= w_result_sel_mul_m;
  2530 `endif
  2531         write_idx_w <= write_idx_m;
  2532 `ifdef CFG_TRACE_ENABLED
  2533         eid_w <= eid_m;
  2534         eret_w <= eret_m;
  2535 `ifdef CFG_DEBUG_ENABLED
  2536         bret_w <= bret_m; 
  2537 `endif
  2538 `endif
  2539         write_enable_w <= write_enable_m;
  2540 `ifdef CFG_DEBUG_ENABLED
  2541         debug_exception_w <= debug_exception_m;
  2542         non_debug_exception_w <= non_debug_exception_m;
  2543 `else
  2544         exception_w <= exception_m;
  2545 `endif
  2546 `ifdef CFG_BUS_ERRORS_ENABLED
  2547         if (   (stall_m == `FALSE)
  2548             && (   (load_q_m == `TRUE) 
  2549                 || (store_q_m == `TRUE)
  2552           memop_pc_w <= pc_m;
  2553 `endif
  2554     end
  2555 end
  2557 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
  2558 // Buffer data read from register file, in case a stall occurs, and watch for
  2559 // any writes to the modified registers
  2560 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2561 begin
  2562     if (rst_i == `TRUE)
  2563     begin
  2564         use_buf <= `FALSE;
  2565         reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
  2566         reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
  2567     end
  2568     else
  2569     begin
  2570         if (stall_d == `FALSE)
  2571             use_buf <= `FALSE;
  2572         else if (use_buf == `FALSE)
  2573         begin        
  2574             reg_data_buf_0 <= reg_data_live_0;
  2575             reg_data_buf_1 <= reg_data_live_1;
  2576             use_buf <= `TRUE;
  2577         end        
  2578         if (reg_write_enable_q_w == `TRUE)
  2579         begin
  2580             if (write_idx_w == read_idx_0_d)
  2581                 reg_data_buf_0 <= w_result;
  2582             if (write_idx_w == read_idx_1_d)
  2583                 reg_data_buf_1 <= w_result;
  2584         end
  2585     end
  2586 end
  2587 `endif
  2589 `ifdef LM32_EBR_REGISTER_FILE
  2590 `else
  2591 // Register file write port
  2592 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2593 begin
  2594     if (rst_i == `TRUE) begin
  2595         registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
  2596         registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
  2597         registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
  2598         registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
  2599         registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
  2600         registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
  2601         registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
  2602         registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
  2603         registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
  2604         registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
  2605         registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
  2606         registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
  2607         registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
  2608         registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
  2609         registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
  2610         registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
  2611         registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
  2612         registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
  2613         registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
  2614         registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
  2615         registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
  2616         registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
  2617         registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
  2618         registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
  2619         registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
  2620         registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
  2621         registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
  2622         registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
  2623         registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
  2624         registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
  2625         registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
  2626         registers[31] <= {`LM32_WORD_WIDTH{1'b0}}; 
  2627         end
  2628     else begin
  2629         if (reg_write_enable_q_w == `TRUE)
  2630           registers[write_idx_w] <= w_result;
  2631         end
  2632 end
  2633 `endif
  2635 `ifdef CFG_TRACE_ENABLED
  2636 // PC tracing logic
  2637 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
  2638 begin
  2639     if (rst_i == `TRUE)
  2640     begin
  2641         trace_pc_valid <= `FALSE;
  2642         trace_pc <= {`LM32_PC_WIDTH{1'b0}};
  2643         trace_exception <= `FALSE;
  2644         trace_eid <= `LM32_EID_RESET;
  2645         trace_eret <= `FALSE;
  2646 `ifdef CFG_DEBUG_ENABLED
  2647         trace_bret <= `FALSE;
  2648 `endif
  2649         pc_c <= `CFG_EBA_RESET/4;
  2650     end
  2651     else
  2652     begin
  2653         trace_pc_valid <= `FALSE;
  2654         // Has an exception occured
  2655 `ifdef CFG_DEBUG_ENABLED
  2656         if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
  2657 `else
  2658         if (exception_q_w == `TRUE)
  2659 `endif
  2660         begin        
  2661             trace_exception <= `TRUE;
  2662             trace_pc_valid <= `TRUE;
  2663             trace_pc <= pc_w;
  2664             trace_eid <= eid_w;
  2665         end
  2666         else
  2667             trace_exception <= `FALSE;
  2669         if ((valid_w == `TRUE) && (!kill_w))
  2670         begin
  2671             // An instruction is commiting. Determine if it is non-sequential
  2672             if (pc_c + 1'b1 != pc_w)
  2673             begin
  2674                 // Non-sequential instruction
  2675                 trace_pc_valid <= `TRUE;
  2676                 trace_pc <= pc_w;
  2677             end
  2678             // Record PC so we can determine if next instruction is sequential or not
  2679             pc_c <= pc_w;
  2680             // Indicate if it was an eret/bret instruction
  2681             trace_eret <= eret_w;
  2682 `ifdef CFG_DEBUG_ENABLED
  2683             trace_bret <= bret_w;
  2684 `endif
  2685         end
  2686         else
  2687         begin
  2688             trace_eret <= `FALSE;
  2689 `ifdef CFG_DEBUG_ENABLED
  2690             trace_bret <= `FALSE;
  2691 `endif
  2692         end
  2693     end
  2694 end
  2695 `endif
  2697 /////////////////////////////////////////////////////
  2698 // Behavioural Logic
  2699 /////////////////////////////////////////////////////
  2701 // synthesis translate_off            
  2703 // Reset register 0. Only needed for simulation. 
  2704 initial
  2705 begin
  2706 `ifdef LM32_EBR_REGISTER_FILE
  2707     reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
  2708     reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
  2709 `else
  2710     registers[0] = {`LM32_WORD_WIDTH{1'b0}};
  2711 `endif
  2712 end
  2714 // synthesis translate_on
  2716 endmodule