lm32_dp_ram.v

Sun, 06 Mar 2011 21:03:32 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 21:03:32 +0000
changeset 18
cc945f778cd7
permissions
-rw-r--r--

Commit GSI patches from Wesley Terpstra

- Add JTAG capture pin
==> allows removing sensitivity to reg_update which caused clocking problems making JTAG unstable
- Use register file backed by RAM blocks
==> saves quite some area and speed on altera
... be sure to enable it using `define CFG_EBR_POSEDGE_REGISTER_FILE
- Fix a minor problem where compilation fails when interrupts are not supported
- Add support to flush icache and dcache per JTAG
- Fix wrong width assignments for PC

Multiplier patch has been left out for now; don't the design synthesizers (Quartus / Xst) split the multiply automatically?

Original-Author: Wesley Terpstra <w.terpsta gsi.de>
Original-Source: Milkymist mailing list postings, 2011-02-28 (11:19 and 13:32) and 2011-03-01
Original-Message-Ids: <4D6B84B5.9040604@gsi.de> <4D6BA3E4.3020609@gsi.de> <4D6CFFF2.6030703@gsi.de>

     1 module lm32_dp_ram(
     2 	clk_i,
     3 	rst_i,
     4 	we_i,
     5 	waddr_i,
     6 	wdata_i,
     7 	raddr_i,
     8 	rdata_o);
    10 parameter addr_width = 32;
    11 parameter addr_depth = 1024;
    12 parameter data_width = 8;
    14 input clk_i;
    15 input rst_i;
    16 input we_i;
    17 input [addr_width-1:0] waddr_i;
    18 input [data_width-1:0] wdata_i;
    19 input [addr_width-1:0] raddr_i;
    20 output [data_width-1:0] rdata_o;
    22 reg [data_width-1:0] ram[addr_depth-1:0];
    24 reg [addr_width-1:0] raddr_r;
    25 assign rdata_o = ram[raddr_r];
    27 always @ (posedge clk_i)
    28 begin
    29 	if (we_i)
    30 		ram[waddr_i] <= wdata_i;
    31 	raddr_r <= raddr_i;
    32 end
    34 endmodule