lm32_jtag.v

Sun, 06 Mar 2011 21:03:32 +0000

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 06 Mar 2011 21:03:32 +0000
changeset 18
cc945f778cd7
parent 14
54dd95f89113
permissions
-rwxr-xr-x

Commit GSI patches from Wesley Terpstra

- Add JTAG capture pin
==> allows removing sensitivity to reg_update which caused clocking problems making JTAG unstable
- Use register file backed by RAM blocks
==> saves quite some area and speed on altera
... be sure to enable it using `define CFG_EBR_POSEDGE_REGISTER_FILE
- Fix a minor problem where compilation fails when interrupts are not supported
- Add support to flush icache and dcache per JTAG
- Fix wrong width assignments for PC

Multiplier patch has been left out for now; don't the design synthesizers (Quartus / Xst) split the multiply automatically?

Original-Author: Wesley Terpstra <w.terpsta gsi.de>
Original-Source: Milkymist mailing list postings, 2011-02-28 (11:19 and 13:32) and 2011-03-01
Original-Message-Ids: <4D6B84B5.9040604@gsi.de> <4D6BA3E4.3020609@gsi.de> <4D6CFFF2.6030703@gsi.de>

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : lm32_jtag.v
    19 // Title            : JTAG interface
    20 // Dependencies     : lm32_include.v
    21 // Version          : 6.1.17
    22 //                  : Initial Release
    23 // Version          : 7.0SP2, 3.0
    24 //                  : No Change
    25 // Version          : 3.1
    26 //                  : No Change
    27 // =============================================================================
    29 `include "lm32_include.v"
    31 `ifdef CFG_JTAG_ENABLED
    33 `define LM32_DP                             3'b000
    34 `define LM32_TX                             3'b001
    35 `define LM32_RX                             3'b010
    37 // LM32 Debug Protocol commands IDs
    38 `define LM32_DP_RNG                         3:0
    39 `define LM32_DP_READ_MEMORY                 4'b0001
    40 `define LM32_DP_WRITE_MEMORY                4'b0010
    41 `define LM32_DP_READ_SEQUENTIAL             4'b0011
    42 `define LM32_DP_WRITE_SEQUENTIAL            4'b0100
    43 `define LM32_DP_WRITE_CSR                   4'b0101
    44 `define LM32_DP_BREAK                       4'b0110
    45 `define LM32_DP_RESET                       4'b0111
    47 // States for FSM
    48 `define LM32_JTAG_STATE_RNG                 3:0
    49 `define LM32_JTAG_STATE_READ_COMMAND        4'h0
    50 `define LM32_JTAG_STATE_READ_BYTE_0         4'h1
    51 `define LM32_JTAG_STATE_READ_BYTE_1         4'h2
    52 `define LM32_JTAG_STATE_READ_BYTE_2         4'h3
    53 `define LM32_JTAG_STATE_READ_BYTE_3         4'h4
    54 `define LM32_JTAG_STATE_READ_BYTE_4         4'h5
    55 `define LM32_JTAG_STATE_PROCESS_COMMAND     4'h6
    56 `define LM32_JTAG_STATE_WAIT_FOR_MEMORY     4'h7
    57 `define LM32_JTAG_STATE_WAIT_FOR_CSR        4'h8
    59 /////////////////////////////////////////////////////
    60 // Module interface
    61 /////////////////////////////////////////////////////
    63 module lm32_jtag (
    64     // ----- Inputs -------
    65     clk_i,
    66     rst_i,
    67     jtag_clk, 
    68     jtag_update,
    69     jtag_reg_q,
    70     jtag_reg_addr_q,
    71 `ifdef CFG_JTAG_UART_ENABLED
    72     csr,
    73     csr_write_enable,
    74     csr_write_data,
    75     stall_x,
    76 `endif
    77 `ifdef CFG_HW_DEBUG_ENABLED
    78     jtag_read_data,
    79     jtag_access_complete,
    80 `endif
    81 `ifdef CFG_DEBUG_ENABLED
    82     exception_q_w,
    83 `endif
    84     // ----- Outputs -------
    85 `ifdef CFG_JTAG_UART_ENABLED
    86     jtx_csr_read_data,
    87     jrx_csr_read_data,
    88 `endif
    89 `ifdef CFG_HW_DEBUG_ENABLED
    90     jtag_csr_write_enable,
    91     jtag_csr_write_data,
    92     jtag_csr,
    93     jtag_read_enable,
    94     jtag_write_enable,
    95     jtag_write_data,
    96     jtag_address,
    97 `endif
    98 `ifdef CFG_DEBUG_ENABLED
    99     jtag_break,
   100     jtag_reset,
   101 `endif
   102     jtag_reg_d,
   103     jtag_reg_addr_d
   104     );
   106 /////////////////////////////////////////////////////
   107 // Inputs
   108 /////////////////////////////////////////////////////
   110 input clk_i;                                            // Clock
   111 input rst_i;                                            // Reset
   113 input jtag_clk;                                         // JTAG clock
   114 input jtag_update;                                      // JTAG data register has been updated
   115 input [`LM32_BYTE_RNG] jtag_reg_q;                      // JTAG data register
   116 input [2:0] jtag_reg_addr_q;                            // JTAG data register
   118 `ifdef CFG_JTAG_UART_ENABLED
   119 input [`LM32_CSR_RNG] csr;                              // CSR to write
   120 input csr_write_enable;                                 // CSR write enable
   121 input [`LM32_WORD_RNG] csr_write_data;                  // Data to write to specified CSR
   122 input stall_x;                                          // Stall instruction in X stage
   123 `endif
   124 `ifdef CFG_HW_DEBUG_ENABLED
   125 input [`LM32_BYTE_RNG] jtag_read_data;                  // Data read from requested address
   126 input jtag_access_complete;                             // Memory access if complete
   127 `endif
   128 `ifdef CFG_DEBUG_ENABLED
   129 input exception_q_w;                                    // Indicates an exception has occured in W stage
   130 `endif
   132 /////////////////////////////////////////////////////
   133 // Outputs
   134 /////////////////////////////////////////////////////
   136 `ifdef CFG_JTAG_UART_ENABLED
   137 output [`LM32_WORD_RNG] jtx_csr_read_data;              // Value of JTX CSR for rcsr instructions
   138 wire   [`LM32_WORD_RNG] jtx_csr_read_data;
   139 output [`LM32_WORD_RNG] jrx_csr_read_data;              // Value of JRX CSR for rcsr instructions
   140 wire   [`LM32_WORD_RNG] jrx_csr_read_data;
   141 `endif
   142 `ifdef CFG_HW_DEBUG_ENABLED
   143 output jtag_csr_write_enable;                           // CSR write enable
   144 reg    jtag_csr_write_enable;
   145 output [`LM32_WORD_RNG] jtag_csr_write_data;            // Data to write to specified CSR
   146 wire   [`LM32_WORD_RNG] jtag_csr_write_data;
   147 output [`LM32_CSR_RNG] jtag_csr;                        // CSR to write
   148 wire   [`LM32_CSR_RNG] jtag_csr;
   149 output jtag_read_enable;                                // Memory read enable
   150 reg    jtag_read_enable;
   151 output jtag_write_enable;                               // Memory write enable
   152 reg    jtag_write_enable;
   153 output [`LM32_BYTE_RNG] jtag_write_data;                // Data to write to specified address
   154 wire   [`LM32_BYTE_RNG] jtag_write_data;        
   155 output [`LM32_WORD_RNG] jtag_address;                   // Memory read/write address
   156 wire   [`LM32_WORD_RNG] jtag_address;
   157 `endif
   158 `ifdef CFG_DEBUG_ENABLED
   159 output jtag_break;                                      // Request to raise a breakpoint exception
   160 reg    jtag_break;
   161 output jtag_reset;                                      // Request to raise a reset exception
   162 reg    jtag_reset;
   163 `endif
   164 output [`LM32_BYTE_RNG] jtag_reg_d;
   165 reg    [`LM32_BYTE_RNG] jtag_reg_d;
   166 output [2:0] jtag_reg_addr_d;
   167 wire   [2:0] jtag_reg_addr_d;
   169 /////////////////////////////////////////////////////
   170 // Internal nets and registers 
   171 /////////////////////////////////////////////////////
   173 reg rx_update;                          // Clock-domain crossing registers
   174 reg rx_update_r;                        // Registered version of rx_update
   175 reg rx_update_r_r;                      // Registered version of rx_update_r
   176 reg rx_update_r_r_r;                    // Registered version of rx_update_r_r
   178 // These wires come from the JTAG clock domain.
   179 // They have been held unchanged for an entire JTAG clock cycle before the jtag_update toggle flips
   180 wire [`LM32_BYTE_RNG] rx_byte;   
   181 wire [2:0] rx_addr;
   183 `ifdef CFG_JTAG_UART_ENABLED                 
   184 reg [`LM32_BYTE_RNG] uart_tx_byte;      // UART TX data
   185 reg uart_tx_valid;                      // TX data is valid
   186 reg [`LM32_BYTE_RNG] uart_rx_byte;      // UART RX data
   187 reg uart_rx_valid;                      // RX data is valid
   188 `endif
   190 reg [`LM32_DP_RNG] command;             // The last received command
   191 `ifdef CFG_HW_DEBUG_ENABLED
   192 reg [`LM32_BYTE_RNG] jtag_byte_0;       // Registers to hold command paramaters
   193 reg [`LM32_BYTE_RNG] jtag_byte_1;
   194 reg [`LM32_BYTE_RNG] jtag_byte_2;
   195 reg [`LM32_BYTE_RNG] jtag_byte_3;
   196 reg [`LM32_BYTE_RNG] jtag_byte_4;
   197 reg processing;                         // Indicates if we're still processing a memory read/write
   198 `endif
   200 reg [`LM32_JTAG_STATE_RNG] state;       // Current state of FSM
   202 /////////////////////////////////////////////////////
   203 // Combinational Logic
   204 /////////////////////////////////////////////////////
   206 `ifdef CFG_HW_DEBUG_ENABLED
   207 assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
   208 assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
   209 assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
   210 assign jtag_write_data = jtag_byte_4;
   211 `endif
   213 // Generate status flags for reading via the JTAG interface                 
   214 `ifdef CFG_JTAG_UART_ENABLED                 
   215 assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};         
   216 `else
   217 assign jtag_reg_addr_d[1:0] = 2'b00;
   218 `endif
   219 `ifdef CFG_HW_DEBUG_ENABLED
   220 assign jtag_reg_addr_d[2] = processing;
   221 `else
   222 assign jtag_reg_addr_d[2] = 1'b0;
   223 `endif
   225 `ifdef CFG_JTAG_UART_ENABLED                 
   226 assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
   227 assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
   228 `endif         
   230 /////////////////////////////////////////////////////
   231 // Sequential Logic
   232 /////////////////////////////////////////////////////
   234 assign rx_byte = jtag_reg_q;
   235 assign rx_addr = jtag_reg_addr_q;
   237 // The JTAG latched jtag_reg[_addr]_q at least one JTCK before jtag_update is raised
   238 // Thus, they are stable (and safe to sample) when jtag_update is high
   239 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   240 begin
   241     if (rst_i == `TRUE)
   242     begin
   243         rx_update <= 1'b0;
   244         rx_update_r <= 1'b0;
   245         rx_update_r_r <= 1'b0;
   246         rx_update_r_r_r <= 1'b0;
   247     end
   248     else
   249     begin
   250         rx_update <= jtag_update;
   251         rx_update_r <= rx_update;
   252         rx_update_r_r <= rx_update_r;
   253         rx_update_r_r_r <= rx_update_r_r;
   254     end
   255 end
   257 // LM32 debug protocol state machine
   258 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
   259 begin
   260     if (rst_i == `TRUE)
   261     begin
   262         state <= `LM32_JTAG_STATE_READ_COMMAND;
   263         command <= 4'b0000;
   264         jtag_reg_d <= 8'h00;
   265 `ifdef CFG_HW_DEBUG_ENABLED
   266         processing <= `FALSE;
   267         jtag_csr_write_enable <= `FALSE;
   268         jtag_read_enable <= `FALSE;
   269         jtag_write_enable <= `FALSE;
   270 `endif
   271 `ifdef CFG_DEBUG_ENABLED
   272         jtag_break <= `FALSE;
   273         jtag_reset <= `FALSE;
   274 `endif
   275 `ifdef CFG_JTAG_UART_ENABLED                 
   276         uart_tx_byte <= 8'h00;
   277         uart_tx_valid <= `FALSE;
   278         uart_rx_byte <= 8'h00;
   279         uart_rx_valid <= `FALSE;
   280 `endif
   281     end
   282     else
   283     begin
   284 `ifdef CFG_JTAG_UART_ENABLED                 
   285         if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
   286         begin
   287             case (csr)
   288             `LM32_CSR_JTX:
   289             begin
   290                 // Set flag indicating data is available
   291                 uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
   292                 uart_tx_valid <= `TRUE;
   293             end
   294             `LM32_CSR_JRX:
   295             begin
   296                 // Clear flag indidicating data has been received
   297                 uart_rx_valid <= `FALSE;
   298             end
   299             endcase
   300         end
   301 `endif
   302 `ifdef CFG_DEBUG_ENABLED
   303         // When an exception has occured, clear the requests
   304         if (exception_q_w == `TRUE)
   305         begin
   306             jtag_break <= `FALSE;
   307             jtag_reset <= `FALSE;
   308         end
   309 `endif
   310         case (state)
   311         `LM32_JTAG_STATE_READ_COMMAND:
   312         begin
   313             // Wait for rx register to toggle which indicates new data is available
   314             if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
   315             begin
   316                 command <= rx_byte[7:4];                
   317                 case (rx_addr)
   318 `ifdef CFG_DEBUG_ENABLED
   319                 `LM32_DP:
   320                 begin
   321                     case (rx_byte[7:4])
   322 `ifdef CFG_HW_DEBUG_ENABLED
   323                     `LM32_DP_READ_MEMORY:
   324                         state <= `LM32_JTAG_STATE_READ_BYTE_0;
   325                     `LM32_DP_READ_SEQUENTIAL:
   326                     begin
   327                         {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
   328                         state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   329                     end
   330                     `LM32_DP_WRITE_MEMORY:
   331                         state <= `LM32_JTAG_STATE_READ_BYTE_0;
   332                     `LM32_DP_WRITE_SEQUENTIAL:
   333                     begin
   334                         {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
   335                         state <= 5;
   336                     end
   337                     `LM32_DP_WRITE_CSR:
   338                         state <= `LM32_JTAG_STATE_READ_BYTE_0;
   339 `endif                    
   340                     `LM32_DP_BREAK:
   341                     begin
   342 `ifdef CFG_JTAG_UART_ENABLED     
   343                         uart_rx_valid <= `FALSE;    
   344                         uart_tx_valid <= `FALSE;         
   345 `endif
   346                         jtag_break <= `TRUE;
   347                     end
   348                     `LM32_DP_RESET:
   349                     begin
   350 `ifdef CFG_JTAG_UART_ENABLED     
   351                         uart_rx_valid <= `FALSE;    
   352                         uart_tx_valid <= `FALSE;         
   353 `endif
   354                         jtag_reset <= `TRUE;
   355                     end
   356                     endcase                               
   357                 end
   358 `endif
   359 `ifdef CFG_JTAG_UART_ENABLED                 
   360                 `LM32_TX:
   361                 begin
   362                     uart_rx_byte <= rx_byte;
   363                     uart_rx_valid <= `TRUE;
   364                 end                    
   365                 `LM32_RX:
   366                 begin
   367                     jtag_reg_d <= uart_tx_byte;
   368                     uart_tx_valid <= `FALSE;
   369                 end
   370 `endif
   371                 default:
   372                     ;
   373                 endcase                
   374             end
   375         end
   376 `ifdef CFG_HW_DEBUG_ENABLED
   377         `LM32_JTAG_STATE_READ_BYTE_0:
   378         begin
   379             if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
   380             begin
   381                 jtag_byte_0 <= rx_byte;
   382                 state <= `LM32_JTAG_STATE_READ_BYTE_1;
   383             end
   384         end
   385         `LM32_JTAG_STATE_READ_BYTE_1:
   386         begin
   387             if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
   388             begin
   389                 jtag_byte_1 <= rx_byte;
   390                 state <= `LM32_JTAG_STATE_READ_BYTE_2;
   391             end
   392         end
   393         `LM32_JTAG_STATE_READ_BYTE_2:
   394         begin
   395             if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
   396             begin
   397                 jtag_byte_2 <= rx_byte;
   398                 state <= `LM32_JTAG_STATE_READ_BYTE_3;
   399             end
   400         end
   401         `LM32_JTAG_STATE_READ_BYTE_3:
   402         begin
   403             if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
   404             begin
   405                 jtag_byte_3 <= rx_byte;
   406                 if (command == `LM32_DP_READ_MEMORY)
   407                     state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   408                 else 
   409                     state <= `LM32_JTAG_STATE_READ_BYTE_4;
   410             end
   411         end
   412         `LM32_JTAG_STATE_READ_BYTE_4:
   413         begin
   414             if ((~rx_update_r_r_r & rx_update_r_r) == `TRUE)
   415             begin
   416                 jtag_byte_4 <= rx_byte;
   417                 state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
   418             end
   419         end
   420         `LM32_JTAG_STATE_PROCESS_COMMAND:
   421         begin
   422             case (command)
   423             `LM32_DP_READ_MEMORY,
   424             `LM32_DP_READ_SEQUENTIAL:
   425             begin
   426                 jtag_read_enable <= `TRUE;
   427                 processing <= `TRUE;
   428                 state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   429             end
   430             `LM32_DP_WRITE_MEMORY,
   431             `LM32_DP_WRITE_SEQUENTIAL:
   432             begin
   433                 jtag_write_enable <= `TRUE;
   434                 processing <= `TRUE;
   435                 state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
   436             end
   437             `LM32_DP_WRITE_CSR:
   438             begin
   439                 jtag_csr_write_enable <= `TRUE;
   440                 processing <= `TRUE;
   441                 state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
   442             end
   443             endcase
   444         end
   445         `LM32_JTAG_STATE_WAIT_FOR_MEMORY:
   446         begin
   447             if (jtag_access_complete == `TRUE)
   448             begin          
   449                 jtag_read_enable <= `FALSE;
   450                 jtag_reg_d <= jtag_read_data;
   451                 jtag_write_enable <= `FALSE;  
   452                 processing <= `FALSE;
   453                 state <= `LM32_JTAG_STATE_READ_COMMAND;
   454             end
   455         end    
   456         `LM32_JTAG_STATE_WAIT_FOR_CSR:
   457         begin
   458             jtag_csr_write_enable <= `FALSE;
   459             processing <= `FALSE;
   460             state <= `LM32_JTAG_STATE_READ_COMMAND;
   461         end    
   462 `endif
   463         endcase
   464     end
   465 end
   467 endmodule
   469 `endif