Sun, 04 Apr 2010 20:40:03 +0100
add lm32 source
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : lm32_cpu.v
19 // Title : Top-level of CPU.
20 // Dependencies : lm32_include.v
21 //
22 // Version 3.4
23 // 1. Bug Fix: In a tight infinite loop (add, sw, bi) incoming interrupts were
24 // never serviced.
25 //
26 // Version 3.3
27 // 1. Feature: Support for memory that is tightly coupled to processor core, and
28 // has a single-cycle access latency (same as caches). Instruction port has
29 // access to a dedicated physically-mapped memory. Data port has access to
30 // a dedicated physically-mapped memory. In order to be able to manipulate
31 // values in both these memories via the debugger, these memories also
32 // interface with the data port of LM32.
33 // 2. Feature: Extended Configuration Register
34 // 3. Bug Fix: Removed port names that conflict with keywords reserved in System-
35 // Verilog.
36 //
37 // Version 3.2
38 // 1. Bug Fix: Single-stepping a load/store to invalid address causes debugger to
39 // hang. At the same time CPU fails to register data bus error exception. Bug
40 // is caused because (a) data bus error exception occurs after load/store has
41 // passed X stage and next sequential instruction (e.g., brk) is already in X
42 // stage, and (b) data bus error exception had lower priority than, say, brk
43 // exception.
44 // 2. Bug Fix: If a brk (or scall/eret/bret) sequentially follows a load/store to
45 // invalid location, CPU will fail to register data bus error exception. The
46 // solution is to stall scall/eret/bret/brk instructions in D pipeline stage
47 // until load/store has completed.
48 // 3. Feature: Enable precise identification of load/store that causes seg fault.
49 // 4. SYNC resets used for register file when implemented in EBRs.
50 //
51 // Version 3.1
52 // 1. Feature: LM32 Register File can now be mapped in to on-chip block RAM (EBR)
53 // instead of distributed memory by enabling the option in LM32 GUI.
54 // 2. Feature: LM32 also adds a static branch predictor to improve branch
55 // performance. All immediate-based forward-pointing branches are predicted
56 // not-taken. All immediate-based backward-pointing branches are predicted taken.
57 //
58 // Version 7.0SP2, 3.0
59 // No Change
60 //
61 // Version 6.1.17
62 // Initial Release
63 // =============================================================================
65 `include "lm32_include.v"
67 /////////////////////////////////////////////////////
68 // Module interface
69 /////////////////////////////////////////////////////
71 module lm32_cpu (
72 // ----- Inputs -------
73 clk_i,
74 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
75 clk_n_i,
76 `endif
77 rst_i,
78 // From external devices
79 `ifdef CFG_INTERRUPTS_ENABLED
80 interrupt_n,
81 `endif
82 // From user logic
83 `ifdef CFG_USER_ENABLED
84 user_result,
85 user_complete,
86 `endif
87 `ifdef CFG_JTAG_ENABLED
88 // From JTAG
89 jtag_clk,
90 jtag_update,
91 jtag_reg_q,
92 jtag_reg_addr_q,
93 `endif
94 `ifdef CFG_IWB_ENABLED
95 // Instruction Wishbone master
96 I_DAT_I,
97 I_ACK_I,
98 I_ERR_I,
99 I_RTY_I,
100 `endif
101 // Data Wishbone master
102 D_DAT_I,
103 D_ACK_I,
104 D_ERR_I,
105 D_RTY_I,
106 // ----- Outputs -------
107 `ifdef CFG_TRACE_ENABLED
108 trace_pc,
109 trace_pc_valid,
110 trace_exception,
111 trace_eid,
112 trace_eret,
113 `ifdef CFG_DEBUG_ENABLED
114 trace_bret,
115 `endif
116 `endif
117 `ifdef CFG_JTAG_ENABLED
118 jtag_reg_d,
119 jtag_reg_addr_d,
120 `endif
121 `ifdef CFG_USER_ENABLED
122 user_valid,
123 user_opcode,
124 user_operand_0,
125 user_operand_1,
126 `endif
127 `ifdef CFG_IWB_ENABLED
128 // Instruction Wishbone master
129 I_DAT_O,
130 I_ADR_O,
131 I_CYC_O,
132 I_SEL_O,
133 I_STB_O,
134 I_WE_O,
135 I_CTI_O,
136 I_LOCK_O,
137 I_BTE_O,
138 `endif
139 // Data Wishbone master
140 D_DAT_O,
141 D_ADR_O,
142 D_CYC_O,
143 D_SEL_O,
144 D_STB_O,
145 D_WE_O,
146 D_CTI_O,
147 D_LOCK_O,
148 D_BTE_O
149 );
151 /////////////////////////////////////////////////////
152 // Parameters
153 /////////////////////////////////////////////////////
155 parameter eba_reset = `CFG_EBA_RESET; // Reset value for EBA CSR
156 `ifdef CFG_DEBUG_ENABLED
157 parameter deba_reset = `CFG_DEBA_RESET; // Reset value for DEBA CSR
158 `endif
160 `ifdef CFG_ICACHE_ENABLED
161 parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
162 parameter icache_sets = `CFG_ICACHE_SETS; // Number of sets
163 parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of bytes per cache line
164 parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory
165 parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory
166 `else
167 parameter icache_associativity = 1;
168 parameter icache_sets = 512;
169 parameter icache_bytes_per_line = 16;
170 parameter icache_base_address = 0;
171 parameter icache_limit = 0;
172 `endif
174 `ifdef CFG_DCACHE_ENABLED
175 parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
176 parameter dcache_sets = `CFG_DCACHE_SETS; // Number of sets
177 parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of bytes per cache line
178 parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory
179 parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory
180 `else
181 parameter dcache_associativity = 1;
182 parameter dcache_sets = 512;
183 parameter dcache_bytes_per_line = 16;
184 parameter dcache_base_address = 0;
185 parameter dcache_limit = 0;
186 `endif
188 `ifdef CFG_DEBUG_ENABLED
189 parameter watchpoints = `CFG_WATCHPOINTS; // Number of h/w watchpoint CSRs
190 `else
191 parameter watchpoints = 0;
192 `endif
193 `ifdef CFG_ROM_DEBUG_ENABLED
194 parameter breakpoints = `CFG_BREAKPOINTS; // Number of h/w breakpoint CSRs
195 `else
196 parameter breakpoints = 0;
197 `endif
199 `ifdef CFG_INTERRUPTS_ENABLED
200 parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
201 `else
202 parameter interrupts = 0;
203 `endif
205 /////////////////////////////////////////////////////
206 // Inputs
207 /////////////////////////////////////////////////////
209 input clk_i; // Clock
210 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
211 input clk_n_i; // Inverted clock
212 `endif
213 input rst_i; // Reset
215 `ifdef CFG_INTERRUPTS_ENABLED
216 input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low
217 `endif
219 `ifdef CFG_USER_ENABLED
220 input [`LM32_WORD_RNG] user_result; // User-defined instruction result
221 input user_complete; // User-defined instruction execution is complete
222 `endif
224 `ifdef CFG_JTAG_ENABLED
225 input jtag_clk; // JTAG clock
226 input jtag_update; // JTAG state machine is in data register update state
227 input [`LM32_BYTE_RNG] jtag_reg_q;
228 input [2:0] jtag_reg_addr_q;
229 `endif
231 `ifdef CFG_IWB_ENABLED
232 input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
233 input I_ACK_I; // Instruction Wishbone interface acknowledgement
234 input I_ERR_I; // Instruction Wishbone interface error
235 input I_RTY_I; // Instruction Wishbone interface retry
236 `endif
238 input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
239 input D_ACK_I; // Data Wishbone interface acknowledgement
240 input D_ERR_I; // Data Wishbone interface error
241 input D_RTY_I; // Data Wishbone interface retry
243 /////////////////////////////////////////////////////
244 // Outputs
245 /////////////////////////////////////////////////////
247 `ifdef CFG_TRACE_ENABLED
248 output [`LM32_PC_RNG] trace_pc; // PC to trace
249 reg [`LM32_PC_RNG] trace_pc;
250 output trace_pc_valid; // Indicates that a new trace PC is valid
251 reg trace_pc_valid;
252 output trace_exception; // Indicates an exception has occured
253 reg trace_exception;
254 output [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
255 reg [`LM32_EID_RNG] trace_eid;
256 output trace_eret; // Indicates an eret instruction has been executed
257 reg trace_eret;
258 `ifdef CFG_DEBUG_ENABLED
259 output trace_bret; // Indicates a bret instruction has been executed
260 reg trace_bret;
261 `endif
262 `endif
264 `ifdef CFG_JTAG_ENABLED
265 output [`LM32_BYTE_RNG] jtag_reg_d;
266 wire [`LM32_BYTE_RNG] jtag_reg_d;
267 output [2:0] jtag_reg_addr_d;
268 wire [2:0] jtag_reg_addr_d;
269 `endif
271 `ifdef CFG_USER_ENABLED
272 output user_valid; // Indicates if user_opcode is valid
273 wire user_valid;
274 output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
275 reg [`LM32_USER_OPCODE_RNG] user_opcode;
276 output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
277 wire [`LM32_WORD_RNG] user_operand_0;
278 output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
279 wire [`LM32_WORD_RNG] user_operand_1;
280 `endif
282 `ifdef CFG_IWB_ENABLED
283 output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
284 wire [`LM32_WORD_RNG] I_DAT_O;
285 output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
286 wire [`LM32_WORD_RNG] I_ADR_O;
287 output I_CYC_O; // Instruction Wishbone interface cycle
288 wire I_CYC_O;
289 output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
290 wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
291 output I_STB_O; // Instruction Wishbone interface strobe
292 wire I_STB_O;
293 output I_WE_O; // Instruction Wishbone interface write enable
294 wire I_WE_O;
295 output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
296 wire [`LM32_CTYPE_RNG] I_CTI_O;
297 output I_LOCK_O; // Instruction Wishbone interface lock bus
298 wire I_LOCK_O;
299 output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
300 wire [`LM32_BTYPE_RNG] I_BTE_O;
301 `endif
303 output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
304 wire [`LM32_WORD_RNG] D_DAT_O;
305 output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
306 wire [`LM32_WORD_RNG] D_ADR_O;
307 output D_CYC_O; // Data Wishbone interface cycle
308 wire D_CYC_O;
309 output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
310 wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
311 output D_STB_O; // Data Wishbone interface strobe
312 wire D_STB_O;
313 output D_WE_O; // Data Wishbone interface write enable
314 wire D_WE_O;
315 output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
316 wire [`LM32_CTYPE_RNG] D_CTI_O;
317 output D_LOCK_O; // Date Wishbone interface lock bus
318 wire D_LOCK_O;
319 output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
320 wire [`LM32_BTYPE_RNG] D_BTE_O;
322 /////////////////////////////////////////////////////
323 // Internal nets and registers
324 /////////////////////////////////////////////////////
326 // Pipeline registers
328 `ifdef LM32_CACHE_ENABLED
329 reg valid_a; // Instruction in A stage is valid
330 `endif
331 reg valid_f; // Instruction in F stage is valid
332 reg valid_d; // Instruction in D stage is valid
333 reg valid_x; // Instruction in X stage is valid
334 reg valid_m; // Instruction in M stage is valid
335 reg valid_w; // Instruction in W stage is valid
337 wire q_x;
338 wire [`LM32_WORD_RNG] immediate_d; // Immediate operand
339 wire load_d; // Indicates a load instruction
340 reg load_x;
341 reg load_m;
342 wire load_q_x;
343 wire store_q_x;
344 wire store_d; // Indicates a store instruction
345 reg store_x;
346 reg store_m;
347 wire [`LM32_SIZE_RNG] size_d; // Size of load/store (byte, hword, word)
348 reg [`LM32_SIZE_RNG] size_x;
349 wire branch_d; // Indicates a branch instruction
350 wire branch_predict_d; // Indicates a branch is predicted
351 wire branch_predict_taken_d; // Indicates a branch is predicted taken
352 wire [`LM32_PC_RNG] branch_predict_address_d; // Address to which predicted branch jumps
353 wire [`LM32_PC_RNG] branch_target_d;
354 wire bi_unconditional;
355 wire bi_conditional;
356 reg branch_x;
357 reg branch_predict_x;
358 reg branch_predict_taken_x;
359 reg branch_m;
360 reg branch_predict_m;
361 reg branch_predict_taken_m;
362 wire branch_mispredict_taken_m; // Indicates a branch was mispredicted as taken
363 wire branch_flushX_m; // Indicates that instruction in X stage must be squashed
364 wire branch_reg_d; // Branch to register or immediate
365 wire [`LM32_PC_RNG] branch_offset_d; // Branch offset for immediate branches
366 reg [`LM32_PC_RNG] branch_target_x; // Address to branch to
367 reg [`LM32_PC_RNG] branch_target_m;
368 wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
369 wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
371 wire x_result_sel_csr_d; // Select X stage result from CSRs
372 reg x_result_sel_csr_x;
373 `ifdef LM32_MC_ARITHMETIC_ENABLED
374 wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit
375 reg x_result_sel_mc_arith_x;
376 `endif
377 `ifdef LM32_NO_BARREL_SHIFT
378 wire x_result_sel_shift_d; // Select X stage result from shifter
379 reg x_result_sel_shift_x;
380 `endif
381 `ifdef CFG_SIGN_EXTEND_ENABLED
382 wire x_result_sel_sext_d; // Select X stage result from sign-extend logic
383 reg x_result_sel_sext_x;
384 `endif
385 wire x_result_sel_logic_d; // Select X stage result from logic op unit
386 reg x_result_sel_logic_x;
387 `ifdef CFG_USER_ENABLED
388 wire x_result_sel_user_d; // Select X stage result from user-defined logic
389 reg x_result_sel_user_x;
390 `endif
391 wire x_result_sel_add_d; // Select X stage result from adder
392 reg x_result_sel_add_x;
393 wire m_result_sel_compare_d; // Select M stage result from comparison logic
394 reg m_result_sel_compare_x;
395 reg m_result_sel_compare_m;
396 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
397 wire m_result_sel_shift_d; // Select M stage result from shifter
398 reg m_result_sel_shift_x;
399 reg m_result_sel_shift_m;
400 `endif
401 wire w_result_sel_load_d; // Select W stage result from load/store unit
402 reg w_result_sel_load_x;
403 reg w_result_sel_load_m;
404 reg w_result_sel_load_w;
405 `ifdef CFG_PL_MULTIPLY_ENABLED
406 wire w_result_sel_mul_d; // Select W stage result from multiplier
407 reg w_result_sel_mul_x;
408 reg w_result_sel_mul_m;
409 reg w_result_sel_mul_w;
410 `endif
411 wire x_bypass_enable_d; // Whether result is bypassable in X stage
412 reg x_bypass_enable_x;
413 wire m_bypass_enable_d; // Whether result is bypassable in M stage
414 reg m_bypass_enable_x;
415 reg m_bypass_enable_m;
416 wire sign_extend_d; // Whether to sign-extend or zero-extend
417 reg sign_extend_x;
418 wire write_enable_d; // Register file write enable
419 reg write_enable_x;
420 wire write_enable_q_x;
421 reg write_enable_m;
422 wire write_enable_q_m;
423 reg write_enable_w;
424 wire write_enable_q_w;
425 wire read_enable_0_d; // Register file read enable 0
426 wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0
427 wire read_enable_1_d; // Register file read enable 1
428 wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1
429 wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index
430 reg [`LM32_REG_IDX_RNG] write_idx_x;
431 reg [`LM32_REG_IDX_RNG] write_idx_m;
432 reg [`LM32_REG_IDX_RNG] write_idx_w;
433 wire [`LM32_CSR_RNG] csr_d; // CSR read/write index
434 reg [`LM32_CSR_RNG] csr_x;
435 wire [`LM32_CONDITION_RNG] condition_d; // Branch condition
436 reg [`LM32_CONDITION_RNG] condition_x;
437 `ifdef CFG_DEBUG_ENABLED
438 wire break_d; // Indicates a break instruction
439 reg break_x;
440 `endif
441 wire scall_d; // Indicates a scall instruction
442 reg scall_x;
443 wire eret_d; // Indicates an eret instruction
444 reg eret_x;
445 wire eret_q_x;
446 reg eret_m;
447 `ifdef CFG_TRACE_ENABLED
448 reg eret_w;
449 `endif
450 `ifdef CFG_DEBUG_ENABLED
451 wire bret_d; // Indicates a bret instruction
452 reg bret_x;
453 wire bret_q_x;
454 reg bret_m;
455 `ifdef CFG_TRACE_ENABLED
456 reg bret_w;
457 `endif
458 `endif
459 wire csr_write_enable_d; // CSR write enable
460 reg csr_write_enable_x;
461 wire csr_write_enable_q_x;
462 `ifdef CFG_USER_ENABLED
463 wire [`LM32_USER_OPCODE_RNG] user_opcode_d; // User-defined instruction opcode
464 `endif
466 `ifdef CFG_BUS_ERRORS_ENABLED
467 wire bus_error_d; // Indicates an bus error occured while fetching the instruction in this pipeline stage
468 reg bus_error_x;
469 reg data_bus_error_exception_m;
470 reg [`LM32_PC_RNG] memop_pc_w;
471 `endif
473 reg [`LM32_WORD_RNG] d_result_0; // Result of instruction in D stage (operand 0)
474 reg [`LM32_WORD_RNG] d_result_1; // Result of instruction in D stage (operand 1)
475 reg [`LM32_WORD_RNG] x_result; // Result of instruction in X stage
476 reg [`LM32_WORD_RNG] m_result; // Result of instruction in M stage
477 reg [`LM32_WORD_RNG] w_result; // Result of instruction in W stage
479 reg [`LM32_WORD_RNG] operand_0_x; // Operand 0 for X stage instruction
480 reg [`LM32_WORD_RNG] operand_1_x; // Operand 1 for X stage instruction
481 reg [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
482 reg [`LM32_WORD_RNG] operand_m; // Operand for M stage instruction
483 reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instruction
485 // To/from register file
486 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
487 reg [`LM32_WORD_RNG] reg_data_live_0;
488 reg [`LM32_WORD_RNG] reg_data_live_1;
489 reg use_buf; // Whether to use reg_data_live or reg_data_buf
490 reg [`LM32_WORD_RNG] reg_data_buf_0;
491 reg [`LM32_WORD_RNG] reg_data_buf_1;
492 `endif
493 `ifdef LM32_EBR_REGISTER_FILE
494 `else
495 reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file
496 `endif
497 wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data
498 wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data
499 reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing
500 reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing
501 wire reg_write_enable_q_w;
503 reg interlock; // Indicates pipeline should be stalled because of a read-after-write hazzard
505 wire stall_a; // Stall instruction in A pipeline stage
506 wire stall_f; // Stall instruction in F pipeline stage
507 wire stall_d; // Stall instruction in D pipeline stage
508 wire stall_x; // Stall instruction in X pipeline stage
509 wire stall_m; // Stall instruction in M pipeline stage
511 // To/from adder
512 wire adder_op_d; // Whether to add or subtract
513 reg adder_op_x;
514 reg adder_op_x_n; // Inverted version of adder_op_x
515 wire [`LM32_WORD_RNG] adder_result_x; // Result from adder
516 wire adder_overflow_x; // Whether a signed overflow occured
517 wire adder_carry_n_x; // Whether a carry was generated
519 // To/from logical operations unit
520 wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform
521 reg [`LM32_LOGIC_OP_RNG] logic_op_x;
522 wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation
524 `ifdef CFG_SIGN_EXTEND_ENABLED
525 // From sign-extension unit
526 wire [`LM32_WORD_RNG] sextb_result_x; // Result of byte sign-extension
527 wire [`LM32_WORD_RNG] sexth_result_x; // Result of half-word sign-extenstion
528 wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension specified by instruction
529 `endif
531 // To/from shifter
532 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
533 `ifdef CFG_ROTATE_ENABLED
534 wire rotate_d; // Whether we should rotate or shift
535 reg rotate_x;
536 `endif
537 wire direction_d; // Which direction to shift in
538 reg direction_x;
539 reg direction_m;
540 wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter
541 `endif
542 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
543 wire shift_left_d; // Indicates whether to perform a left shift or not
544 wire shift_left_q_d;
545 wire shift_right_d; // Indicates whether to perform a right shift or not
546 wire shift_right_q_d;
547 `endif
548 `ifdef LM32_NO_BARREL_SHIFT
549 wire [`LM32_WORD_RNG] shifter_result_x; // Result of single-bit right shifter
550 `endif
552 // To/from multiplier
553 `ifdef LM32_MULTIPLY_ENABLED
554 wire [`LM32_WORD_RNG] multiplier_result_w; // Result from multiplier
555 `endif
556 `ifdef CFG_MC_MULTIPLY_ENABLED
557 wire multiply_d; // Indicates whether to perform a multiply or not
558 wire multiply_q_d;
559 `endif
561 // To/from divider
562 `ifdef CFG_MC_DIVIDE_ENABLED
563 wire divide_d; // Indicates whether to perform a divider or not
564 wire divide_q_d;
565 wire modulus_d;
566 wire modulus_q_d;
567 wire divide_by_zero_x; // Indicates an attempt was made to divide by zero
568 `endif
570 // To from multi-cycle arithmetic unit
571 `ifdef LM32_MC_ARITHMETIC_ENABLED
572 wire mc_stall_request_x; // Multi-cycle arithmetic unit stall request
573 wire [`LM32_WORD_RNG] mc_result_x;
574 `endif
576 // From CSRs
577 `ifdef CFG_INTERRUPTS_ENABLED
578 wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
579 `endif
580 wire [`LM32_WORD_RNG] cfg; // Configuration CSR
581 wire [`LM32_WORD_RNG] cfg2; // Extended Configuration CSR
582 `ifdef CFG_CYCLE_COUNTER_ENABLED
583 reg [`LM32_WORD_RNG] cc; // Cycle counter CSR
584 `endif
585 reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs
587 // To/from instruction unit
588 wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage
589 wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage
590 wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage
591 wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage
592 wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage
593 `ifdef CFG_TRACE_ENABLED
594 reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction
595 `endif
596 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
597 wire [`LM32_INSTRUCTION_RNG] instruction_f; // Instruction in F stage
598 `endif
599 //pragma attribute instruction_d preserve_signal true
600 //pragma attribute instruction_d preserve_driver true
601 wire [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction in D stage
602 `ifdef CFG_ICACHE_ENABLED
603 wire iflush; // Flush instruction cache
604 wire icache_stall_request; // Stall pipeline because instruction cache is busy
605 wire icache_restart_request; // Restart instruction that caused an instruction cache miss
606 wire icache_refill_request; // Request to refill instruction cache
607 wire icache_refilling; // Indicates the instruction cache is being refilled
608 `endif
609 `ifdef CFG_IROM_ENABLED
610 wire [`LM32_WORD_RNG] irom_store_data_m; // Store data to instruction ROM
611 wire [`LM32_WORD_RNG] irom_address_xm; // Address to instruction ROM from load-store unit
612 wire [`LM32_WORD_RNG] irom_data_m; // Load data from instruction ROM
613 wire irom_we_xm; // Indicates data needs to be written to instruction ROM
614 wire irom_stall_request_x; // Indicates D stage needs to be stalled on a store to instruction ROM
615 `endif
617 // To/from load/store unit
618 `ifdef CFG_DCACHE_ENABLED
619 wire dflush_x; // Flush data cache
620 reg dflush_m;
621 wire dcache_stall_request; // Stall pipeline because data cache is busy
622 wire dcache_restart_request; // Restart instruction that caused a data cache miss
623 wire dcache_refill_request; // Request to refill data cache
624 wire dcache_refilling; // Indicates the data cache is being refilled
625 `endif
626 wire [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
627 wire stall_wb_load; // Stall pipeline because of a load via the data Wishbone interface
629 // To/from JTAG interface
630 `ifdef CFG_JTAG_ENABLED
631 `ifdef CFG_JTAG_UART_ENABLED
632 wire [`LM32_WORD_RNG] jtx_csr_read_data; // Read data for JTX CSR
633 wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR
634 `endif
635 `ifdef CFG_HW_DEBUG_ENABLED
636 wire jtag_csr_write_enable; // Debugger CSR write enable
637 wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
638 wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
639 wire jtag_read_enable;
640 wire [`LM32_BYTE_RNG] jtag_read_data;
641 wire jtag_write_enable;
642 wire [`LM32_BYTE_RNG] jtag_write_data;
643 wire [`LM32_WORD_RNG] jtag_address;
644 wire jtag_access_complete;
645 `endif
646 `ifdef CFG_DEBUG_ENABLED
647 wire jtag_break; // Request from debugger to raise a breakpoint
648 `endif
649 `endif
651 // Hazzard detection
652 wire raw_x_0; // RAW hazzard between instruction in X stage and read port 0
653 wire raw_x_1; // RAW hazzard between instruction in X stage and read port 1
654 wire raw_m_0; // RAW hazzard between instruction in M stage and read port 0
655 wire raw_m_1; // RAW hazzard between instruction in M stage and read port 1
656 wire raw_w_0; // RAW hazzard between instruction in W stage and read port 0
657 wire raw_w_1; // RAW hazzard between instruction in W stage and read port 1
659 // Control flow
660 wire cmp_zero; // Result of comparison is zero
661 wire cmp_negative; // Result of comparison is negative
662 wire cmp_overflow; // Comparison produced an overflow
663 wire cmp_carry_n; // Comparison produced a carry, inverted
664 reg condition_met_x; // Condition of branch instruction is met
665 reg condition_met_m;
666 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
667 wire branch_taken_x; // Branch is taken in X stage
668 `endif
669 wire branch_taken_m; // Branch is taken in M stage
671 wire kill_f; // Kill instruction in F stage
672 wire kill_d; // Kill instruction in D stage
673 wire kill_x; // Kill instruction in X stage
674 wire kill_m; // Kill instruction in M stage
675 wire kill_w; // Kill instruction in W stage
677 reg [`LM32_PC_WIDTH+2-1:8] eba; // Exception Base Address (EBA) CSR
678 `ifdef CFG_DEBUG_ENABLED
679 reg [`LM32_PC_WIDTH+2-1:8] deba; // Debug Exception Base Address (DEBA) CSR
680 `endif
681 reg [`LM32_EID_RNG] eid_x; // Exception ID in X stage
682 `ifdef CFG_TRACE_ENABLED
683 reg [`LM32_EID_RNG] eid_m; // Exception ID in M stage
684 reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage
685 `endif
687 `ifdef CFG_DEBUG_ENABLED
688 `ifdef LM32_SINGLE_STEP_ENABLED
689 wire dc_ss; // Is single-step enabled
690 `endif
691 wire dc_re; // Remap all exceptions
692 wire exception_x; // An exception occured in the X stage
693 reg exception_m; // An instruction that caused an exception is in the M stage
694 wire debug_exception_x; // Indicates if a debug exception has occured
695 reg debug_exception_m;
696 reg debug_exception_w;
697 wire debug_exception_q_w;
698 wire non_debug_exception_x; // Indicates if a non debug exception has occured
699 reg non_debug_exception_m;
700 reg non_debug_exception_w;
701 wire non_debug_exception_q_w;
702 `else
703 wire exception_x; // Indicates if a debug exception has occured
704 reg exception_m;
705 reg exception_w;
706 wire exception_q_w;
707 `endif
709 `ifdef CFG_DEBUG_ENABLED
710 `ifdef CFG_JTAG_ENABLED
711 wire reset_exception; // Indicates if a reset exception has occured
712 `endif
713 `endif
714 `ifdef CFG_INTERRUPTS_ENABLED
715 wire interrupt_exception; // Indicates if an interrupt exception has occured
716 `endif
717 `ifdef CFG_DEBUG_ENABLED
718 wire breakpoint_exception; // Indicates if a breakpoint exception has occured
719 wire watchpoint_exception; // Indicates if a watchpoint exception has occured
720 `endif
721 `ifdef CFG_BUS_ERRORS_ENABLED
722 wire instruction_bus_error_exception; // Indicates if an instruction bus error exception has occured
723 wire data_bus_error_exception; // Indicates if a data bus error exception has occured
724 `endif
725 `ifdef CFG_MC_DIVIDE_ENABLED
726 wire divide_by_zero_exception; // Indicates if a divide by zero exception has occured
727 `endif
728 wire system_call_exception; // Indicates if a system call exception has occured
730 `ifdef CFG_BUS_ERRORS_ENABLED
731 reg data_bus_error_seen; // Indicates if a data bus error was seen
732 `endif
734 /////////////////////////////////////////////////////
735 // Functions
736 /////////////////////////////////////////////////////
738 `include "lm32_functions.v"
740 /////////////////////////////////////////////////////
741 // Instantiations
742 /////////////////////////////////////////////////////
744 // Instruction unit
745 lm32_instruction_unit #(
746 .associativity (icache_associativity),
747 .sets (icache_sets),
748 .bytes_per_line (icache_bytes_per_line),
749 .base_address (icache_base_address),
750 .limit (icache_limit)
751 ) instruction_unit (
752 // ----- Inputs -------
753 .clk_i (clk_i),
754 .rst_i (rst_i),
755 // From pipeline
756 .stall_a (stall_a),
757 .stall_f (stall_f),
758 .stall_d (stall_d),
759 .stall_x (stall_x),
760 .stall_m (stall_m),
761 .valid_f (valid_f),
762 .valid_d (valid_d),
763 .kill_f (kill_f),
764 .branch_predict_taken_d (branch_predict_taken_d),
765 .branch_predict_address_d (branch_predict_address_d),
766 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
767 .branch_taken_x (branch_taken_x),
768 .branch_target_x (branch_target_x),
769 `endif
770 .exception_m (exception_m),
771 .branch_taken_m (branch_taken_m),
772 .branch_mispredict_taken_m (branch_mispredict_taken_m),
773 .branch_target_m (branch_target_m),
774 `ifdef CFG_ICACHE_ENABLED
775 .iflush (iflush),
776 `endif
777 `ifdef CFG_IROM_ENABLED
778 .irom_store_data_m (irom_store_data_m),
779 .irom_address_xm (irom_address_xm),
780 .irom_we_xm (irom_we_xm),
781 `endif
782 `ifdef CFG_DCACHE_ENABLED
783 .dcache_restart_request (dcache_restart_request),
784 .dcache_refill_request (dcache_refill_request),
785 .dcache_refilling (dcache_refilling),
786 `endif
787 `ifdef CFG_IWB_ENABLED
788 // From Wishbone
789 .i_dat_i (I_DAT_I),
790 .i_ack_i (I_ACK_I),
791 .i_err_i (I_ERR_I),
792 .i_rty_i (I_RTY_I),
793 `endif
794 `ifdef CFG_HW_DEBUG_ENABLED
795 .jtag_read_enable (jtag_read_enable),
796 .jtag_write_enable (jtag_write_enable),
797 .jtag_write_data (jtag_write_data),
798 .jtag_address (jtag_address),
799 `endif
800 // ----- Outputs -------
801 // To pipeline
802 .pc_f (pc_f),
803 .pc_d (pc_d),
804 .pc_x (pc_x),
805 .pc_m (pc_m),
806 .pc_w (pc_w),
807 `ifdef CFG_ICACHE_ENABLED
808 .icache_stall_request (icache_stall_request),
809 .icache_restart_request (icache_restart_request),
810 .icache_refill_request (icache_refill_request),
811 .icache_refilling (icache_refilling),
812 `endif
813 `ifdef CFG_IROM_ENABLED
814 .irom_data_m (irom_data_m),
815 `endif
816 `ifdef CFG_IWB_ENABLED
817 // To Wishbone
818 .i_dat_o (I_DAT_O),
819 .i_adr_o (I_ADR_O),
820 .i_cyc_o (I_CYC_O),
821 .i_sel_o (I_SEL_O),
822 .i_stb_o (I_STB_O),
823 .i_we_o (I_WE_O),
824 .i_cti_o (I_CTI_O),
825 .i_lock_o (I_LOCK_O),
826 .i_bte_o (I_BTE_O),
827 `endif
828 `ifdef CFG_HW_DEBUG_ENABLED
829 .jtag_read_data (jtag_read_data),
830 .jtag_access_complete (jtag_access_complete),
831 `endif
832 `ifdef CFG_BUS_ERRORS_ENABLED
833 .bus_error_d (bus_error_d),
834 `endif
835 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
836 .instruction_f (instruction_f),
837 `endif
838 .instruction_d (instruction_d)
839 );
841 // Instruction decoder
842 lm32_decoder decoder (
843 // ----- Inputs -------
844 .instruction (instruction_d),
845 // ----- Outputs -------
846 .d_result_sel_0 (d_result_sel_0_d),
847 .d_result_sel_1 (d_result_sel_1_d),
848 .x_result_sel_csr (x_result_sel_csr_d),
849 `ifdef LM32_MC_ARITHMETIC_ENABLED
850 .x_result_sel_mc_arith (x_result_sel_mc_arith_d),
851 `endif
852 `ifdef LM32_NO_BARREL_SHIFT
853 .x_result_sel_shift (x_result_sel_shift_d),
854 `endif
855 `ifdef CFG_SIGN_EXTEND_ENABLED
856 .x_result_sel_sext (x_result_sel_sext_d),
857 `endif
858 .x_result_sel_logic (x_result_sel_logic_d),
859 `ifdef CFG_USER_ENABLED
860 .x_result_sel_user (x_result_sel_user_d),
861 `endif
862 .x_result_sel_add (x_result_sel_add_d),
863 .m_result_sel_compare (m_result_sel_compare_d),
864 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
865 .m_result_sel_shift (m_result_sel_shift_d),
866 `endif
867 .w_result_sel_load (w_result_sel_load_d),
868 `ifdef CFG_PL_MULTIPLY_ENABLED
869 .w_result_sel_mul (w_result_sel_mul_d),
870 `endif
871 .x_bypass_enable (x_bypass_enable_d),
872 .m_bypass_enable (m_bypass_enable_d),
873 .read_enable_0 (read_enable_0_d),
874 .read_idx_0 (read_idx_0_d),
875 .read_enable_1 (read_enable_1_d),
876 .read_idx_1 (read_idx_1_d),
877 .write_enable (write_enable_d),
878 .write_idx (write_idx_d),
879 .immediate (immediate_d),
880 .branch_offset (branch_offset_d),
881 .load (load_d),
882 .store (store_d),
883 .size (size_d),
884 .sign_extend (sign_extend_d),
885 .adder_op (adder_op_d),
886 .logic_op (logic_op_d),
887 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
888 .direction (direction_d),
889 `endif
890 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
891 .shift_left (shift_left_d),
892 .shift_right (shift_right_d),
893 `endif
894 `ifdef CFG_MC_MULTIPLY_ENABLED
895 .multiply (multiply_d),
896 `endif
897 `ifdef CFG_MC_DIVIDE_ENABLED
898 .divide (divide_d),
899 .modulus (modulus_d),
900 `endif
901 .branch (branch_d),
902 .bi_unconditional (bi_unconditional),
903 .bi_conditional (bi_conditional),
904 .branch_reg (branch_reg_d),
905 .condition (condition_d),
906 `ifdef CFG_DEBUG_ENABLED
907 .break_opcode (break_d),
908 `endif
909 .scall (scall_d),
910 .eret (eret_d),
911 `ifdef CFG_DEBUG_ENABLED
912 .bret (bret_d),
913 `endif
914 `ifdef CFG_USER_ENABLED
915 .user_opcode (user_opcode_d),
916 `endif
917 .csr_write_enable (csr_write_enable_d)
918 );
920 // Load/store unit
921 lm32_load_store_unit #(
922 .associativity (dcache_associativity),
923 .sets (dcache_sets),
924 .bytes_per_line (dcache_bytes_per_line),
925 .base_address (dcache_base_address),
926 .limit (dcache_limit)
927 ) load_store_unit (
928 // ----- Inputs -------
929 .clk_i (clk_i),
930 .rst_i (rst_i),
931 // From pipeline
932 .stall_a (stall_a),
933 .stall_x (stall_x),
934 .stall_m (stall_m),
935 .kill_x (kill_x),
936 .kill_m (kill_m),
937 .exception_m (exception_m),
938 .store_operand_x (store_operand_x),
939 .load_store_address_x (adder_result_x),
940 .load_store_address_m (operand_m),
941 .load_store_address_w (operand_w[1:0]),
942 .load_x (load_x),
943 .store_x (store_x),
944 .load_q_x (load_q_x),
945 .store_q_x (store_q_x),
946 .load_q_m (load_q_m),
947 .store_q_m (store_q_m),
948 .sign_extend_x (sign_extend_x),
949 .size_x (size_x),
950 `ifdef CFG_DCACHE_ENABLED
951 .dflush (dflush_m),
952 `endif
953 `ifdef CFG_IROM_ENABLED
954 .irom_data_m (irom_data_m),
955 `endif
956 // From Wishbone
957 .d_dat_i (D_DAT_I),
958 .d_ack_i (D_ACK_I),
959 .d_err_i (D_ERR_I),
960 .d_rty_i (D_RTY_I),
961 // ----- Outputs -------
962 // To pipeline
963 `ifdef CFG_DCACHE_ENABLED
964 .dcache_refill_request (dcache_refill_request),
965 .dcache_restart_request (dcache_restart_request),
966 .dcache_stall_request (dcache_stall_request),
967 .dcache_refilling (dcache_refilling),
968 `endif
969 `ifdef CFG_IROM_ENABLED
970 .irom_store_data_m (irom_store_data_m),
971 .irom_address_xm (irom_address_xm),
972 .irom_we_xm (irom_we_xm),
973 .irom_stall_request_x (irom_stall_request_x),
974 `endif
975 .load_data_w (load_data_w),
976 .stall_wb_load (stall_wb_load),
977 // To Wishbone
978 .d_dat_o (D_DAT_O),
979 .d_adr_o (D_ADR_O),
980 .d_cyc_o (D_CYC_O),
981 .d_sel_o (D_SEL_O),
982 .d_stb_o (D_STB_O),
983 .d_we_o (D_WE_O),
984 .d_cti_o (D_CTI_O),
985 .d_lock_o (D_LOCK_O),
986 .d_bte_o (D_BTE_O)
987 );
989 // Adder
990 lm32_adder adder (
991 // ----- Inputs -------
992 .adder_op_x (adder_op_x),
993 .adder_op_x_n (adder_op_x_n),
994 .operand_0_x (operand_0_x),
995 .operand_1_x (operand_1_x),
996 // ----- Outputs -------
997 .adder_result_x (adder_result_x),
998 .adder_carry_n_x (adder_carry_n_x),
999 .adder_overflow_x (adder_overflow_x)
1000 );
1002 // Logic operations
1003 lm32_logic_op logic_op (
1004 // ----- Inputs -------
1005 .logic_op_x (logic_op_x),
1006 .operand_0_x (operand_0_x),
1008 .operand_1_x (operand_1_x),
1009 // ----- Outputs -------
1010 .logic_result_x (logic_result_x)
1011 );
1013 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
1014 // Pipelined barrel-shifter
1015 lm32_shifter shifter (
1016 // ----- Inputs -------
1017 .clk_i (clk_i),
1018 .rst_i (rst_i),
1019 .stall_x (stall_x),
1020 .direction_x (direction_x),
1021 .sign_extend_x (sign_extend_x),
1022 .operand_0_x (operand_0_x),
1023 .operand_1_x (operand_1_x),
1024 // ----- Outputs -------
1025 .shifter_result_m (shifter_result_m)
1026 );
1027 `endif
1029 `ifdef CFG_PL_MULTIPLY_ENABLED
1030 // Pipeline fixed-point multiplier
1031 lm32_multiplier multiplier (
1032 // ----- Inputs -------
1033 .clk_i (clk_i),
1034 .rst_i (rst_i),
1035 .stall_x (stall_x),
1036 .stall_m (stall_m),
1037 .operand_0 (d_result_0),
1038 .operand_1 (d_result_1),
1039 // ----- Outputs -------
1040 .result (multiplier_result_w)
1041 );
1042 `endif
1044 `ifdef LM32_MC_ARITHMETIC_ENABLED
1045 // Multi-cycle arithmetic
1046 lm32_mc_arithmetic mc_arithmetic (
1047 // ----- Inputs -------
1048 .clk_i (clk_i),
1049 .rst_i (rst_i),
1050 .stall_d (stall_d),
1051 .kill_x (kill_x),
1052 `ifdef CFG_MC_DIVIDE_ENABLED
1053 .divide_d (divide_q_d),
1054 .modulus_d (modulus_q_d),
1055 `endif
1056 `ifdef CFG_MC_MULTIPLY_ENABLED
1057 .multiply_d (multiply_q_d),
1058 `endif
1059 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
1060 .shift_left_d (shift_left_q_d),
1061 .shift_right_d (shift_right_q_d),
1062 .sign_extend_d (sign_extend_d),
1063 `endif
1064 .operand_0_d (d_result_0),
1065 .operand_1_d (d_result_1),
1066 // ----- Outputs -------
1067 .result_x (mc_result_x),
1068 `ifdef CFG_MC_DIVIDE_ENABLED
1069 .divide_by_zero_x (divide_by_zero_x),
1070 `endif
1071 .stall_request_x (mc_stall_request_x)
1072 );
1073 `endif
1075 `ifdef CFG_INTERRUPTS_ENABLED
1076 // Interrupt unit
1077 lm32_interrupt interrupt (
1078 // ----- Inputs -------
1079 .clk_i (clk_i),
1080 .rst_i (rst_i),
1081 // From external devices
1082 .interrupt_n (interrupt_n),
1083 // From pipeline
1084 .stall_x (stall_x),
1085 `ifdef CFG_DEBUG_ENABLED
1086 .non_debug_exception (non_debug_exception_q_w),
1087 .debug_exception (debug_exception_q_w),
1088 `else
1089 .exception (exception_q_w),
1090 `endif
1091 .eret_q_x (eret_q_x),
1092 `ifdef CFG_DEBUG_ENABLED
1093 .bret_q_x (bret_q_x),
1094 `endif
1095 .csr (csr_x),
1096 .csr_write_data (operand_1_x),
1097 .csr_write_enable (csr_write_enable_q_x),
1098 // ----- Outputs -------
1099 .interrupt_exception (interrupt_exception),
1100 // To pipeline
1101 .csr_read_data (interrupt_csr_read_data_x)
1102 );
1103 `endif
1105 `ifdef CFG_JTAG_ENABLED
1106 // JTAG interface
1107 lm32_jtag jtag (
1108 // ----- Inputs -------
1109 .clk_i (clk_i),
1110 .rst_i (rst_i),
1111 // From JTAG
1112 .jtag_clk (jtag_clk),
1113 .jtag_update (jtag_update),
1114 .jtag_reg_q (jtag_reg_q),
1115 .jtag_reg_addr_q (jtag_reg_addr_q),
1116 // From pipeline
1117 `ifdef CFG_JTAG_UART_ENABLED
1118 .csr (csr_x),
1119 .csr_write_data (operand_1_x),
1120 .csr_write_enable (csr_write_enable_q_x),
1121 .stall_x (stall_x),
1122 `endif
1123 `ifdef CFG_HW_DEBUG_ENABLED
1124 .jtag_read_data (jtag_read_data),
1125 .jtag_access_complete (jtag_access_complete),
1126 `endif
1127 `ifdef CFG_DEBUG_ENABLED
1128 .exception_q_w (debug_exception_q_w || non_debug_exception_q_w),
1129 `endif
1130 // ----- Outputs -------
1131 // To pipeline
1132 `ifdef CFG_JTAG_UART_ENABLED
1133 .jtx_csr_read_data (jtx_csr_read_data),
1134 .jrx_csr_read_data (jrx_csr_read_data),
1135 `endif
1136 `ifdef CFG_HW_DEBUG_ENABLED
1137 .jtag_csr_write_enable (jtag_csr_write_enable),
1138 .jtag_csr_write_data (jtag_csr_write_data),
1139 .jtag_csr (jtag_csr),
1140 .jtag_read_enable (jtag_read_enable),
1141 .jtag_write_enable (jtag_write_enable),
1142 .jtag_write_data (jtag_write_data),
1143 .jtag_address (jtag_address),
1144 `endif
1145 `ifdef CFG_DEBUG_ENABLED
1146 .jtag_break (jtag_break),
1147 .jtag_reset (reset_exception),
1148 `endif
1149 // To JTAG
1150 .jtag_reg_d (jtag_reg_d),
1151 .jtag_reg_addr_d (jtag_reg_addr_d)
1152 );
1153 `endif
1155 `ifdef CFG_DEBUG_ENABLED
1156 // Debug unit
1157 lm32_debug #(
1158 .breakpoints (breakpoints),
1159 .watchpoints (watchpoints)
1160 ) hw_debug (
1161 // ----- Inputs -------
1162 .clk_i (clk_i),
1163 .rst_i (rst_i),
1164 .pc_x (pc_x),
1165 .load_x (load_x),
1166 .store_x (store_x),
1167 .load_store_address_x (adder_result_x),
1168 .csr_write_enable_x (csr_write_enable_q_x),
1169 .csr_write_data (operand_1_x),
1170 .csr_x (csr_x),
1171 `ifdef CFG_HW_DEBUG_ENABLED
1172 .jtag_csr_write_enable (jtag_csr_write_enable),
1173 .jtag_csr_write_data (jtag_csr_write_data),
1174 .jtag_csr (jtag_csr),
1175 `endif
1176 `ifdef LM32_SINGLE_STEP_ENABLED
1177 .eret_q_x (eret_q_x),
1178 .bret_q_x (bret_q_x),
1179 .stall_x (stall_x),
1180 .exception_x (exception_x),
1181 .q_x (q_x),
1182 `ifdef CFG_DCACHE_ENABLED
1183 .dcache_refill_request (dcache_refill_request),
1184 `endif
1185 `endif
1186 // ----- Outputs -------
1187 `ifdef LM32_SINGLE_STEP_ENABLED
1188 .dc_ss (dc_ss),
1189 `endif
1190 .dc_re (dc_re),
1191 .bp_match (bp_match),
1192 .wp_match (wp_match)
1193 );
1194 `endif
1196 // Register file
1198 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1199 /*----------------------------------------------------------------------
1200 Register File is implemented using EBRs. There can be three accesses to
1201 the register file in each cycle: two reads and one write. On-chip block
1202 RAM has two read/write ports. To accomodate three accesses, two on-chip
1203 block RAMs are used (each register file "write" is made to both block
1204 RAMs).
1206 One limitation of the on-chip block RAMs is that one cannot perform a
1207 read and write to same location in a cycle (if this is done, then the
1208 data read out is indeterminate).
1209 ----------------------------------------------------------------------*/
1210 wire [31:0] regfile_data_0, regfile_data_1;
1211 reg [31:0] w_result_d;
1212 reg regfile_raw_0, regfile_raw_0_nxt;
1213 reg regfile_raw_1, regfile_raw_1_nxt;
1215 /*----------------------------------------------------------------------
1216 Check if read and write is being performed to same register in current
1217 cycle? This is done by comparing the read and write IDXs.
1218 ----------------------------------------------------------------------*/
1219 always @(reg_write_enable_q_w or write_idx_w or instruction_f)
1220 begin
1221 if (reg_write_enable_q_w
1222 && (write_idx_w == instruction_f[25:21]))
1223 regfile_raw_0_nxt = 1'b1;
1224 else
1225 regfile_raw_0_nxt = 1'b0;
1227 if (reg_write_enable_q_w
1228 && (write_idx_w == instruction_f[20:16]))
1229 regfile_raw_1_nxt = 1'b1;
1230 else
1231 regfile_raw_1_nxt = 1'b0;
1232 end
1234 /*----------------------------------------------------------------------
1235 Select latched (delayed) write value or data from register file. If
1236 read in previous cycle was performed to register written to in same
1237 cycle, then latched (delayed) write value is selected.
1238 ----------------------------------------------------------------------*/
1239 always @(regfile_raw_0 or w_result_d or regfile_data_0)
1240 if (regfile_raw_0)
1241 reg_data_live_0 = w_result_d;
1242 else
1243 reg_data_live_0 = regfile_data_0;
1245 /*----------------------------------------------------------------------
1246 Select latched (delayed) write value or data from register file. If
1247 read in previous cycle was performed to register written to in same
1248 cycle, then latched (delayed) write value is selected.
1249 ----------------------------------------------------------------------*/
1250 always @(regfile_raw_1 or w_result_d or regfile_data_1)
1251 if (regfile_raw_1)
1252 reg_data_live_1 = w_result_d;
1253 else
1254 reg_data_live_1 = regfile_data_1;
1256 /*----------------------------------------------------------------------
1257 Latch value written to register file
1258 ----------------------------------------------------------------------*/
1259 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1260 if (rst_i == `TRUE)
1261 begin
1262 regfile_raw_0 <= 1'b0;
1263 regfile_raw_1 <= 1'b0;
1264 w_result_d <= 32'b0;
1265 end
1266 else
1267 begin
1268 regfile_raw_0 <= regfile_raw_0_nxt;
1269 regfile_raw_1 <= regfile_raw_1_nxt;
1270 w_result_d <= w_result;
1271 end
1273 /*----------------------------------------------------------------------
1274 Register file instantiation as Pseudo-Dual Port EBRs.
1275 ----------------------------------------------------------------------*/
1276 pmi_ram_dp
1277 #(
1278 // ----- Parameters -----
1279 .pmi_wr_addr_depth(1<<5),
1280 .pmi_wr_addr_width(5),
1281 .pmi_wr_data_width(32),
1282 .pmi_rd_addr_depth(1<<5),
1283 .pmi_rd_addr_width(5),
1284 .pmi_rd_data_width(32),
1285 .pmi_regmode("noreg"),
1286 .pmi_gsr("enable"),
1287 .pmi_resetmode("sync"),
1288 .pmi_init_file("none"),
1289 .pmi_init_file_format("binary"),
1290 .pmi_family(`LATTICE_FAMILY),
1291 .module_type("pmi_ram_dp")
1292 )
1293 reg_0
1294 (
1295 // ----- Inputs -----
1296 .Data(w_result),
1297 .WrAddress(write_idx_w),
1298 .RdAddress(instruction_f[25:21]),
1299 .WrClock(clk_i),
1300 .RdClock(clk_i),
1301 .WrClockEn(`TRUE),
1302 .RdClockEn(`TRUE),
1303 .WE(reg_write_enable_q_w),
1304 .Reset(rst_i),
1305 // ----- Outputs -----
1306 .Q(regfile_data_0)
1307 );
1309 pmi_ram_dp
1310 #(
1311 // ----- Parameters -----
1312 .pmi_wr_addr_depth(1<<5),
1313 .pmi_wr_addr_width(5),
1314 .pmi_wr_data_width(32),
1315 .pmi_rd_addr_depth(1<<5),
1316 .pmi_rd_addr_width(5),
1317 .pmi_rd_data_width(32),
1318 .pmi_regmode("noreg"),
1319 .pmi_gsr("enable"),
1320 .pmi_resetmode("sync"),
1321 .pmi_init_file("none"),
1322 .pmi_init_file_format("binary"),
1323 .pmi_family(`LATTICE_FAMILY),
1324 .module_type("pmi_ram_dp")
1325 )
1326 reg_1
1327 (
1328 // ----- Inputs -----
1329 .Data(w_result),
1330 .WrAddress(write_idx_w),
1331 .RdAddress(instruction_f[20:16]),
1332 .WrClock(clk_i),
1333 .RdClock(clk_i),
1334 .WrClockEn(`TRUE),
1335 .RdClockEn(`TRUE),
1336 .WE(reg_write_enable_q_w),
1337 .Reset(rst_i),
1338 // ----- Outputs -----
1339 .Q(regfile_data_1)
1340 );
1341 `endif
1343 `ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
1344 pmi_ram_dp
1345 #(
1346 // ----- Parameters -----
1347 .pmi_wr_addr_depth(1<<5),
1348 .pmi_wr_addr_width(5),
1349 .pmi_wr_data_width(32),
1350 .pmi_rd_addr_depth(1<<5),
1351 .pmi_rd_addr_width(5),
1352 .pmi_rd_data_width(32),
1353 .pmi_regmode("noreg"),
1354 .pmi_gsr("enable"),
1355 .pmi_resetmode("sync"),
1356 .pmi_init_file("none"),
1357 .pmi_init_file_format("binary"),
1358 .pmi_family(`LATTICE_FAMILY),
1359 .module_type("pmi_ram_dp")
1360 )
1361 reg_0
1362 (
1363 // ----- Inputs -----
1364 .Data(w_result),
1365 .WrAddress(write_idx_w),
1366 .RdAddress(read_idx_0_d),
1367 .WrClock(clk_i),
1368 .RdClock(clk_n_i),
1369 .WrClockEn(`TRUE),
1370 .RdClockEn(stall_f == `FALSE),
1371 .WE(reg_write_enable_q_w),
1372 .Reset(rst_i),
1373 // ----- Outputs -----
1374 .Q(reg_data_0)
1375 );
1377 pmi_ram_dp
1378 #(
1379 // ----- Parameters -----
1380 .pmi_wr_addr_depth(1<<5),
1381 .pmi_wr_addr_width(5),
1382 .pmi_wr_data_width(32),
1383 .pmi_rd_addr_depth(1<<5),
1384 .pmi_rd_addr_width(5),
1385 .pmi_rd_data_width(32),
1386 .pmi_regmode("noreg"),
1387 .pmi_gsr("enable"),
1388 .pmi_resetmode("sync"),
1389 .pmi_init_file("none"),
1390 .pmi_init_file_format("binary"),
1391 .pmi_family(`LATTICE_FAMILY),
1392 .module_type("pmi_ram_dp")
1393 )
1394 reg_1
1395 (
1396 // ----- Inputs -----
1397 .Data(w_result),
1398 .WrAddress(write_idx_w),
1399 .RdAddress(read_idx_1_d),
1400 .WrClock(clk_i),
1401 .RdClock(clk_n_i),
1402 .WrClockEn(`TRUE),
1403 .RdClockEn(stall_f == `FALSE),
1404 .WE(reg_write_enable_q_w),
1405 .Reset(rst_i),
1406 // ----- Outputs -----
1407 .Q(reg_data_1)
1408 );
1409 `endif
1412 /////////////////////////////////////////////////////
1413 // Combinational Logic
1414 /////////////////////////////////////////////////////
1416 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1417 // Select between buffered and live data from register file
1418 assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
1419 assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
1420 `endif
1421 `ifdef LM32_EBR_REGISTER_FILE
1422 `else
1423 // Register file read ports
1424 assign reg_data_0 = registers[read_idx_0_d];
1425 assign reg_data_1 = registers[read_idx_1_d];
1426 `endif
1428 // Detect read-after-write hazzards
1429 assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
1430 assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
1431 assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
1432 assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
1433 assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
1434 assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
1436 // Interlock detection - Raise an interlock for RAW hazzards
1437 always @(*)
1438 begin
1439 if ( ( (x_bypass_enable_x == `FALSE)
1440 && ( ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
1441 || ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
1442 )
1443 )
1444 || ( (m_bypass_enable_m == `FALSE)
1445 && ( ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
1446 || ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
1447 )
1448 )
1449 )
1450 interlock = `TRUE;
1451 else
1452 interlock = `FALSE;
1453 end
1455 // Bypass for reg port 0
1456 always @(*)
1457 begin
1458 if (raw_x_0 == `TRUE)
1459 bypass_data_0 = x_result;
1460 else if (raw_m_0 == `TRUE)
1461 bypass_data_0 = m_result;
1462 else if (raw_w_0 == `TRUE)
1463 bypass_data_0 = w_result;
1464 else
1465 bypass_data_0 = reg_data_0;
1466 end
1468 // Bypass for reg port 1
1469 always @(*)
1470 begin
1471 if (raw_x_1 == `TRUE)
1472 bypass_data_1 = x_result;
1473 else if (raw_m_1 == `TRUE)
1474 bypass_data_1 = m_result;
1475 else if (raw_w_1 == `TRUE)
1476 bypass_data_1 = w_result;
1477 else
1478 bypass_data_1 = reg_data_1;
1479 end
1481 /*----------------------------------------------------------------------
1482 Branch prediction is performed in D stage of pipeline. Only PC-relative
1483 branches are predicted: forward-pointing conditional branches are not-
1484 taken, while backward-pointing conditional branches are taken.
1485 Unconditional branches are always predicted taken!
1486 ----------------------------------------------------------------------*/
1487 assign branch_predict_d = bi_unconditional | bi_conditional;
1488 assign branch_predict_taken_d = bi_unconditional ? 1'b1 : (bi_conditional ? instruction_d[15] : 1'b0);
1490 // Compute branch target address: Branch PC PLUS Offset
1491 assign branch_target_d = pc_d + branch_offset_d;
1493 // Compute fetch address. Address of instruction sequentially after the
1494 // branch if branch is not taken. Target address of branch is branch is
1495 // taken
1496 assign branch_predict_address_d = branch_predict_taken_d ? branch_target_d : pc_f;
1498 // D stage result selection
1499 always @(*)
1500 begin
1501 d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
1502 case (d_result_sel_1_d)
1503 `LM32_D_RESULT_SEL_1_ZERO: d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
1504 `LM32_D_RESULT_SEL_1_REG_1: d_result_1 = bypass_data_1;
1505 `LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
1506 default: d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
1507 endcase
1508 end
1510 `ifdef CFG_USER_ENABLED
1511 // Operands for user-defined instructions
1512 assign user_operand_0 = operand_0_x;
1513 assign user_operand_1 = operand_1_x;
1514 `endif
1516 `ifdef CFG_SIGN_EXTEND_ENABLED
1517 // Sign-extension
1518 assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
1519 assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
1520 assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
1521 `endif
1523 `ifdef LM32_NO_BARREL_SHIFT
1524 // Only single bit shift operations are supported when barrel-shifter isn't implemented
1525 assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
1526 `endif
1528 // Condition evaluation
1529 assign cmp_zero = operand_0_x == operand_1_x;
1530 assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
1531 assign cmp_overflow = adder_overflow_x;
1532 assign cmp_carry_n = adder_carry_n_x;
1533 always @(*)
1534 begin
1535 case (condition_x)
1536 `LM32_CONDITION_U1: condition_met_x = `TRUE;
1537 `LM32_CONDITION_U2: condition_met_x = `TRUE;
1538 `LM32_CONDITION_E: condition_met_x = cmp_zero;
1539 `LM32_CONDITION_NE: condition_met_x = !cmp_zero;
1540 `LM32_CONDITION_G: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
1541 `LM32_CONDITION_GU: condition_met_x = cmp_carry_n && !cmp_zero;
1542 `LM32_CONDITION_GE: condition_met_x = cmp_negative == cmp_overflow;
1543 `LM32_CONDITION_GEU: condition_met_x = cmp_carry_n;
1544 default: condition_met_x = 1'bx;
1545 endcase
1546 end
1548 // X stage result selection
1549 always @(*)
1550 begin
1551 x_result = x_result_sel_add_x ? adder_result_x
1552 : x_result_sel_csr_x ? csr_read_data_x
1553 `ifdef CFG_SIGN_EXTEND_ENABLED
1554 : x_result_sel_sext_x ? sext_result_x
1555 `endif
1556 `ifdef CFG_USER_ENABLED
1557 : x_result_sel_user_x ? user_result
1558 `endif
1559 `ifdef LM32_NO_BARREL_SHIFT
1560 : x_result_sel_shift_x ? shifter_result_x
1561 `endif
1562 `ifdef LM32_MC_ARITHMETIC_ENABLED
1563 : x_result_sel_mc_arith_x ? mc_result_x
1564 `endif
1565 : logic_result_x;
1566 end
1568 // M stage result selection
1569 always @(*)
1570 begin
1571 m_result = m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
1572 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
1573 : m_result_sel_shift_m ? shifter_result_m
1574 `endif
1575 : operand_m;
1576 end
1578 // W stage result selection
1579 always @(*)
1580 begin
1581 w_result = w_result_sel_load_w ? load_data_w
1582 `ifdef CFG_PL_MULTIPLY_ENABLED
1583 : w_result_sel_mul_w ? multiplier_result_w
1584 `endif
1585 : operand_w;
1586 end
1588 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1589 // Indicate when a branch should be taken in X stage
1590 assign branch_taken_x = (stall_x == `FALSE)
1591 && ( (branch_x == `TRUE)
1592 && ((condition_x == `LM32_CONDITION_U1) || (condition_x == `LM32_CONDITION_U2))
1593 && (valid_x == `TRUE)
1594 && (branch_predict_x == `FALSE)
1595 );
1596 `endif
1598 // Indicate when a branch should be taken in M stage (exceptions are a type of branch)
1599 assign branch_taken_m = (stall_m == `FALSE)
1600 && ( ( (branch_m == `TRUE)
1601 && (valid_m == `TRUE)
1602 && ( ( (condition_met_m == `TRUE)
1603 && (branch_predict_taken_m == `FALSE)
1604 )
1605 || ( (condition_met_m == `FALSE)
1606 && (branch_predict_m == `TRUE)
1607 && (branch_predict_taken_m == `TRUE)
1608 )
1609 )
1610 )
1611 || (exception_m == `TRUE)
1612 );
1614 // Indicate when a branch in M stage is mispredicted as being taken
1615 assign branch_mispredict_taken_m = (condition_met_m == `FALSE)
1616 && (branch_predict_m == `TRUE)
1617 && (branch_predict_taken_m == `TRUE);
1619 // Indicate when a branch in M stage will cause flush in X stage
1620 assign branch_flushX_m = (stall_m == `FALSE)
1621 && ( ( (branch_m == `TRUE)
1622 && (valid_m == `TRUE)
1623 && ( (condition_met_m == `TRUE)
1624 || ( (condition_met_m == `FALSE)
1625 && (branch_predict_m == `TRUE)
1626 && (branch_predict_taken_m == `TRUE)
1627 )
1628 )
1629 )
1630 || (exception_m == `TRUE)
1631 );
1633 // Generate signal that will kill instructions in each pipeline stage when necessary
1634 assign kill_f = ( (valid_d == `TRUE)
1635 && (branch_predict_taken_d == `TRUE)
1636 )
1637 || (branch_taken_m == `TRUE)
1638 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1639 || (branch_taken_x == `TRUE)
1640 `endif
1641 `ifdef CFG_ICACHE_ENABLED
1642 || (icache_refill_request == `TRUE)
1643 `endif
1644 `ifdef CFG_DCACHE_ENABLED
1645 || (dcache_refill_request == `TRUE)
1646 `endif
1647 ;
1648 assign kill_d = (branch_taken_m == `TRUE)
1649 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1650 || (branch_taken_x == `TRUE)
1651 `endif
1652 `ifdef CFG_ICACHE_ENABLED
1653 || (icache_refill_request == `TRUE)
1654 `endif
1655 `ifdef CFG_DCACHE_ENABLED
1656 || (dcache_refill_request == `TRUE)
1657 `endif
1658 ;
1659 assign kill_x = (branch_flushX_m == `TRUE)
1660 `ifdef CFG_DCACHE_ENABLED
1661 || (dcache_refill_request == `TRUE)
1662 `endif
1663 ;
1664 assign kill_m = `FALSE
1665 `ifdef CFG_DCACHE_ENABLED
1666 || (dcache_refill_request == `TRUE)
1667 `endif
1668 ;
1669 assign kill_w = `FALSE
1670 `ifdef CFG_DCACHE_ENABLED
1671 || (dcache_refill_request == `TRUE)
1672 `endif
1673 ;
1675 // Exceptions
1677 `ifdef CFG_DEBUG_ENABLED
1678 assign breakpoint_exception = ( ( (break_x == `TRUE)
1679 || (bp_match == `TRUE)
1680 )
1681 && (valid_x == `TRUE)
1682 )
1683 `ifdef CFG_JTAG_ENABLED
1684 || (jtag_break == `TRUE)
1685 `endif
1686 ;
1687 `endif
1689 `ifdef CFG_DEBUG_ENABLED
1690 assign watchpoint_exception = wp_match == `TRUE;
1691 `endif
1693 `ifdef CFG_BUS_ERRORS_ENABLED
1694 assign instruction_bus_error_exception = ( (bus_error_x == `TRUE)
1695 && (valid_x == `TRUE)
1696 );
1697 assign data_bus_error_exception = data_bus_error_seen == `TRUE;
1698 `endif
1700 `ifdef CFG_MC_DIVIDE_ENABLED
1701 assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
1702 `endif
1704 assign system_call_exception = ( (scall_x == `TRUE)
1705 `ifdef CFG_BUS_ERRORS_ENABLED
1706 && (valid_x == `TRUE)
1707 `endif
1708 );
1710 `ifdef CFG_DEBUG_ENABLED
1711 assign debug_exception_x = (breakpoint_exception == `TRUE)
1712 || (watchpoint_exception == `TRUE)
1713 ;
1715 assign non_debug_exception_x = (system_call_exception == `TRUE)
1716 `ifdef CFG_JTAG_ENABLED
1717 || (reset_exception == `TRUE)
1718 `endif
1719 `ifdef CFG_BUS_ERRORS_ENABLED
1720 || (instruction_bus_error_exception == `TRUE)
1721 || (data_bus_error_exception == `TRUE)
1722 `endif
1723 `ifdef CFG_MC_DIVIDE_ENABLED
1724 || (divide_by_zero_exception == `TRUE)
1725 `endif
1726 `ifdef CFG_INTERRUPTS_ENABLED
1727 || ( (interrupt_exception == `TRUE)
1728 `ifdef LM32_SINGLE_STEP_ENABLED
1729 && (dc_ss == `FALSE)
1730 `endif
1731 `ifdef CFG_BUS_ERRORS_ENABLED
1732 && (store_q_m == `FALSE)
1733 && (D_CYC_O == `FALSE)
1734 `endif
1735 )
1736 `endif
1737 ;
1739 assign exception_x = (debug_exception_x == `TRUE) || (non_debug_exception_x == `TRUE);
1740 `else
1741 assign exception_x = (system_call_exception == `TRUE)
1742 `ifdef CFG_BUS_ERRORS_ENABLED
1743 || (instruction_bus_error_exception == `TRUE)
1744 || (data_bus_error_exception == `TRUE)
1745 `endif
1746 `ifdef CFG_MC_DIVIDE_ENABLED
1747 || (divide_by_zero_exception == `TRUE)
1748 `endif
1749 `ifdef CFG_INTERRUPTS_ENABLED
1750 || ( (interrupt_exception == `TRUE)
1751 `ifdef LM32_SINGLE_STEP_ENABLED
1752 && (dc_ss == `FALSE)
1753 `endif
1754 `ifdef CFG_BUS_ERRORS_ENABLED
1755 && (store_q_m == `FALSE)
1756 && (D_CYC_O == `FALSE)
1757 `endif
1758 )
1759 `endif
1760 ;
1761 `endif
1763 // Exception ID
1764 always @(*)
1765 begin
1766 `ifdef CFG_DEBUG_ENABLED
1767 `ifdef CFG_JTAG_ENABLED
1768 if (reset_exception == `TRUE)
1769 eid_x = `LM32_EID_RESET;
1770 else
1771 `endif
1772 `ifdef CFG_BUS_ERRORS_ENABLED
1773 if (data_bus_error_exception == `TRUE)
1774 eid_x = `LM32_EID_DATA_BUS_ERROR;
1775 else
1776 `endif
1777 if (breakpoint_exception == `TRUE)
1778 eid_x = `LM32_EID_BREAKPOINT;
1779 else
1780 `endif
1781 `ifdef CFG_BUS_ERRORS_ENABLED
1782 if (data_bus_error_exception == `TRUE)
1783 eid_x = `LM32_EID_DATA_BUS_ERROR;
1784 else
1785 if (instruction_bus_error_exception == `TRUE)
1786 eid_x = `LM32_EID_INST_BUS_ERROR;
1787 else
1788 `endif
1789 `ifdef CFG_DEBUG_ENABLED
1790 if (watchpoint_exception == `TRUE)
1791 eid_x = `LM32_EID_WATCHPOINT;
1792 else
1793 `endif
1794 `ifdef CFG_MC_DIVIDE_ENABLED
1795 if (divide_by_zero_exception == `TRUE)
1796 eid_x = `LM32_EID_DIVIDE_BY_ZERO;
1797 else
1798 `endif
1799 `ifdef CFG_INTERRUPTS_ENABLED
1800 if ( (interrupt_exception == `TRUE)
1801 `ifdef LM32_SINGLE_STEP_ENABLED
1802 && (dc_ss == `FALSE)
1803 `endif
1804 )
1805 eid_x = `LM32_EID_INTERRUPT;
1806 else
1807 `endif
1808 eid_x = `LM32_EID_SCALL;
1809 end
1811 // Stall generation
1813 assign stall_a = (stall_f == `TRUE);
1815 assign stall_f = (stall_d == `TRUE);
1817 assign stall_d = (stall_x == `TRUE)
1818 || ( (interlock == `TRUE)
1819 && (kill_d == `FALSE)
1820 )
1821 || ( ( (eret_d == `TRUE)
1822 || (scall_d == `TRUE)
1823 || (bus_error_d == `TRUE)
1824 )
1825 && ( (load_q_x == `TRUE)
1826 || (load_q_m == `TRUE)
1827 || (store_q_x == `TRUE)
1828 || (store_q_m == `TRUE)
1829 || (D_CYC_O == `TRUE)
1830 )
1831 && (kill_d == `FALSE)
1832 )
1833 `ifdef CFG_DEBUG_ENABLED
1834 || ( ( (break_d == `TRUE)
1835 || (bret_d == `TRUE)
1836 )
1837 && ( (load_q_x == `TRUE)
1838 || (store_q_x == `TRUE)
1839 || (load_q_m == `TRUE)
1840 || (store_q_m == `TRUE)
1841 || (D_CYC_O == `TRUE)
1842 )
1843 && (kill_d == `FALSE)
1844 )
1845 `endif
1846 || ( (csr_write_enable_d == `TRUE)
1847 && (load_q_x == `TRUE)
1848 )
1849 ;
1851 assign stall_x = (stall_m == `TRUE)
1852 `ifdef LM32_MC_ARITHMETIC_ENABLED
1853 || ( (mc_stall_request_x == `TRUE)
1854 && (kill_x == `FALSE)
1855 )
1856 `endif
1857 `ifdef CFG_IROM_ENABLED
1858 // Stall load/store instruction in D stage if there is an ongoing store
1859 // operation to instruction ROM in M stage
1860 || ( (irom_stall_request_x == `TRUE)
1861 && ( (load_d == `TRUE)
1862 || (store_d == `TRUE)
1863 )
1864 )
1865 `endif
1866 ;
1868 assign stall_m = (stall_wb_load == `TRUE)
1869 `ifdef CFG_SIZE_OVER_SPEED
1870 || (D_CYC_O == `TRUE)
1871 `else
1872 || ( (D_CYC_O == `TRUE)
1873 && ( (store_m == `TRUE)
1874 /*
1875 Bug: Following loop does not allow interrupts to be services since
1876 either D_CYC_O or store_m is always high during entire duration of
1877 loop.
1878 L1: addi r1, r1, 1
1879 sw (r2,0), r1
1880 bi L1
1882 Introduce a single-cycle stall when a wishbone cycle is in progress
1883 and a new store instruction is in Execute stage and a interrupt
1884 exception has occured. This stall will ensure that D_CYC_O and
1885 store_m will both be low for one cycle.
1886 */
1887 || ((store_x == `TRUE) && (interrupt_exception == `TRUE))
1888 || (load_m == `TRUE)
1889 || (load_x == `TRUE)
1890 )
1891 )
1892 `endif
1893 `ifdef CFG_DCACHE_ENABLED
1894 || (dcache_stall_request == `TRUE) // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
1895 `endif
1896 `ifdef CFG_ICACHE_ENABLED
1897 || (icache_stall_request == `TRUE) // Pipeline needs to be stalled otherwise branches may be lost
1898 || ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) || (exception_m == `TRUE)))
1899 `else
1900 `ifdef CFG_IWB_ENABLED
1901 || (I_CYC_O == `TRUE)
1902 `endif
1903 `endif
1904 `ifdef CFG_USER_ENABLED
1905 || ( (user_valid == `TRUE) // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
1906 && (user_complete == `FALSE)
1907 )
1908 `endif
1909 ;
1911 // Qualify state changing control signals
1912 `ifdef LM32_MC_ARITHMETIC_ENABLED
1913 assign q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
1914 `endif
1915 `ifdef CFG_MC_BARREL_SHIFT_ENABLED
1916 assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
1917 assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
1918 `endif
1919 `ifdef CFG_MC_MULTIPLY_ENABLED
1920 assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
1921 `endif
1922 `ifdef CFG_MC_DIVIDE_ENABLED
1923 assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
1924 assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
1925 `endif
1926 assign q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
1927 assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
1928 assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
1929 `ifdef CFG_DEBUG_ENABLED
1930 assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
1931 `endif
1932 assign load_q_x = (load_x == `TRUE)
1933 && (q_x == `TRUE)
1934 `ifdef CFG_DEBUG_ENABLED
1935 && (bp_match == `FALSE)
1936 `endif
1937 ;
1938 assign store_q_x = (store_x == `TRUE)
1939 && (q_x == `TRUE)
1940 `ifdef CFG_DEBUG_ENABLED
1941 && (bp_match == `FALSE)
1942 `endif
1943 ;
1944 `ifdef CFG_USER_ENABLED
1945 assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
1946 `endif
1947 assign q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
1948 assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
1949 assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
1950 `ifdef CFG_DEBUG_ENABLED
1951 assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
1952 assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));
1953 `else
1954 assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));
1955 `endif
1956 // Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
1957 assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE) && (branch_flushX_m == `FALSE);
1958 assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
1959 assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
1960 // The enable that actually does write the registers needs to be qualified with kill
1961 assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
1963 // Configuration (CFG) CSR
1964 assign cfg = {
1965 `LM32_REVISION,
1966 watchpoints[3:0],
1967 breakpoints[3:0],
1968 interrupts[5:0],
1969 `ifdef CFG_JTAG_UART_ENABLED
1970 `TRUE,
1971 `else
1972 `FALSE,
1973 `endif
1974 `ifdef CFG_ROM_DEBUG_ENABLED
1975 `TRUE,
1976 `else
1977 `FALSE,
1978 `endif
1979 `ifdef CFG_HW_DEBUG_ENABLED
1980 `TRUE,
1981 `else
1982 `FALSE,
1983 `endif
1984 `ifdef CFG_DEBUG_ENABLED
1985 `TRUE,
1986 `else
1987 `FALSE,
1988 `endif
1989 `ifdef CFG_ICACHE_ENABLED
1990 `TRUE,
1991 `else
1992 `FALSE,
1993 `endif
1994 `ifdef CFG_DCACHE_ENABLED
1995 `TRUE,
1996 `else
1997 `FALSE,
1998 `endif
1999 `ifdef CFG_CYCLE_COUNTER_ENABLED
2000 `TRUE,
2001 `else
2002 `FALSE,
2003 `endif
2004 `ifdef CFG_USER_ENABLED
2005 `TRUE,
2006 `else
2007 `FALSE,
2008 `endif
2009 `ifdef CFG_SIGN_EXTEND_ENABLED
2010 `TRUE,
2011 `else
2012 `FALSE,
2013 `endif
2014 `ifdef LM32_BARREL_SHIFT_ENABLED
2015 `TRUE,
2016 `else
2017 `FALSE,
2018 `endif
2019 `ifdef CFG_MC_DIVIDE_ENABLED
2020 `TRUE,
2021 `else
2022 `FALSE,
2023 `endif
2024 `ifdef LM32_MULTIPLY_ENABLED
2025 `TRUE
2026 `else
2027 `FALSE
2028 `endif
2029 };
2031 assign cfg2 = {
2032 30'b0,
2033 `ifdef CFG_IROM_ENABLED
2034 `TRUE,
2035 `else
2036 `FALSE,
2037 `endif
2038 `ifdef CFG_DRAM_ENABLED
2039 `TRUE
2040 `else
2041 `FALSE
2042 `endif
2043 };
2045 // Cache flush
2046 `ifdef CFG_ICACHE_ENABLED
2047 assign iflush = (csr_write_enable_d == `TRUE)
2048 && (csr_d == `LM32_CSR_ICC)
2049 && (stall_d == `FALSE)
2050 && (kill_d == `FALSE)
2051 && (valid_d == `TRUE);
2052 `endif
2053 `ifdef CFG_DCACHE_ENABLED
2054 assign dflush_x = (csr_write_enable_q_x == `TRUE)
2055 && (csr_x == `LM32_CSR_DCC);
2056 `endif
2058 // Extract CSR index
2059 assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
2061 // CSR reads
2062 always @(*)
2063 begin
2064 case (csr_x)
2065 `ifdef CFG_INTERRUPTS_ENABLED
2066 `LM32_CSR_IE,
2067 `LM32_CSR_IM,
2068 `LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x;
2069 `endif
2070 `ifdef CFG_CYCLE_COUNTER_ENABLED
2071 `LM32_CSR_CC: csr_read_data_x = cc;
2072 `endif
2073 `LM32_CSR_CFG: csr_read_data_x = cfg;
2074 `LM32_CSR_EBA: csr_read_data_x = {eba, 8'h00};
2075 `ifdef CFG_DEBUG_ENABLED
2076 `LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
2077 `endif
2078 `ifdef CFG_JTAG_UART_ENABLED
2079 `LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data;
2080 `LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data;
2081 `endif
2082 `LM32_CSR_CFG2: csr_read_data_x = cfg2;
2084 default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
2085 endcase
2086 end
2088 /////////////////////////////////////////////////////
2089 // Sequential Logic
2090 /////////////////////////////////////////////////////
2092 // Exception Base Address (EBA) CSR
2093 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2094 begin
2095 if (rst_i == `TRUE)
2096 eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
2097 else
2098 begin
2099 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
2100 eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
2101 `ifdef CFG_HW_DEBUG_ENABLED
2102 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
2103 eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
2104 `endif
2105 end
2106 end
2108 `ifdef CFG_DEBUG_ENABLED
2109 // Debug Exception Base Address (DEBA) CSR
2110 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2111 begin
2112 if (rst_i == `TRUE)
2113 deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
2114 else
2115 begin
2116 if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
2117 deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
2118 `ifdef CFG_HW_DEBUG_ENABLED
2119 if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
2120 deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
2121 `endif
2122 end
2123 end
2124 `endif
2126 // Cycle Counter (CC) CSR
2127 `ifdef CFG_CYCLE_COUNTER_ENABLED
2128 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2129 begin
2130 if (rst_i == `TRUE)
2131 cc <= {`LM32_WORD_WIDTH{1'b0}};
2132 else
2133 cc <= cc + 1'b1;
2134 end
2135 `endif
2137 `ifdef CFG_BUS_ERRORS_ENABLED
2138 // Watch for data bus errors
2139 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2140 begin
2141 if (rst_i == `TRUE)
2142 data_bus_error_seen <= `FALSE;
2143 else
2144 begin
2145 // Set flag when bus error is detected
2146 if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
2147 data_bus_error_seen <= `TRUE;
2148 // Clear flag when exception is taken
2149 if ((exception_m == `TRUE) && (kill_m == `FALSE))
2150 data_bus_error_seen <= `FALSE;
2151 end
2152 end
2153 `endif
2155 // Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not
2157 `ifdef CFG_ICACHE_ENABLED
2158 `ifdef CFG_DCACHE_ENABLED
2159 always @(*)
2160 begin
2161 if ( (icache_refill_request == `TRUE)
2162 || (dcache_refill_request == `TRUE)
2163 )
2164 valid_a = `FALSE;
2165 else if ( (icache_restart_request == `TRUE)
2166 || (dcache_restart_request == `TRUE)
2167 )
2168 valid_a = `TRUE;
2169 else
2170 valid_a = !icache_refilling && !dcache_refilling;
2171 end
2172 `else
2173 always @(*)
2174 begin
2175 if (icache_refill_request == `TRUE)
2176 valid_a = `FALSE;
2177 else if (icache_restart_request == `TRUE)
2178 valid_a = `TRUE;
2179 else
2180 valid_a = !icache_refilling;
2181 end
2182 `endif
2183 `else
2184 `ifdef CFG_DCACHE_ENABLED
2185 always @(*)
2186 begin
2187 if (dcache_refill_request == `TRUE)
2188 valid_a = `FALSE;
2189 else if (dcache_restart_request == `TRUE)
2190 valid_a = `TRUE;
2191 else
2192 valid_a = !dcache_refilling;
2193 end
2194 `endif
2195 `endif
2197 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2198 begin
2199 if (rst_i == `TRUE)
2200 begin
2201 valid_f <= `FALSE;
2202 valid_d <= `FALSE;
2203 valid_x <= `FALSE;
2204 valid_m <= `FALSE;
2205 valid_w <= `FALSE;
2206 end
2207 else
2208 begin
2209 if ((kill_f == `TRUE) || (stall_a == `FALSE))
2210 `ifdef LM32_CACHE_ENABLED
2211 valid_f <= valid_a;
2212 `else
2213 valid_f <= `TRUE;
2214 `endif
2215 else if (stall_f == `FALSE)
2216 valid_f <= `FALSE;
2218 if (kill_d == `TRUE)
2219 valid_d <= `FALSE;
2220 else if (stall_f == `FALSE)
2221 valid_d <= valid_f & !kill_f;
2222 else if (stall_d == `FALSE)
2223 valid_d <= `FALSE;
2225 if (stall_d == `FALSE)
2226 valid_x <= valid_d & !kill_d;
2227 else if (kill_x == `TRUE)
2228 valid_x <= `FALSE;
2229 else if (stall_x == `FALSE)
2230 valid_x <= `FALSE;
2232 if (kill_m == `TRUE)
2233 valid_m <= `FALSE;
2234 else if (stall_x == `FALSE)
2235 valid_m <= valid_x & !kill_x;
2236 else if (stall_m == `FALSE)
2237 valid_m <= `FALSE;
2239 if (stall_m == `FALSE)
2240 valid_w <= valid_m & !kill_m;
2241 else
2242 valid_w <= `FALSE;
2243 end
2244 end
2246 // Microcode pipeline registers
2247 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2248 begin
2249 if (rst_i == `TRUE)
2250 begin
2251 `ifdef CFG_USER_ENABLED
2252 user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};
2253 `endif
2254 operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
2255 operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
2256 store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
2257 branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};
2258 x_result_sel_csr_x <= `FALSE;
2259 `ifdef LM32_MC_ARITHMETIC_ENABLED
2260 x_result_sel_mc_arith_x <= `FALSE;
2261 `endif
2262 `ifdef LM32_NO_BARREL_SHIFT
2263 x_result_sel_shift_x <= `FALSE;
2264 `endif
2265 `ifdef CFG_SIGN_EXTEND_ENABLED
2266 x_result_sel_sext_x <= `FALSE;
2267 `endif
2268 x_result_sel_logic_x <= `FALSE;
2269 `ifdef CFG_USER_ENABLED
2270 x_result_sel_user_x <= `FALSE;
2271 `endif
2272 x_result_sel_add_x <= `FALSE;
2273 m_result_sel_compare_x <= `FALSE;
2274 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2275 m_result_sel_shift_x <= `FALSE;
2276 `endif
2277 w_result_sel_load_x <= `FALSE;
2278 `ifdef CFG_PL_MULTIPLY_ENABLED
2279 w_result_sel_mul_x <= `FALSE;
2280 `endif
2281 x_bypass_enable_x <= `FALSE;
2282 m_bypass_enable_x <= `FALSE;
2283 write_enable_x <= `FALSE;
2284 write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
2285 csr_x <= {`LM32_CSR_WIDTH{1'b0}};
2286 load_x <= `FALSE;
2287 store_x <= `FALSE;
2288 size_x <= {`LM32_SIZE_WIDTH{1'b0}};
2289 sign_extend_x <= `FALSE;
2290 adder_op_x <= `FALSE;
2291 adder_op_x_n <= `FALSE;
2292 logic_op_x <= 4'h0;
2293 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2294 direction_x <= `FALSE;
2295 `endif
2296 `ifdef CFG_ROTATE_ENABLED
2297 rotate_x <= `FALSE;
2299 `endif
2300 branch_x <= `FALSE;
2301 branch_predict_x <= `FALSE;
2302 branch_predict_taken_x <= `FALSE;
2303 condition_x <= `LM32_CONDITION_U1;
2304 `ifdef CFG_DEBUG_ENABLED
2305 break_x <= `FALSE;
2306 `endif
2307 scall_x <= `FALSE;
2308 eret_x <= `FALSE;
2309 `ifdef CFG_DEBUG_ENABLED
2310 bret_x <= `FALSE;
2311 `endif
2312 `ifdef CFG_BUS_ERRORS_ENABLED
2313 bus_error_x <= `FALSE;
2314 data_bus_error_exception_m <= `FALSE;
2315 `endif
2316 csr_write_enable_x <= `FALSE;
2317 operand_m <= {`LM32_WORD_WIDTH{1'b0}};
2318 branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
2319 m_result_sel_compare_m <= `FALSE;
2320 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2321 m_result_sel_shift_m <= `FALSE;
2322 `endif
2323 w_result_sel_load_m <= `FALSE;
2324 `ifdef CFG_PL_MULTIPLY_ENABLED
2325 w_result_sel_mul_m <= `FALSE;
2326 `endif
2327 m_bypass_enable_m <= `FALSE;
2328 branch_m <= `FALSE;
2329 branch_predict_m <= `FALSE;
2330 branch_predict_taken_m <= `FALSE;
2331 exception_m <= `FALSE;
2332 load_m <= `FALSE;
2333 store_m <= `FALSE;
2334 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2335 direction_m <= `FALSE;
2336 `endif
2337 write_enable_m <= `FALSE;
2338 write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
2339 condition_met_m <= `FALSE;
2340 `ifdef CFG_DCACHE_ENABLED
2341 dflush_m <= `FALSE;
2342 `endif
2343 `ifdef CFG_DEBUG_ENABLED
2344 debug_exception_m <= `FALSE;
2345 non_debug_exception_m <= `FALSE;
2346 `endif
2347 operand_w <= {`LM32_WORD_WIDTH{1'b0}};
2348 w_result_sel_load_w <= `FALSE;
2349 `ifdef CFG_PL_MULTIPLY_ENABLED
2350 w_result_sel_mul_w <= `FALSE;
2351 `endif
2352 write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};
2353 write_enable_w <= `FALSE;
2354 `ifdef CFG_DEBUG_ENABLED
2355 debug_exception_w <= `FALSE;
2356 non_debug_exception_w <= `FALSE;
2357 `else
2358 exception_w <= `FALSE;
2359 `endif
2360 `ifdef CFG_BUS_ERRORS_ENABLED
2361 memop_pc_w <= {`LM32_PC_WIDTH{1'b0}};
2362 `endif
2363 end
2364 else
2365 begin
2366 // D/X stage registers
2368 if (stall_x == `FALSE)
2369 begin
2370 `ifdef CFG_USER_ENABLED
2371 user_opcode <= user_opcode_d;
2372 `endif
2373 operand_0_x <= d_result_0;
2374 operand_1_x <= d_result_1;
2375 store_operand_x <= bypass_data_1;
2376 branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : branch_target_d;
2377 x_result_sel_csr_x <= x_result_sel_csr_d;
2378 `ifdef LM32_MC_ARITHMETIC_ENABLED
2379 x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
2380 `endif
2381 `ifdef LM32_NO_BARREL_SHIFT
2382 x_result_sel_shift_x <= x_result_sel_shift_d;
2383 `endif
2384 `ifdef CFG_SIGN_EXTEND_ENABLED
2385 x_result_sel_sext_x <= x_result_sel_sext_d;
2386 `endif
2387 x_result_sel_logic_x <= x_result_sel_logic_d;
2388 `ifdef CFG_USER_ENABLED
2389 x_result_sel_user_x <= x_result_sel_user_d;
2390 `endif
2391 x_result_sel_add_x <= x_result_sel_add_d;
2392 m_result_sel_compare_x <= m_result_sel_compare_d;
2393 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2394 m_result_sel_shift_x <= m_result_sel_shift_d;
2395 `endif
2396 w_result_sel_load_x <= w_result_sel_load_d;
2397 `ifdef CFG_PL_MULTIPLY_ENABLED
2398 w_result_sel_mul_x <= w_result_sel_mul_d;
2399 `endif
2400 x_bypass_enable_x <= x_bypass_enable_d;
2401 m_bypass_enable_x <= m_bypass_enable_d;
2402 load_x <= load_d;
2403 store_x <= store_d;
2404 branch_x <= branch_d;
2405 branch_predict_x <= branch_predict_d;
2406 branch_predict_taken_x <= branch_predict_taken_d;
2407 write_idx_x <= write_idx_d;
2408 csr_x <= csr_d;
2409 size_x <= size_d;
2410 sign_extend_x <= sign_extend_d;
2411 adder_op_x <= adder_op_d;
2412 adder_op_x_n <= ~adder_op_d;
2413 logic_op_x <= logic_op_d;
2414 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2415 direction_x <= direction_d;
2416 `endif
2417 `ifdef CFG_ROTATE_ENABLED
2418 rotate_x <= rotate_d;
2419 `endif
2420 condition_x <= condition_d;
2421 csr_write_enable_x <= csr_write_enable_d;
2422 `ifdef CFG_DEBUG_ENABLED
2423 break_x <= break_d;
2424 `endif
2425 scall_x <= scall_d;
2426 `ifdef CFG_BUS_ERRORS_ENABLED
2427 bus_error_x <= bus_error_d;
2428 `endif
2429 eret_x <= eret_d;
2430 `ifdef CFG_DEBUG_ENABLED
2431 bret_x <= bret_d;
2432 `endif
2433 write_enable_x <= write_enable_d;
2434 end
2436 // X/M stage registers
2438 if (stall_m == `FALSE)
2439 begin
2440 operand_m <= x_result;
2441 m_result_sel_compare_m <= m_result_sel_compare_x;
2442 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2443 m_result_sel_shift_m <= m_result_sel_shift_x;
2444 `endif
2445 if (exception_x == `TRUE)
2446 begin
2447 w_result_sel_load_m <= `FALSE;
2448 `ifdef CFG_PL_MULTIPLY_ENABLED
2449 w_result_sel_mul_m <= `FALSE;
2450 `endif
2451 end
2452 else
2453 begin
2454 w_result_sel_load_m <= w_result_sel_load_x;
2455 `ifdef CFG_PL_MULTIPLY_ENABLED
2456 w_result_sel_mul_m <= w_result_sel_mul_x;
2457 `endif
2458 end
2459 m_bypass_enable_m <= m_bypass_enable_x;
2460 `ifdef CFG_PL_BARREL_SHIFT_ENABLED
2461 direction_m <= direction_x;
2462 `endif
2463 load_m <= load_x;
2464 store_m <= store_x;
2465 `ifdef CFG_FAST_UNCONDITIONAL_BRANCH
2466 branch_m <= branch_x && !branch_taken_x;
2467 `else
2468 branch_m <= branch_x;
2469 branch_predict_m <= branch_predict_x;
2470 branch_predict_taken_m <= branch_predict_taken_x;
2471 `endif
2472 `ifdef CFG_DEBUG_ENABLED
2473 // Data bus errors are generated by the wishbone and are
2474 // made known to the processor only in next cycle (as a
2475 // non-debug exception). A break instruction can be seen
2476 // in same cycle (causing a debug exception). Handle non
2477 // -debug exception first!
2478 if (non_debug_exception_x == `TRUE)
2479 write_idx_m <= `LM32_EA_REG;
2480 else if (debug_exception_x == `TRUE)
2481 write_idx_m <= `LM32_BA_REG;
2482 else
2483 write_idx_m <= write_idx_x;
2484 `else
2485 if (exception_x == `TRUE)
2486 write_idx_m <= `LM32_EA_REG;
2487 else
2488 write_idx_m <= write_idx_x;
2489 `endif
2490 condition_met_m <= condition_met_x;
2491 `ifdef CFG_DEBUG_ENABLED
2492 if (exception_x == `TRUE)
2493 if ((dc_re == `TRUE)
2494 || ((debug_exception_x == `TRUE)
2495 && (non_debug_exception_x == `FALSE)))
2496 branch_target_m <= {deba, eid_x, {3{1'b0}}};
2497 else
2498 branch_target_m <= {eba, eid_x, {3{1'b0}}};
2499 else
2500 branch_target_m <= branch_target_x;
2501 `else
2502 branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
2503 `endif
2504 `ifdef CFG_TRACE_ENABLED
2505 eid_m <= eid_x;
2506 `endif
2507 `ifdef CFG_DCACHE_ENABLED
2508 dflush_m <= dflush_x;
2509 `endif
2510 eret_m <= eret_q_x;
2511 `ifdef CFG_DEBUG_ENABLED
2512 bret_m <= bret_q_x;
2513 `endif
2514 write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;
2515 `ifdef CFG_DEBUG_ENABLED
2516 debug_exception_m <= debug_exception_x;
2517 non_debug_exception_m <= non_debug_exception_x;
2518 `endif
2519 end
2521 // State changing regs
2522 if (stall_m == `FALSE)
2523 begin
2524 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
2525 exception_m <= `TRUE;
2526 else
2527 exception_m <= `FALSE;
2528 `ifdef CFG_BUS_ERRORS_ENABLED
2529 data_bus_error_exception_m <= (data_bus_error_exception == `TRUE)
2530 `ifdef CFG_DEBUG_ENABLED
2531 && (reset_exception == `FALSE)
2532 `endif
2533 ;
2534 `endif
2535 end
2537 // M/W stage registers
2538 `ifdef CFG_BUS_ERRORS_ENABLED
2539 operand_w <= exception_m == `TRUE ? (data_bus_error_exception_m ? {memop_pc_w, 2'b00} : {pc_m, 2'b00}) : m_result;
2540 `else
2541 operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
2542 `endif
2543 w_result_sel_load_w <= w_result_sel_load_m;
2544 `ifdef CFG_PL_MULTIPLY_ENABLED
2545 w_result_sel_mul_w <= w_result_sel_mul_m;
2546 `endif
2547 write_idx_w <= write_idx_m;
2548 `ifdef CFG_TRACE_ENABLED
2549 eid_w <= eid_m;
2550 eret_w <= eret_m;
2551 `ifdef CFG_DEBUG_ENABLED
2552 bret_w <= bret_m;
2553 `endif
2554 `endif
2555 write_enable_w <= write_enable_m;
2556 `ifdef CFG_DEBUG_ENABLED
2557 debug_exception_w <= debug_exception_m;
2558 non_debug_exception_w <= non_debug_exception_m;
2559 `else
2560 exception_w <= exception_m;
2561 `endif
2562 `ifdef CFG_BUS_ERRORS_ENABLED
2563 if ( (stall_m == `FALSE)
2564 && ( (load_q_m == `TRUE)
2565 || (store_q_m == `TRUE)
2566 )
2567 )
2568 memop_pc_w <= pc_m;
2569 `endif
2570 end
2571 end
2573 `ifdef CFG_EBR_POSEDGE_REGISTER_FILE
2574 // Buffer data read from register file, in case a stall occurs, and watch for
2575 // any writes to the modified registers
2576 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2577 begin
2578 if (rst_i == `TRUE)
2579 begin
2580 use_buf <= `FALSE;
2581 reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
2582 reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
2583 end
2584 else
2585 begin
2586 if (stall_d == `FALSE)
2587 use_buf <= `FALSE;
2588 else if (use_buf == `FALSE)
2589 begin
2590 reg_data_buf_0 <= reg_data_live_0;
2591 reg_data_buf_1 <= reg_data_live_1;
2592 use_buf <= `TRUE;
2593 end
2594 if (reg_write_enable_q_w == `TRUE)
2595 begin
2596 if (write_idx_w == read_idx_0_d)
2597 reg_data_buf_0 <= w_result;
2598 if (write_idx_w == read_idx_1_d)
2599 reg_data_buf_1 <= w_result;
2600 end
2601 end
2602 end
2603 `endif
2605 `ifdef LM32_EBR_REGISTER_FILE
2606 `else
2607 // Register file write port
2608 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2609 begin
2610 if (rst_i == `TRUE) begin
2611 registers[0] <= {`LM32_WORD_WIDTH{1'b0}};
2612 registers[1] <= {`LM32_WORD_WIDTH{1'b0}};
2613 registers[2] <= {`LM32_WORD_WIDTH{1'b0}};
2614 registers[3] <= {`LM32_WORD_WIDTH{1'b0}};
2615 registers[4] <= {`LM32_WORD_WIDTH{1'b0}};
2616 registers[5] <= {`LM32_WORD_WIDTH{1'b0}};
2617 registers[6] <= {`LM32_WORD_WIDTH{1'b0}};
2618 registers[7] <= {`LM32_WORD_WIDTH{1'b0}};
2619 registers[8] <= {`LM32_WORD_WIDTH{1'b0}};
2620 registers[9] <= {`LM32_WORD_WIDTH{1'b0}};
2621 registers[10] <= {`LM32_WORD_WIDTH{1'b0}};
2622 registers[11] <= {`LM32_WORD_WIDTH{1'b0}};
2623 registers[12] <= {`LM32_WORD_WIDTH{1'b0}};
2624 registers[13] <= {`LM32_WORD_WIDTH{1'b0}};
2625 registers[14] <= {`LM32_WORD_WIDTH{1'b0}};
2626 registers[15] <= {`LM32_WORD_WIDTH{1'b0}};
2627 registers[16] <= {`LM32_WORD_WIDTH{1'b0}};
2628 registers[17] <= {`LM32_WORD_WIDTH{1'b0}};
2629 registers[18] <= {`LM32_WORD_WIDTH{1'b0}};
2630 registers[19] <= {`LM32_WORD_WIDTH{1'b0}};
2631 registers[20] <= {`LM32_WORD_WIDTH{1'b0}};
2632 registers[21] <= {`LM32_WORD_WIDTH{1'b0}};
2633 registers[22] <= {`LM32_WORD_WIDTH{1'b0}};
2634 registers[23] <= {`LM32_WORD_WIDTH{1'b0}};
2635 registers[24] <= {`LM32_WORD_WIDTH{1'b0}};
2636 registers[25] <= {`LM32_WORD_WIDTH{1'b0}};
2637 registers[26] <= {`LM32_WORD_WIDTH{1'b0}};
2638 registers[27] <= {`LM32_WORD_WIDTH{1'b0}};
2639 registers[28] <= {`LM32_WORD_WIDTH{1'b0}};
2640 registers[29] <= {`LM32_WORD_WIDTH{1'b0}};
2641 registers[30] <= {`LM32_WORD_WIDTH{1'b0}};
2642 registers[31] <= {`LM32_WORD_WIDTH{1'b0}};
2643 end
2644 else begin
2645 if (reg_write_enable_q_w == `TRUE)
2646 registers[write_idx_w] <= w_result;
2647 end
2648 end
2649 `endif
2651 `ifdef CFG_TRACE_ENABLED
2652 // PC tracing logic
2653 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2654 begin
2655 if (rst_i == `TRUE)
2656 begin
2657 trace_pc_valid <= `FALSE;
2658 trace_pc <= {`LM32_PC_WIDTH{1'b0}};
2659 trace_exception <= `FALSE;
2660 trace_eid <= `LM32_EID_RESET;
2661 trace_eret <= `FALSE;
2662 `ifdef CFG_DEBUG_ENABLED
2663 trace_bret <= `FALSE;
2664 `endif
2665 pc_c <= `CFG_EBA_RESET/4;
2666 end
2667 else
2668 begin
2669 trace_pc_valid <= `FALSE;
2670 // Has an exception occured
2671 `ifdef CFG_DEBUG_ENABLED
2672 if ((debug_exception_q_w == `TRUE) || (non_debug_exception_q_w == `TRUE))
2673 `else
2674 if (exception_q_w == `TRUE)
2675 `endif
2676 begin
2677 trace_exception <= `TRUE;
2678 trace_pc_valid <= `TRUE;
2679 trace_pc <= pc_w;
2680 trace_eid <= eid_w;
2681 end
2682 else
2683 trace_exception <= `FALSE;
2685 if ((valid_w == `TRUE) && (!kill_w))
2686 begin
2687 // An instruction is commiting. Determine if it is non-sequential
2688 if (pc_c + 1'b1 != pc_w)
2689 begin
2690 // Non-sequential instruction
2691 trace_pc_valid <= `TRUE;
2692 trace_pc <= pc_w;
2693 end
2694 // Record PC so we can determine if next instruction is sequential or not
2695 pc_c <= pc_w;
2696 // Indicate if it was an eret/bret instruction
2697 trace_eret <= eret_w;
2698 `ifdef CFG_DEBUG_ENABLED
2699 trace_bret <= bret_w;
2700 `endif
2701 end
2702 else
2703 begin
2704 trace_eret <= `FALSE;
2705 `ifdef CFG_DEBUG_ENABLED
2706 trace_bret <= `FALSE;
2707 `endif
2708 end
2709 end
2710 end
2711 `endif
2713 /////////////////////////////////////////////////////
2714 // Behavioural Logic
2715 /////////////////////////////////////////////////////
2717 // synthesis translate_off
2719 // Reset register 0. Only needed for simulation.
2720 initial
2721 begin
2722 `ifdef LM32_EBR_REGISTER_FILE
2723 reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
2724 reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
2725 `else
2726 registers[0] = {`LM32_WORD_WIDTH{1'b0}};
2727 `endif
2728 end
2730 // synthesis translate_on
2732 endmodule