Sun, 04 Apr 2010 20:40:03 +0100
add lm32 source
1 // =============================================================================
2 // COPYRIGHT NOTICE
3 // Copyright 2006 (c) Lattice Semiconductor Corporation
4 // ALL RIGHTS RESERVED
5 // This confidential and proprietary software may be used only as authorised by
6 // a licensing agreement from Lattice Semiconductor Corporation.
7 // The entire notice above must be reproduced on all authorized copies and
8 // copies may only be made to the extent permitted by a licensing agreement from
9 // Lattice Semiconductor Corporation.
10 //
11 // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12 // 5555 NE Moore Court 408-826-6000 (other locations)
13 // Hillsboro, OR 97124 web : http://www.latticesemi.com/
14 // U.S.A email: techsupport@latticesemi.com
15 // =============================================================================/
16 // FILE DETAILS
17 // Project : LatticeMico32
18 // File : SPIPROG.v
19 // This module contains the ER2 regsiters of SPI Serial FLASH programmer IP
20 // core. There are only three ER2 registers, one control register and two
21 // data registers, in this IP core. The control register is a 8-bit wide
22 // register for selecting which data register will be accessed when the
23 // Control/Data# bit in ER1 register is low. Data register 0 is a readonly
24 // ID register. It is composed of three register fields -- an 8-bit
25 // "implementer", a 16-bit "IP_functionality", and a 12-bit "revision".
26 // Data register 1 is a variable length register for sending commands to or
27 // receiving readback data from the SPI Serial FLASH device.
28 // Dependencies : None
29 // Version : 6.1.17
30 // 1. Reduced the the ID register (DR0) length from 36 bits to 8 bits.
31 // 2. Same as TYPEA and TYPEB modules, use falling edge clock
32 // for all TCK Flip-Flops.
33 // 3. Added 7 delay Flip-Flops so that the DR1 readback data from
34 // SPI Serial FLASH is in the byte boundary.
35 // Version : 7.0SP2, 3.0
36 // : No Change
37 // Version : 3.1
38 // : No Change
39 // =============================================================================
40 //---------------------------------------------------------------------------
41 //
42 //Name : SPIPROG.v
43 //
44 //Description:
45 //
46 // This module contains the ER2 regsiters of SPI Serial FLASH programmer IP
47 // core. There are only three ER2 registers, one control register and two
48 // data registers, in this IP core. The control register is a 8-bit wide
49 // register for selecting which data register will be accessed when the
50 // Control/Data# bit in ER1 register is low. Data register 0 is a readonly
51 // ID register. It is composed of three register fields -- an 8-bit
52 // "implementer", a 16-bit "IP_functionality", and a 12-bit "revision".
53 // Data register 1 is a variable length register for sending commands to or
54 // receiving readback data from the SPI Serial FLASH device.
55 //
56 //$Log: spiprog.vhd,v $
57 //Revision 1.2 2004-09-09 11:43:26-07 jhsin
58 //1. Reduced the the ID register (DR0) length from 36 bits to 8 bits.
59 //2. Same as TYPEA and TYPEB modules, use falling edge clock
60 // for all TCK Flip-Flops.
61 //
62 //Revision 1.1 2004-08-12 13:22:05-07 jhsin
63 //Added 7 delay Flip-Flops so that the DR1 readback data from SPI Serial FLASH is in the byte boundary.
64 //
65 //Revision 1.0 2004-08-03 18:35:56-07 jhsin
66 //Initial revision
67 //
68 //
70 module SPIPROG (input JTCK ,
71 input JTDI ,
72 output JTDO2 ,
73 input JSHIFT ,
74 input JUPDATE ,
75 input JRSTN ,
76 input JCE2 ,
77 input SPIPROG_ENABLE ,
78 input CONTROL_DATAN ,
79 output SPI_C ,
80 output SPI_D ,
81 output SPI_SN ,
82 input SPI_Q);
84 wire er2Cr_enable ;
85 wire er2Dr0_enable;
86 wire er2Dr1_enable;
88 wire tdo_er2Cr ;
89 wire tdo_er2Dr0;
90 wire tdo_er2Dr1;
92 wire [7:0] encodedDrSelBits ;
93 wire [8:0] er2CrTdiBit ;
94 wire [8:0] er2Dr0TdiBit ;
96 wire captureDrER2;
97 reg spi_s ;
98 reg [6:0] spi_q_dly;
100 wire [7:0] ip_functionality_id;
102 genvar i;
104 // ------ Control Register 0 ------
106 assign er2Cr_enable = JCE2 & SPIPROG_ENABLE & CONTROL_DATAN;
108 assign tdo_er2Cr = er2CrTdiBit[0];
110 // CR_BIT0_BIT7
111 generate
112 for(i=0; i<=7; i=i+1)
113 begin:CR_BIT0_BIT7
114 TYPEA BIT_N (.CLK (JTCK),
115 .RESET_N (JRSTN),
116 .CLKEN (er2Cr_enable),
117 .TDI (er2CrTdiBit[i + 1]),
118 .TDO (er2CrTdiBit[i]),
119 .DATA_OUT (encodedDrSelBits[i]),
120 .DATA_IN (encodedDrSelBits[i]),
121 .CAPTURE_DR (captureDrER2),
122 .UPDATE_DR (JUPDATE));
123 end
124 endgenerate // CR_BIT0_BIT7
126 assign er2CrTdiBit[8] = JTDI;
128 // ------ Data Register 0 ------
129 assign er2Dr0_enable = (JCE2 & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000000)) ? 1'b1 : 1'b0;
131 assign tdo_er2Dr0 = er2Dr0TdiBit[0];
133 assign ip_functionality_id = 8'b00000001; //-- SPI Serial FLASH Programmer (0x01)
135 // DR0_BIT0_BIT7
136 generate
137 for(i=0; i<=7; i=i+1)
138 begin:DR0_BIT0_BIT7
139 TYPEB BIT_N (.CLK (JTCK),
140 .RESET_N (JRSTN),
141 .CLKEN (er2Dr0_enable),
142 .TDI (er2Dr0TdiBit[i + 1]),
143 .TDO (er2Dr0TdiBit[i]),
144 .DATA_IN (ip_functionality_id[i]),
145 .CAPTURE_DR (captureDrER2));
146 end
147 endgenerate // DR0_BIT0_BIT7
149 assign er2Dr0TdiBit[8] = JTDI;
151 // ------ Data Register 1 ------
153 assign er2Dr1_enable = (JCE2 & JSHIFT & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000001)) ? 1'b1 : 1'b0;
155 assign SPI_C = ~ (JTCK & er2Dr1_enable & spi_s);
157 assign SPI_D = JTDI & er2Dr1_enable;
159 // SPI_S_Proc
160 always @(negedge JTCK or negedge JRSTN)
161 begin
162 if (~JRSTN)
163 spi_s <= 1'b0;
164 else
165 if (JUPDATE)
166 spi_s <= 1'b0;
167 else
168 spi_s <= er2Dr1_enable;
169 end
171 assign SPI_SN = ~spi_s;
173 // SPI_Q_Proc
174 always @(negedge JTCK or negedge JRSTN)
175 begin
176 if (~JRSTN)
177 spi_q_dly <= 'b0;
178 else
179 if (er2Dr1_enable)
180 spi_q_dly <= {spi_q_dly[5:0],SPI_Q};
181 end
183 assign tdo_er2Dr1 = spi_q_dly[6];
185 // ------ JTDO2 MUX ------
187 assign JTDO2 = CONTROL_DATAN ? tdo_er2Cr :
188 (encodedDrSelBits == 8'b00000000) ? tdo_er2Dr0 :
189 (encodedDrSelBits == 8'b00000001) ? tdo_er2Dr1 : 1'b0;
191 assign captureDrER2 = ~JSHIFT & JCE2;
193 endmodule