typea.v

Sun, 04 Apr 2010 20:40:03 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sun, 04 Apr 2010 20:40:03 +0100
changeset 0
cd0b58aa6f83
child 26
73de224304c1
permissions
-rw-r--r--

add lm32 source

     1 // =============================================================================
     2 //                           COPYRIGHT NOTICE
     3 // Copyright 2006 (c) Lattice Semiconductor Corporation
     4 // ALL RIGHTS RESERVED
     5 // This confidential and proprietary software may be used only as authorised by
     6 // a licensing agreement from Lattice Semiconductor Corporation.
     7 // The entire notice above must be reproduced on all authorized copies and
     8 // copies may only be made to the extent permitted by a licensing agreement from
     9 // Lattice Semiconductor Corporation.
    10 //
    11 // Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
    12 // 5555 NE Moore Court                            408-826-6000 (other locations)
    13 // Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
    14 // U.S.A                                   email: techsupport@latticesemi.com
    15 // =============================================================================/
    16 //                         FILE DETAILS
    17 // Project          : LatticeMico32
    18 // File             : TYPEA.v
    19 // Description:
    20 //    This is one of the two types of cells that are used to create ER1/ER2
    21 //    register bits.
    22 // Dependencies     : None
    23 // Version          : 6.1.17
    24 //   The SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 signals of the
    25 //   dedicate logic JTAG_PORT didn't act as what their names implied.
    26 //   The SHIFT_DR_CAPTURE_DR actually acts as SHIFT_DR.
    27 //   The ENABLE_ER1/2 actually acts as SHIFT_DR_CAPTURE_DR.
    28 //   These had caused a lot of headaches for a long time and now they are
    29 //   fixed by:
    30 //   (1) Use SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 to create
    31 //       CAPTURE_DR for all typeA, typeB bits in the ER1, ER2 registers.
    32 //   (2) Use ENABLE_ER1 or the enESR, enCSR, enBAR (these 3 signals
    33 //       have the same waveform of ENABLE_ER2) directly to be the CLKEN
    34 //       of all typeA, typeB bits in the ER1, ER2 registers.
    35 //   (3) Modify typea.vhd to use only UPDATE_DR signal for the clock enable
    36 //       of the holding flip-flop.
    37 //   These changes caused ispTracy.vhd and cge.dat changes and the new
    38 //   CGE.exe version will be 1.3.5.
    39 // Version          : 7.0SP2, 3.0
    40 //                  : No Change
    41 // Version          : 3.1
    42 //                  : No Change
    43 // =============================================================================
    44 module TYPEA(
    45       input CLK,
    46       input RESET_N,
    47       input CLKEN,
    48       input TDI,
    49       output TDO,
    50       output reg DATA_OUT,
    51       input DATA_IN,
    52       input CAPTURE_DR,
    53       input UPDATE_DR
    54    );
    56   reg tdoInt;
    59   always @ (negedge CLK or negedge RESET_N)
    60   begin
    61       if (RESET_N == 1'b0)
    62          tdoInt <= 1'b0;
    63       else if (CLK == 1'b0)
    64          if (CLKEN == 1'b1)
    65             if (CAPTURE_DR == 1'b0)
    66                tdoInt <= TDI;
    67             else
    68                tdoInt <= DATA_IN;
    69   end
    71    assign TDO = tdoInt;
    73   always @ (negedge CLK or negedge RESET_N)
    74    begin
    75       if (RESET_N == 1'b0)
    76          DATA_OUT <= 1'b0;
    77       else if (CLK == 1'b0)
    78          if (UPDATE_DR == 1'b1)
    79             DATA_OUT <= tdoInt;
    80    end
    81 endmodule