er1.v

Sat, 06 Aug 2011 01:26:56 +0100

author
Philip Pemberton <philpem@philpem.me.uk>
date
Sat, 06 Aug 2011 01:26:56 +0100
changeset 27
d6c693415d59
parent 26
73de224304c1
permissions
-rwxr-xr-x

remove synthesis delay entities to ease merge

     1 //   ==================================================================
     2 //   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
     3 //   ------------------------------------------------------------------
     4 //   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
     5 //   ALL RIGHTS RESERVED 
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     7 //
     8 //   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
     9 //
    10 //   Permission:
    11 //
    12 //      Lattice Semiconductor grants permission to use this code
    13 //      pursuant to the terms of the Lattice Semiconductor Corporation
    14 //      Open Source License Agreement.  
    15 //
    16 //   Disclaimer:
    17 //
    18 //      Lattice Semiconductor provides no warranty regarding the use or
    19 //      functionality of this code. It is the user's responsibility to
    20 //      verify the userís design for consistency and functionality through
    21 //      the use of formal verification methods.
    22 //
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    25 //                  Lattice Semiconductor Corporation
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    35 //
    36 //   --------------------------------------------------------------------
    37 //                         FILE DETAILS
    38 // Project          : LatticeMico32
    39 // File             : er1.v
    40 // Description:
    41 //    This module is where the ER1 register implemented. ER1 and ER2 registers
    42 //    can be registers implemented in Lattice FPGAs using normal FPGA's
    43 //    programmable logic resources.  Once they are implemented, they can be
    44 //    accessed as if they are JTAG data registers through the FPGA JTAG port.
    45 //    In order to accessing these registers, JTAG instructions ER1(0x32) or
    46 //    ER2(0x38) needs to be written to the JTAG IR register for enabling the
    47 //    ER1/ER2 accessing logic.  The ER1 or ER2 accessing logic can only be
    48 //    enabled one at a time.  Once they are enabled, they will be disabled if
    49 //    another JTAG instruction is written into the JTAG instruction register.
    50 //    The registers allow dynamically accessing the FPGA internal information
    51 //    even when the device is running.  Therefore, they are very useful for some
    52 //    of the IP cores.  In order to let ER1/ER2 registers shared by multiple IP
    53 //    cores or other designs, there is a ER1/ER2 structure patterned by Lattice.
    54 //    The ER1/ER2 structure allows only one ER1 register but more than one ER2
    55 //    registers in an FPGA device.  Please refer to the related document for
    56 //    this patterned ER1/ER2 structure.
    57 // Dependencies     : None
    58 // Version          : 6.0.14
    59 //                  : Initial Version
    60 // Version          : 7.0SP2, 3.0
    61 //                  : No Change
    62 // Version          : 3.1
    63 //                  : No Change
    64 // =============================================================================
    65 module ER1 (input  JTCK,
    66 	    input  JTDI,
    67 	    output JTDO1,
    68 	    output reg JTDO2,
    69 	    input  JSHIFT,
    70 	    input  JUPDATE,
    71 	    input  JRSTN,
    72 	    input  JCE1,
    73 	    input [14:0] ER2_TDO,
    74 	    output reg [14:0] IP_ENABLE,
    75 	    input  ISPTRACY_ER2_TDO,
    76 	    output ISPTRACY_ENABLE,
    77 	    output CONTROL_DATAN)/* synthesis syn_hier = hard */;
    80    wire 	   controlDataNBit;
    81    wire 	   ispTracyEnableBit;
    82    wire [3:0] 	   encodedIpEnableBits;
    83    wire [9:0] 	   er1TdiBit;
    84    wire 	   captureDrER1;
    87    assign 	   JTDO1 = er1TdiBit[0];
    89    TYPEB BIT0 (.CLK(JTCK),
    90 	       .RESET_N(JRSTN),
    91 	       .CLKEN(JCE1),
    92 	       .TDI(er1TdiBit[1]),
    93 	       .TDO(er1TdiBit[0]),
    94 	       .DATA_IN(1'b0),
    95 	       .CAPTURE_DR(captureDrER1));
    97    TYPEB BIT1 (.CLK(JTCK),
    98 	       .RESET_N(JRSTN),
    99 	       .CLKEN(JCE1),
   100 	       .TDI(er1TdiBit[2]),
   101 	       .TDO(er1TdiBit[1]),
   102 	       .DATA_IN(1'b0),
   103 	       .CAPTURE_DR(captureDrER1));
   105    TYPEB BIT2 (.CLK(JTCK),
   106 	       .RESET_N(JRSTN),
   107 	       .CLKEN(JCE1),
   108 	       .TDI(er1TdiBit[3]),
   109 	       .TDO(er1TdiBit[2]),
   110 	       .DATA_IN(1'b1),
   111 	       .CAPTURE_DR(captureDrER1));
   113    TYPEA BIT3 (.CLK(JTCK),
   114 	       .RESET_N(JRSTN),
   115 	       .CLKEN(JCE1),
   116 	       .TDI(er1TdiBit[4]),
   117 	       .TDO(er1TdiBit[3]),
   118 	       .DATA_OUT(controlDataNBit),
   119 	       .DATA_IN(controlDataNBit),
   120 	       .CAPTURE_DR(captureDrER1),
   121 	       .UPDATE_DR(JUPDATE));
   123    assign CONTROL_DATAN = controlDataNBit;
   125    TYPEA BIT4 (.CLK(JTCK),
   126 	       .RESET_N(JRSTN),
   127 	       .CLKEN(JCE1),
   128 	       .TDI(er1TdiBit[5]),
   129 	       .TDO(er1TdiBit[4]),
   130 	       .DATA_OUT(ispTracyEnableBit),
   131 	       .DATA_IN(ispTracyEnableBit),
   132 	       .CAPTURE_DR(captureDrER1),
   133 	       .UPDATE_DR(JUPDATE)
   134 	       );
   136    assign ISPTRACY_ENABLE = ispTracyEnableBit;
   138    TYPEA BIT5 (.CLK(JTCK),
   139 	       .RESET_N(JRSTN),
   140 	       .CLKEN(JCE1),
   141 	       .TDI(er1TdiBit[6]),
   142 	       .TDO(er1TdiBit[5]),
   143 	       .DATA_OUT(encodedIpEnableBits[0]),
   144 	       .DATA_IN(encodedIpEnableBits[0]),
   145 	       .CAPTURE_DR(captureDrER1),
   146 	       .UPDATE_DR(JUPDATE));
   148    TYPEA BIT6 (.CLK(JTCK),
   149 	       .RESET_N(JRSTN),
   150 	       .CLKEN(JCE1),
   151 	       .TDI(er1TdiBit[7]),
   152 	       .TDO(er1TdiBit[6]),
   153 	       .DATA_OUT(encodedIpEnableBits[1]),
   154 	       .DATA_IN(encodedIpEnableBits[1]),
   155 	       .CAPTURE_DR(captureDrER1),
   156 	       .UPDATE_DR(JUPDATE));
   158    TYPEA BIT7 (.CLK(JTCK),
   159 	       .RESET_N(JRSTN),
   160 	       .CLKEN(JCE1),
   161 	       .TDI(er1TdiBit[8]),
   162 	       .TDO(er1TdiBit[7]),
   163 	       .DATA_OUT(encodedIpEnableBits[2]),
   164 	       .DATA_IN(encodedIpEnableBits[2]),
   165 	       .CAPTURE_DR(captureDrER1),
   166 	       .UPDATE_DR(JUPDATE));
   168    TYPEA BIT8 (.CLK(JTCK),
   169 	       .RESET_N(JRSTN),
   170 	       .CLKEN(JCE1),
   171 	       .TDI(er1TdiBit[9]),
   172 	       .TDO(er1TdiBit[8]),
   173 	       .DATA_OUT(encodedIpEnableBits[3]),
   174 	       .DATA_IN(encodedIpEnableBits[3]),
   175 	       .CAPTURE_DR(captureDrER1),
   176 	       .UPDATE_DR(JUPDATE)
   177 	       );
   179    assign er1TdiBit[9] = JTDI;
   180    assign captureDrER1  = !JSHIFT & JCE1;
   182    always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO)
   183    begin
   184     case (encodedIpEnableBits)
   185       4'h0: begin 
   186       		IP_ENABLE <= 15'b000000000000000;
   187       		JTDO2 <= ISPTRACY_ER2_TDO;
   188       	    end
   189       4'h1: begin
   190       		IP_ENABLE <= 15'b000000000000001;
   191       		JTDO2 <= ER2_TDO[0];
   192       	    end	
   193       4'h2: begin
   194       		IP_ENABLE <= 15'b000000000000010;
   195       		JTDO2 <= ER2_TDO[1];
   196       	    end
   197       4'h3: begin
   198       		IP_ENABLE <= 15'b000000000000100;
   199       		JTDO2 <= ER2_TDO[2];
   200       	    end
   201       4'h4: begin
   202       		IP_ENABLE <= 15'b000000000001000;
   203       		JTDO2 <= ER2_TDO[3];
   204       	    end
   205       4'h5: begin
   206       		IP_ENABLE <= 15'b000000000010000;
   207       		JTDO2 <= ER2_TDO[4];
   208       	    end
   209       4'h6: begin
   210       		IP_ENABLE <= 15'b000000000100000;
   211       		JTDO2 <= ER2_TDO[5];
   212       	    end
   213       4'h7: begin
   214       		IP_ENABLE <= 15'b000000001000000;
   215       		JTDO2 <= ER2_TDO[6];
   216       	    end
   217       4'h8: begin
   218       		IP_ENABLE <= 15'b000000010000000;
   219       		JTDO2 <= ER2_TDO[7];
   220       	    end
   221       4'h9: begin
   222       		IP_ENABLE <= 15'b000000100000000;
   223       		JTDO2 <= ER2_TDO[8];
   224       	    end
   225       4'hA: begin
   226       		IP_ENABLE <= 15'b000001000000000;
   227       		JTDO2 <= ER2_TDO[9];
   228       	    end
   229       4'hB: begin
   230       		IP_ENABLE <= 15'b000010000000000;
   231       		JTDO2 <= ER2_TDO[10];
   232       	    end
   233       4'hC: begin
   234       		IP_ENABLE <= 15'b000100000000000;
   235       		JTDO2 <= ER2_TDO[11];
   236       	    end
   237       4'hD: begin
   238       		IP_ENABLE <= 15'b001000000000000;
   239       		JTDO2 <= ER2_TDO[12];
   240       	    end
   241       4'hE: begin
   242       		IP_ENABLE <= 15'b010000000000000;
   243       		JTDO2 <= ER2_TDO[13];
   244       	    end
   245       4'hF: begin
   246       		IP_ENABLE <= 15'b100000000000000;
   247       		JTDO2 <= ER2_TDO[14];
   248       	    end
   249     endcase
   250   end
   251 endmodule